L E H R S T U H L F R R E AL Z E I T - C O M P U T E R S Y S T E M E TECHNISCHE UNIVERSITT MNCHEN UNIV.-PROF. DR. SC.

SAMARJIT CHAKRABORTY

High-Level Design Laboratory

Exercise 1: Hardware Counter

Introduction

In the High-Level Design (HLD) Laboratory, we use high-level tools for developing embedded applications. These tools allow abstracting the design process from the code implementation. In this manner, the designers can focus on the functional part of an application and do not need to spend much time in programming on their own. The necessary code is then generated by the high-level tools from abstract models of the applications (e.g., automata, conguration tables, etc.).

Figure 1: Model plant used in the HLD lab: baking line This lab is organized in three exercises and a project. The exercises should provide the necessary background for the project and consist of implementing very simple applications using the dierent tools. The project then covers the most of the lab and is about automating a model plant, specically a baking line, as shown in Fig. 1. The baking line, is comprised of a number of conveyor belts, rotary tables, silos, a mixer and a oven, that need to be controlled more details about the project will be given later.

1.1

Processing platform

In this lab we use an FPGA board from Xilinx. In particular, we use the XC5VLX110T board shown in Fig. 2, which is based on a Xilinx Virtex 5 FPGA. As a consequence, we will use Xilinx tools to develop the applications in this lab. Among these tools we have Xilinx ISE (Integrated Software Environment), Xilinx EDK (Embedded Development Kit), Xilinx SDK (Software Development Kit), etc. The FPGA board is 1

Figure 2: Xilinx FPGA board: XC5VLX110T connected to the baking line through a number of boards. In principle, these boards are responsible for adapting signals from the baking line to the FPGA. Further, one of these boards, the HLD board shown in Fig. 3, provides some hardware required in this lab such as an A/D converter, LEDs and buttons (separated from those of the FPGA board itself). IMPORTANT: The HLD board has an emergency-o switch that separates the baking line from the FPGA board. This switch should be turned o for all exercises (i.e., Exercise 1, 2 and 3) and only be turned on again for the project.

Exercise 1: Hardware Counter

The rst exercise consists of implementing an 8-bit counter in VHDL. For this purpose, we will be using the Xilinx Integrated Software Environment (ISE). The other Xilinx tools are closely related to ISE and will be introduced in the following exercises as they become necessary.

2.1

Homework

To be able to do this exercise in the lab, you should go through some documentation before coming to the rst class of the lab. Please consider that you will not have enough time to read the documentation during the class and that you should be well prepared in order to nish the exercise on time. 2

Figure 3: The HLD board Virtex-5 Family Overview: This is less critical for the lab. However, to be aware of the characteristics of the FPGA board used here, we recommend you to take a brief look at the description of the Virtex-5 family. ISE In-Depth Tutorial (version 12.3): The reading of Chapter 1, 2 and 7 of the ISE In-Depth Tutorial is required for implementing the 8-bit hardware counter (i.e., exercise 1). The purpose here is to roughly understand the development process with ISE you are not supposed to learn anything by heart. You will notice that the ISE In-Depth Tutorial is organized into three tutorial ows. These are suggested sequences of chapters to learn specic design techniques using ISE. The tutorial ow needed for the rst exercise (and in general for whole lab) is HDL Design Flow. However, for the purpose of doing exercise 1 in this lab, you do not need to read all chapters but Chapter 1, 2 and 7. The remaining chapters of the HDL Design Flow (i.e., Chapter 4, 5 and 6) are also interesting but their reading is only optional in the context of the lab.

2.2

Description

As mentioned above, an 8-bit counter should be implemented entirely in VHDL. The counter counts pulses (i.e., zero to one transitions) of an input signal. In addition, following features should be implemented: The output of the counter should be assigned to the LEDs provided on the HLD board. This way, the counting state can be visualized on the LEDs. 3

reset button pressed

FPGA - toplevel ERROR_LED_1

clk_100MHz

clk_gen

counter

LEDS

BUTTONS

8-bit counting state

start, stop, speed and reset

Figure 4: Hardware 8-bit counter The input signal should be derived from the clock signal of the FPGA board. The clock of the FPGA board has a frequency of 100MHz. As a result, to allow visualizing the counting state on the LEDs, this frequency should be scaled down to 10Hz. One of the buttons on the HLD board should be used to start the counter. The counter should start/continue counting when this button is pressed once. At overow, the counter should continue counting from zero again. A second button on the HLD board should be used to stop the counter. If this button is pressed once, the counter can be restarted by pressing the start/continue button. The stop button should not aect the current counting state. A third button should reset the counter. After a reset the counter is set at zero and it only starts counting again when the start/continue button is pressed. In addition, one of the LEDs on the FPGA board (i.e., either ERROR LED 1 or ERROR LED 2 these are the names of the signals provided in toplevel.vhd more information below) should be activated while the reset button is being pressed. A fourth button should change the frequency of the counters input signal. If this button is pressed once, the frequency of the input signal should be reduced to 1Hz. Pressing this button a second time, the input signal goes back to its initial frequency (i.e., 10Hz). This button should neither aect the counting state and it should work independently of whether the counter is currently counting or not. That is, it should be possible to change the frequency of the input signal while counting.

Figure 5: New project A schematic representation of the hardware counter is shown in Fig.4. Here two separated blocks (i.e., VHDL modules) are recommended. The block clk gen in Fig.4 generates the input signal for the second block counter, whereas the block counter implements the 8-bit hardware counter itself required in this exercise.

2.3

Getting started

To start Xilinx ISE, double click on the ISE icon that you will nd on the desktop after log-in. Further, create a new project by clicking on the menu File and then on New Project or just click on the quick access button New Project. The project name should be exercise 1 and the top-level source type should be HDL as shown in Fig. 5. Now, click on the Next button of the window of Fig. 5 and congure the project properties as shown in Fig. 6. In particular, select Family to be Virtex 5 and Device to be XC5VLX110T according to the used FPGA board. The property Package here should be set to FF1136 as shown in Fig. 6. The remaining properties are per default set to the values shown in the gure. Clicking on Next once again will bring you to the Project Summary window. There if you click on the Finish button, your project will be created. Two source les are given for this rst exercise and should be included in your VHDL project. The le toplevel.vhd is the rst hierarchy level of the project, whereas pinout.ucf (i.e., user constraints le) provides the mapping of VHDL signals to FPGA ports. To include these les, click on the menu Project and then on Add Source. Then select the toplevel.vhd from the existing exercise 1 directory in your home. This opens up the following window shown in Fig. 7, then click on the OK button of this window. You can proceed exactly in the same manner for adding pinout.ucf to your project. 5

Figure 6: Project settings

HINT: The le toplevel.vhd is read-only (i.e., you will not be able to modify it). However, it contains an entity called hld test that is necessary for performing this rst exercise. So, to make use of hld test, you will need to create your own VHDL le which you then can modify and where you can instantiate hld test accordingly. Now, you can add new source les to your project. We recommend using the structure shown in Fig. 4, which consists of two separated blocks (i.e., two separated VHDL modules) clk gen and counter. For this purpose, you will need to add two new source les. Click on the menu Project and then on New Source. The window of Fig. 8 opens up,

Figure 7: Add source le 6

Figure 8: Add new source le where you can select the name and type of the new source. After clicking on the button Next, the window of Fig. 9 appears. There you can dene input and output (I/O) ports for the module clk gen. Notice that in Fig. 9 not all I/O ports are shown that might be required for implementing the whole functionality of the counter. In a similar manner, you can proceed to add a new source le called counter according to the block diagram suggested in Fig. 4. Once you have added all source les to your project, you can edit them by double clicking on the desired le name in the Hierarchy Pane normally in the left upper corner of the ISE software framework. You can verify that your project can be synthesized using XST (Xilinx Synthesis Technology). Further, to program the FPGA, you need to generate the programming le out of your ISE project. The programming le can then

Figure 9: Dene I/O ports clk gen 7

Figure 10: Programming the FPGA board be downloaded to the FPGA using iMPACT. In order to generate the programming le, select toplevel.vhd in the Hierarchy Pane and then double click on Generate Programming File in the Processes Pane. The generation of the programming le may take a few minutes. Once the programming le has been nished without errors, you can start iMPACT by double clicking on Congure Target Device. Notice that the FPGA board should be turned on and connected to the PC using the JTAG cable. In the iMPACT Flows Pane, click on the Boundary Scan and then start the Initialize Chain process. The main windows of iMPACT should by now be updated as shown in Fig. 10. Continue assigning conguration les by clicking on Yes button in the pop-up window. A new popup window appears, where you can select the device which to assign a conguration le to. Click on the Bypass button until the device xc5vlx110t is highlighted in green. Now, select the bitstream le toplevel.bit that was generated from your project this is normally in the project directory, i.e., in the exercise 1 directory existing in your home. The device we are using supports attached PROMs, but we will not use any in this lab. Finally, right click on the icon of the xc5vlx110t device and select program. The programming takes a few seconds.