Handbook

of Signal Processing Systems

E E

Shuvra S. Bhattacharyya Ed F. Deprettere

Rainer Leupers Jarmo Takala
Editors

Handbook of Signal
Processing Systems
Foreword by S.Y. Kung

Editors
Shuvra S. Bhattacharyya
ECE Department and UMIACS
University of Maryland
2311 A. V. Williams Building
College Park
Maryland 20742
USA
ssb@umd.edu
Rainer Leupers
RWTH Aachen University
Templergraben 55
52056 Aachen
Germany
leupers@iss.rwth-aachen.de

Ed F. Deprettere
Leiden Institute of Advanced
Computer Science
Leiden Embedded Research Center
Leiden University
Niels Bohrweg 1
2333 CA Leiden
Netherlands
edd@liacs.nl
Jarmo Takala
Department of Computer Systems
Tampere University of Technology
Korkeakoulunkatu 1
33720 Tampere
Finland
jarmo.takala@tut.fi

ISBN 978-1-4419-6344-4
e-ISBN 978-1-4419-6345-1
DOI 10.1007/978-1-4419-6345-1
Springer New York Dordrecht Heidelberg London
Library of Congress Control Number: 2010932128
Springer Science+Business Media, LLC 2010
All rights reserved. This work may not be translated or copied in whole or in part without the
written permission of the publisher (Springer Science+Business Media, LLC, 233 Spring Street,
New York, NY 10013, USA), except for brief excerpts in connection with reviews or scholarly analysis.
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are not identified as such, is not to be taken as an expression of opinion as to whether or not they are
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Printed on acid-free paper
Springer is part of Springer Science+Business Media (www.springer.com)

To Milu
Shuvra Bhattacharyya
To Deirdre
Ed Deprettere
To Bettina
Rainer Leupers
To Auli
Jarmo Takala

Foreword

It gives me immense pleasure to introduce this timely handbook to the research/development communities in the field of signal processing systems (SPS). This is the
first of its kind and represents state-of-the-arts coverage of research in this field.
The driving force behind information technologies (IT) hinges critically upon the
major advances in both component integration and system integration. The major
breakthrough for the former is undoubtedly the invention of IC in the 50s by Jack
S. Kilby, the Nobel Prize Laureate in Physics 2000. In an integrated circuit, all
components were made of the same semiconductor material. Beginning with the
pocket calculator in 1964, there have been many increasingly complex applications
followed. In fact, processing gates and memory storage on a chip have since then
grown at an exponential rate, following Moores Law. (Moore himself admitted that
Moores Law had turned out to be more accurate, longer lasting and deeper in impact
than he ever imagined.) With greater device integration, various signal processing
systems have been realized for many killer IT applications. Further breakthroughs in
computer sciences and Internet technologies have also catalyzed large-scale system
integration. All these have led to todays IT revolution which has profound impacts
on our lifestyle and overall prospect of humanity. (It is hard to imagine life today
without mobiles or Internets!)
The success of SPS requires a well-concerted integrated approach from multiple disciplines, such as device, design, and application. It is important to recognize
that system integration means much more than simply squeezing components onto
a chip and, more specifically, there is a symbiotic relationship between applications
and technologies. Emerging applications, e.g. 3D TV, will prompt modern system
requirements on performance and power consumption, thus inspiring new intellectual challenges. The SPS architecture must consider overall system performance,
flexibility, and scalability, power/thermal management, hardware-software partition,
and algorithm developments. With greater integration, system designs become more
complex and there exists a huge gap between what can be theoretically designed and
what can be practically implemented. It is critical to consider, for instance, how to
deploy in concert an ever increasing number of transistors with acceptable power
consumption; and how to make hardware effective for applications and yet friendly
vii

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Foreword

to the users (easy to program). In short, major advances in SPS must arise from close
collaboration between application, hardware/architecture, algorithm, CAD, and system design.
The handbook has offered a comprehensive and up-to-date treatment of the driving forces behind SPS, current architectures and new design trends. It has also
helped seed the SPS field with innovations in applications; architectures; programming and simulation tools; and design methods. More specifically, it has provided
a solid foundation for several imminent technical areas, for instance, scalable,
reusable, and reliable system architectures, energy-efficient high-performance architectures, IP deployment and integration, on-chip interconnects, memory hierarchies, and future cloud computing. Advances in these areas will have greater impact
on future SPS technologies.
It is only fitting for Springer to produce this timely handbook. Springer has long
played a major role in academic publication on SPS, many of them have been in
close cooperation with IEEEs Signal Processing, Circuits and Systems, and Computer Societies. For nearly 20 years, I have been the Editor-in-Chief of Springers
Journal of Signal Processing Systems, considered by many as a major forum for
the SPS researchers. Nevertheless, the idea has been around for years that a singlevolume reference book would very effectively complement the journal in serving
this technical community. Then, during the 2008 IEEE Workshop on Signal Processing Systems, Washington D.C., Jennifer Evans from Springer and the editorial
team led by Prof. Shuvra Bhattacharyya met to brainstorm implementation of such
idea. The result is this handsome volume, containing contributions from renowned
pioneers and active researchers.
I congratulate the authors and editors for putting together such an outstanding
handbook. It is truly a timely contribution to the exciting field of SPS for this new
decade and many decades to come.
Princeton

S.Y. Kung

Preface

This handbook provides a reference on key topics in the design, analysis, implementation, and optimization of hardware and software for signal processing systems. Plans for the handbook originated through valuable discussions with SY Kung
(Princeton University) and Jennifer Evans (Springer). Through these discussions,
we became aware of the need for an integrated reference focusing on the efficient
implementation of signal processing applications. We were then fortunate to be able
to enlist the participation of a diverse group of leading experts to contribute chapters
in a broad range of complementary topics.
We hope that this handbook will serve as a useful reference to engineering practitioners, graduate students, and researchers working in the broad area of signal
processing systems. It is also envisioned that selected chapters from the book can
be used as core readings for seminar- or project-oriented graduate courses in signal
processing systems. Given the wide range of topics covered in the book, instructors
would have significant flexibility to orient such a course towards particular themes
or levels of abstraction that they would like to emphasize.
The handbook is organized in four parts. Part I motivates representative applications that drive and apply state-of-the art methods for design and implementation of
signal processing systems; Part II discusses architectures for implementing these applications; Part III focuses on compilers and simulation tools; and Part IV describes
models of computation and their associated design tools and methodologies.
We are very grateful to all of the authors for their valuable contributions, and for
the time and effort they have devoted to preparing the chapters. We would also like
to thank Jennifer Evans and SY Kung for their encouragement of this project, which
was instrumental in getting the project off the ground, and to Jennifer Maurer for her
support and patience throughout the entire development process of the handbook.
Shuvra Bhattacharyya, Ed Deprettere
Rainer Leupers, and Jarmo Takala

ix

Contents

Part I Applications
Managing Editor: Shuvra Bhattacharyya
Signal Processing for Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
William S. Levine
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2
Brief introduction to control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1
Stability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2
Sensitivity to disturbance . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3
Sensitivity conservation . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3
Signal processing in control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1
simple cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2
Demanding cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3
Exemplary case . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4
Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5
Further reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Digital Signal Processing in Home Entertainment . . . . . . . . . . . . . . . . . . . .
Konstantinos Konstantinides
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1
The Personal Computer and the Digital Home . . . . . . . . . .
2
The Digital Photo Pipeline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1
Image Capture and Compression . . . . . . . . . . . . . . . . . . . . .
2.2
Focus and exposure control . . . . . . . . . . . . . . . . . . . . . . . . .
2.3
Pre-processing of CCD data . . . . . . . . . . . . . . . . . . . . . . . . .
2.4
White Balance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.5
Demosaicing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.6
Color transformations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.7
Post Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.8
Preview display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3
3
4
8
9
9
10
12
15
19
20
20
21
23
23
24
25
25
26
26
27
27
27
27
27

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Contents

2.9
Compression and storage . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.10
Photo Post-Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.11
Storage and Search . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.12
Digital Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3
The Digital Music Pipeline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1
Compression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2
Broadcast Radio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3
Audio Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4
The Digital Video Pipeline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1
Digital Video Broadcasting . . . . . . . . . . . . . . . . . . . . . . . . .
4.2
New Portable Digital Media . . . . . . . . . . . . . . . . . . . . . . . . .
4.3
Digital Video Recording . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4
Digital Video Processing . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.5
Digital Video Playback and Display . . . . . . . . . . . . . . . . . .
5
Sharing Digital Media in the Home . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1
DLNA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.2
Digital Media Server . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3
Digital Media Player . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6
Copy Protection and DRM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.1
Microsoft Windows DRM . . . . . . . . . . . . . . . . . . . . . . . . . .
7
Summary and Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8
To Probe Further . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

27
28
28
29
29
29
30
31
31
33
33
33
35
35
35
36
36
36
37
38
40
41
41

MPEG Reconfigurable Video Coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Marco Mattavelli, Jrn W. Janneck and Mickal Raulet
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2
Requirements and rationale of the MPEG RVC framework . . . . . . .
2.1
Limits of previous monolithic specifications . . . . . . . . . . .
2.2
Reconfigurable Video Coding specification requirements
3
Description of the standard or normative components of the
framework . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1
The toolbox library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2
The C AL Actor Language . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3
FU Network language for the codec configurations . . . . .
3.4
Bitstream syntax specification language BSDL . . . . . . . . .
3.5
Instantiation of the ADM . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.6
Case study of new and existing codec configurations . . . .
4
The procedures and tools supporting decoder implementations . . .
4.1
OpenDF supporting framework . . . . . . . . . . . . . . . . . . . . . .
4.2
CAL2HDL synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3
CAL2C synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5
Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

43
44
44
46
47
48
48
49
53
55
57
57
61
61
62
64
65
66

Contents

xiii

Signal Processing for High-Speed Links . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Naresh Shanbhag, Andrew Singer, and Hyeon-min Bae
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
2
System Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
2.1
The Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
2.2
The Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
2.3
Receiver Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
2.4
Noise Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
3
Signal Processing Methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
3.1
Modulation Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
3.2
Adaptive Equalization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
3.3
Equalization of Nonlinear Channels . . . . . . . . . . . . . . . . . . 87
3.4
Maximum Likelihood Sequence Estimation (MLSE) . . . . 88
4
Case Study of an OC-192 EDC-based Receiver . . . . . . . . . . . . . . . . 91
4.1
MLSE Receiver Architecture . . . . . . . . . . . . . . . . . . . . . . . . 91
4.2
MLSE Equalizer Algorithm and VLSI Architecture . . . . . 92
4.3
Measured Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
5
Advanced Techniques . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
5.1
FEC for Low-power Back-Plane Links . . . . . . . . . . . . . . . . 96
5.2
Coherent Detection in Optical Links . . . . . . . . . . . . . . . . . . 98
6
Concluding Remarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
7
Acknowledgements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Video Compression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Yu-Han Chen and Liang-Gee Chen
1
Evolution of Video Coding Standards . . . . . . . . . . . . . . . . . . . . . . . . 103
2
Basic Components of Video Coding Systems . . . . . . . . . . . . . . . . . . 105
2.1
Color Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
2.2
Prediction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
2.3
Transform and Quantization . . . . . . . . . . . . . . . . . . . . . . . . . 110
2.4
Entropy Coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
3
Emergent Video Applications and Corresponding Coding Systems 113
3.1
HDTV Applications and H.264/AVC . . . . . . . . . . . . . . . . . 113
3.2
Streaming and Surveillance Applications and Scalable
Video Coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
3.3
3D Video Applications and Multiview Video Coding . . . . 117
4
Conclusion and Future Directions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Low-power Wireless Sensor Network Platforms . . . . . . . . . . . . . . . . . . . . . . 123
Jukka Suhonen, Mikko Kohvakka, Ville Kaseva, Timo D. Hmlinen, and
Marko Hnnikinen
1
Characteristics of Low-power WSNs . . . . . . . . . . . . . . . . . . . . . . . . . 123
1.1
Quality of Service Requirements . . . . . . . . . . . . . . . . . . . . . 125
1.2
Services for Signal Processing Application . . . . . . . . . . . . 126

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Key Standards and Industry Specifications . . . . . . . . . . . . . . . . . . . . 127

2.1
IEEE 1451 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
2.2
WSN Communication Standards . . . . . . . . . . . . . . . . . . . . . 127
3
Software Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
3.1
Sensor Operating Systems . . . . . . . . . . . . . . . . . . . . . . . . . . 130
3.2
Middlewares . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
4
Hardware Platforms and Components . . . . . . . . . . . . . . . . . . . . . . . . 131
4.1
Communication subsystem . . . . . . . . . . . . . . . . . . . . . . . . . 131
4.2
Computing subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
4.3
Sensing subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
4.4
Power subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
4.5
Existing Platforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
5
Medium Access Control Features and Services . . . . . . . . . . . . . . . . . 136
5.1
MAC Technologies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
5.2
Unsynchronized Low Duty-Cycle MAC Protocols . . . . . . 137
5.3
Synchronized Low Duty-Cycle MAC Protocols . . . . . . . . 138
5.4
Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
6
Routing and Transport . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
6.1
Services . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
6.2
Routing Paradigms and Technologies . . . . . . . . . . . . . . . . . 144
6.3
Hybrid Transport and Routing Protocols . . . . . . . . . . . . . . 147
7
Embedded WSN Services . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
7.1
Localization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
7.2
Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
8
Experiments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
8.1
Low-Energy TUTWSN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
8.2
Low-Latency TUTWSN . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
9
Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Signal Processing for Cryptography and Security Applications . . . . . . . . . 161
Miroslav Kneevic1, Lejla Batina1 , Elke De Mulder1 , Junfeng Fan1 ,
Benedikt Gierlichs1 , Yong Ki Lee2 , Roel Maes1 and Ingrid Verbauwhede1,2
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
2
Efficient Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
2.1
Secret-Key Algorithms and Implementations . . . . . . . . . . . 162
2.2
Public-Key Algorithms and Implementations . . . . . . . . . . 164
2.3
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
3
Secure Implementations: Side Channel Attacks . . . . . . . . . . . . . . . . 170
3.1
DSP Techniques Used in Side Channel Analysis . . . . . . . . 171
4
Working with Fuzzy Secrets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
4.1
Fuzzy Secrets: Properties and Applications in
Cryptography . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
4.2
Generating Cryptographic Keys from Fuzzy Secrets . . . . . 173
5
Conclusion and Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174

Contents

xv

References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
High-Energy Physics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
Anthony Gregerson, Michael J. Schulte, and Katherine Compton
1
Introduction to High-Energy Physics . . . . . . . . . . . . . . . . . . . . . . . . . 179
2
The Compact Muon Solenoid Experiment . . . . . . . . . . . . . . . . . . . . . 182
2.1
Physics Research at the CMS Experiment . . . . . . . . . . . . . 183
2.2
Sensors and Triggering Systems . . . . . . . . . . . . . . . . . . . . . 184
2.3
The Super Large Hadron Collider Upgrade . . . . . . . . . . . . 188
3
Characteristics of High-Energy Physics Applications . . . . . . . . . . . 189
3.1
Technical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
3.2
Characteristics of the Development Process . . . . . . . . . . . . 192
3.3
Evolving Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
3.4
Functional Verification and Testing . . . . . . . . . . . . . . . . . . . 194
3.5
Unit Modification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
4
Techniques for Managing Design Challenges . . . . . . . . . . . . . . . . . . 196
4.1
Managing Hardware Cost and Complexity . . . . . . . . . . . . . 196
4.2
Managing Variable Latency and Variable Resource Use . . 198
4.3
Scalable and Modular Designs . . . . . . . . . . . . . . . . . . . . . . . 201
4.4
Dataflow-Based Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
4.5
Language-Independent Functional Testing . . . . . . . . . . . . . 203
4.6
Efficient Design Partitioning . . . . . . . . . . . . . . . . . . . . . . . . 204
5
Example Problems from the CMS Level-1 Trigger . . . . . . . . . . . . . . 204
5.1
Particle Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
5.2
Jet Reconstruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
6
Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
Medical Image Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
Raj Shekhar, Vivek Walimbe, and William Plishker
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
2
Medical Imaging Modalities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
2.1
Radiography . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
2.2
Computed Tomography . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
2.3
Nuclear Medicine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
2.4
Magnetic Resonance Imaging . . . . . . . . . . . . . . . . . . . . . . . 215
2.5
Ultrasound . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
3
Medical Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
3.1
Imaging Pipeline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
4
Image Reconstruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
4.1
CT Reconstruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
4.2
PET/SPECT Reconstruction . . . . . . . . . . . . . . . . . . . . . . . . 223
4.3
Reconstruction in MRI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
4.4
Ultrasound Reconstruction . . . . . . . . . . . . . . . . . . . . . . . . . . 224
5
Image Preprocessing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
6
Image Segmentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227

xvi

Contents

6.1
Classification of Segmentation Techniques . . . . . . . . . . . . 227
6.2
Threshold-based . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
6.3
Deformable Model-based . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
7
Image Registration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
7.1
Geometry-based . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
7.2
Intensity-based . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
7.3
Transformation Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
8
Image Visualization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
8.1
Surface Rendering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
8.2
Volume Rendering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
9
Medical Image Processing Platforms . . . . . . . . . . . . . . . . . . . . . . . . . 237
9.1
Computing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
9.2
Platforms For Accelerated Implementation . . . . . . . . . . . . 238
10
Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
11
Further Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
Signal Processing for Audio HCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
Dmitry N. Zotkin and Ramani Duraiswami
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
2
Microphone Arrays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
2.1
Source Localization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
2.2
Beamforming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
2.3
Practical Issues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
3
Audio Reproduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
3.1
Head-related transfer function . . . . . . . . . . . . . . . . . . . . . . . 248
3.2
Reverberation Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
3.3
User Motion Tracking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
3.4
Signal Processing Pipeline . . . . . . . . . . . . . . . . . . . . . . . . . . 250
4
Sample Application: Fast HRTF Measurement System . . . . . . . . . . 252
5
Sample Application: Auditory Scene Capture and Reproduction . . 256
6
Sample Application: Acoustic Field Visualization . . . . . . . . . . . . . . 260
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
Distributed Smart Cameras and Distributed Computer Vision . . . . . . . . . . 267
Marilyn Wolf and Jason Schlessman
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
2
Approaches to Computer Vision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268
3
Early Work in Distributed Smart Cameras . . . . . . . . . . . . . . . . . . . . . 270
4
Approaches to Distributed Computer Vision . . . . . . . . . . . . . . . . . . . 270
4.1
Challenges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
4.2
Platform Architectures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
4.3
Mid-Level Fusion for Gesture Recognition . . . . . . . . . . . . 275
4.4
Target-Level Fusion for Tracking . . . . . . . . . . . . . . . . . . . . 275
4.5
Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276
4.6
Sparse Camera Networks . . . . . . . . . . . . . . . . . . . . . . . . . . . 277

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5
Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279
Part II Architectures
Managing Editor: Jarmo Takala
Arithmetic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283
Oscar Gustafsson and Lars Wanhammar
1
Number representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283
1.1
Binary representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284
1.2
Twos complement representation . . . . . . . . . . . . . . . . . . . . 284
1.3
Redundant representations . . . . . . . . . . . . . . . . . . . . . . . . . . 284
1.4
Shifting and increasing the wordlength . . . . . . . . . . . . . . . . 286
1.5
Negation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
1.6
Finite-wordlength effects . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
2
Addition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290
2.1
Ripple-carry addition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
2.2
Carry-lookahead addition . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
2.3
Carry-select and conditional sum addition . . . . . . . . . . . . . 295
2.4
Multi-operand addition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296
3
Multiplication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298
3.1
Partial product generation . . . . . . . . . . . . . . . . . . . . . . . . . . . 298
3.2
Summation structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301
3.3
Vector merging adder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305
3.4
Multiply-accumulate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305
3.5
Multiplication by a constant . . . . . . . . . . . . . . . . . . . . . . . . . 305
3.6
Distributed arithmetic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308
4
Division . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312
4.1
Restoring and nonrestoring division . . . . . . . . . . . . . . . . . . 313
4.2
SRT division . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314
4.3
Speeding up division . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314
4.4
Square root extraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315
5
Floating-point representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315
5.1
Normalized representations . . . . . . . . . . . . . . . . . . . . . . . . . 316
5.2
IEEE 754 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316
5.3
Addition and subtraction . . . . . . . . . . . . . . . . . . . . . . . . . . . 317
5.4
Multiplication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318
5.5
Quantization error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318
6
Computation of elementary function . . . . . . . . . . . . . . . . . . . . . . . . . 319
6.1
CORDIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319
6.2
Polynomial and piecewise polynomial approximations . . 321
6.3
Table-based methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323
7
Further reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325

xviii

Contents

Application-Specific Accelerators for Communications . . . . . . . . . . . . . . . . 329

Yang Sun, Kiarash Amiri, Michael Brogioli, and Joseph R. Cavallaro
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330
1.1
Coarse Grain Versus Fine Grain Accelerator Architectures331
1.2
Hardware/Software Workload Partition Criteria . . . . . . . . 333
2
Hardware Accelerators for Communications . . . . . . . . . . . . . . . . . . . 335
2.1
MIMO Channel Equalization Accelerator . . . . . . . . . . . . . 336
2.2
MIMO Detection Accelerators . . . . . . . . . . . . . . . . . . . . . . . 338
2.3
Channel Decoding Accelerators . . . . . . . . . . . . . . . . . . . . . 344
3
Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360
FPGA-based DSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363
John McAllister
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363
2
FPGA Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365
2.1
FPGA Fundamentals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365
2.2
The Evolution of FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366
3
State-of-the-art FPGA Technology for DSP Applications . . . . . . . . 368
3.1
FPGA Programmable Logic Technology . . . . . . . . . . . . . . 369
3.2
FPGA DSP-datapath for DSP . . . . . . . . . . . . . . . . . . . . . . . 371
3.3
FPGA Memory Hierarchy in DSP System Implementation374
3.4
Discussion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376
4
Core-Based Implementation of FPGA DSP Systems . . . . . . . . . . . . 377
4.1
Strategy Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377
4.2
Core-based Implementation of DSP Applications from
Simulink . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378
4.3
Other Core-based Development Approaches . . . . . . . . . . . 379
5
Programmable Processor-Based FPGA DSP System Design . . . . . . 380
5.1
Application Specific Microprocessor Technology for
FPGA DSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381
5.2
Reconfigurable Processor Design for FPGA . . . . . . . . . . . 384
5.3
Discussion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386
6
System Level Design for FPGA DSP . . . . . . . . . . . . . . . . . . . . . . . . . 387
6.1
Deadalus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387
6.2
Compaan/LAURA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 388
6.3
Koski . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 388
6.4
Requirements for FPGA DSP System Design . . . . . . . . . . 389
7
Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 390
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 390
General-Purpose DSP Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393
Jarmo Takala
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393
2
Arithmetic Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395
3
Data Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395

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3.1
Fixed-Point Data Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395
3.2
Floating-Point Data Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . 402
3.3
Special Function Units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 403
4
Memory Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 404
5
Address Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 409
6
Program Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411
7
Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411
8
Further Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 412
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 412
Application Specific Instruction Set DSP Processors . . . . . . . . . . . . . . . . . . 415
Dake Liu
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415
1.1
ASIP Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415
1.2
Difference Between ASIP and General CPU . . . . . . . . . . . 416
2
DSP ASIP Design Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417
3
Architecture and Instruction Set Design . . . . . . . . . . . . . . . . . . . . . . . 420
3.1
Code Profiling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 420
3.2
Using an Available Architecture . . . . . . . . . . . . . . . . . . . . . 422
3.3
Generating a Custom Architecture . . . . . . . . . . . . . . . . . . . 425
4
Instruction Set Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 427
4.1
Instruction Set Specification . . . . . . . . . . . . . . . . . . . . . . . . . 428
4.2
Instructions for Functional Acceleration . . . . . . . . . . . . . . . 429
4.3
Instruction Coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 430
4.4
Instruction and Architecture Optimization . . . . . . . . . . . . . 431
4.5
Design Automation of an Instruction Set Architecture . . . 433
5
ASIP Instruction Set for Radio Baseband Processors . . . . . . . . . . . . 434
6
ASIP Instruction Set for Video and Image Compression . . . . . . . . . 437
7
Programming Toolchain and Benchmarking . . . . . . . . . . . . . . . . . . . 439
8
ASIP Firmware Design and Benchmarking . . . . . . . . . . . . . . . . . . . . 440
8.1
Firmware Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 441
8.2
Benchmarking and Instruction Usage Profiling . . . . . . . . . 442
9
Microarchitecture Design for ASIP . . . . . . . . . . . . . . . . . . . . . . . . . . 444
10
Further Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 446
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 446
Coarse-Grained Reconfigurable Array Architectures . . . . . . . . . . . . . . . . . 449
Bjorn De Sutter, Praveen Raghavan, Andy Lambrechts
1
Application Domain of Coarse-Grained Reconfigurable Arrays . . . 449
2
CGRA Basics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 451
3
CGRA Design Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453
3.1
Tight versus Loose Coupling . . . . . . . . . . . . . . . . . . . . . . . . 454
3.2
CGRA Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 456
3.3
Interconnects and Register Files . . . . . . . . . . . . . . . . . . . . . 461
3.4
Computational Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . 463
3.5
Memory Hierarchies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 465

xx

Contents

3.6
Compiler Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 466
Case Study: ADRES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 468
4.1
Mapping Loops onto ADRES CGRAs . . . . . . . . . . . . . . . . 469
4.2
ADRES Design Space Exploration . . . . . . . . . . . . . . . . . . . 475
5
Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 480
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 481
4

Multi-core Systems on Chip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 485

Luigi Carro and Mateus Beck Rutzig
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 485
2
Analytical Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 491
2.1
Performance Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . 492
2.2
Energy Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 496
2.3
DSP Applications on a MPSoC Organization . . . . . . . . . . 497
3
MPSoC Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500
3.1
Architecture View Point . . . . . . . . . . . . . . . . . . . . . . . . . . . . 501
3.2
Organization View Point . . . . . . . . . . . . . . . . . . . . . . . . . . . . 503
4
Successful MPSoC Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 504
4.1
OMAP Platform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 504
4.2
Samsung S3C6410/S5PC100 . . . . . . . . . . . . . . . . . . . . . . . . 506
4.3
Other MPSoCs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 508
5
Open Problems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 510
5.1
Interconnection Mechanism . . . . . . . . . . . . . . . . . . . . . . . . . 510
5.2
MPSoC Programming Models . . . . . . . . . . . . . . . . . . . . . . . 511
6
Future Research Challenges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 512
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 513
DSP Systems using Three-Dimensional (3D) Integration Technology . . . . . 515
Tong Zhang, Yangyang Pan, and Yiran Li
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 515
2
Overview of 3D Integration Technology . . . . . . . . . . . . . . . . . . . . . . 517
3
3D Logic-Memory Integration Paradigm for DSP Systems:
Rationale and Opportunities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 518
4
3D DRAM Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 521
5
Case Study I: 3D Integrated VLIW Digital Signal Processor . . . . . 523
5.1
3D DRAM Stacking in VLIW Digital Signal Processors . 523
5.2
3D DRAM L2 Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 524
5.3
Performance Evaluation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 526
6
Case Study II: 3D Integrated H.264 Video Encoder . . . . . . . . . . . . . 527
6.1
H.264 Video Encoding Basics . . . . . . . . . . . . . . . . . . . . . . . 528
6.2
3D DRAM Stacking in H.264 Video Encoder . . . . . . . . . . 530
6.3
Performance Evaluation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 535
7
Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 538
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 538

Contents

xxi

Mixed Signal Techniques . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 543

Olli Vainio
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 543
2
General Properties of Data Converters . . . . . . . . . . . . . . . . . . . . . . . . 544
2.1
Sample and Hold Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . 545
2.2
Quantization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 547
2.3
Performance Specifications . . . . . . . . . . . . . . . . . . . . . . . . . 548
3
Analog to Digital Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 549
3.1
Nyquist-Rate A/D Converters . . . . . . . . . . . . . . . . . . . . . . . 550
3.2
Oversampled A/D Converters . . . . . . . . . . . . . . . . . . . . . . . 553
4
Digital to Analog Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 557
4.1
Nyquist-rate D/A Converters . . . . . . . . . . . . . . . . . . . . . . . . 558
4.2
Oversampled D/A Converters . . . . . . . . . . . . . . . . . . . . . . . 560
5
Switched-Capacitor Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 561
5.1
Amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 562
5.2
Switched Capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 562
5.3
Integrators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 563
5.4
First-Order Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 564
5.5
Second-Order Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 565
5.6
Differential SC Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . 566
5.7
Performance Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . 567
6
Frequency Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 567
6.1
Phase-Locked Loops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 567
6.2
Fractional-N Frequency Synthesis . . . . . . . . . . . . . . . . . . . . 568
6.3
Delay-Locked Loops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 569
6.4
Direct Digital Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . 570
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 571
Part III Programming and Simulation Tools
Managing Editor: Rainer Leupers
C Compilers and Code Optimization for DSPs . . . . . . . . . . . . . . . . . . . . . . . 575
Bjrn Franke
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 575
2
C Compilers for DSPs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 576
2.1
Industrial Context . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 576
2.2
Compiler and Language Extensions . . . . . . . . . . . . . . . . . . 577
2.3
Compiler Benchmarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 578
3
Code Optimizations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 579
3.1
Address Code Optimizations . . . . . . . . . . . . . . . . . . . . . . . . 580
3.2
Control Flow Optimizations . . . . . . . . . . . . . . . . . . . . . . . . . 582
3.3
Loop Optimizations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 585
3.4
Memory Optimizations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 592
3.5
Optimizations for Code Size . . . . . . . . . . . . . . . . . . . . . . . . 594
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 598

xxii

Contents

Compiling for VLIW DSPs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 603

Christoph W. Kessler
1
VLIW DSP architecture concepts and resource modeling . . . . . . . . 603
2
Case study: TI C62x DSP processor family . . . . . . . . . . . . . . . . . . . 611
3
VLIW DSP code generation overview . . . . . . . . . . . . . . . . . . . . . . . . 615
4
Instruction selection and resource allocation . . . . . . . . . . . . . . . . . . . 617
5
Cluster assignment for clustered VLIW architectures . . . . . . . . . . . 619
6
Register allocation and generalized spilling . . . . . . . . . . . . . . . . . . . . 620
7
Instruction scheduling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 622
7.1
Local instruction scheduling . . . . . . . . . . . . . . . . . . . . . . . . 623
7.2
Modulo scheduling for loops . . . . . . . . . . . . . . . . . . . . . . . . 624
7.3
Global instruction scheduling . . . . . . . . . . . . . . . . . . . . . . . 627
7.4
Generated instruction schedulers . . . . . . . . . . . . . . . . . . . . . 629
8
Integrated code generation for VLIW and clustered VLIW . . . . . . . 630
9
Concluding remarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 633
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 634
Software Compilation Techniques for MPSoCs . . . . . . . . . . . . . . . . . . . . . . . 639
Rainer Leupers, Weihua Sheng, Jeronimo Castrillon
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 640
1.1
MPSoCs and MPSoC Compilers . . . . . . . . . . . . . . . . . . . . . 640
1.2
Challenges of Building MPSoC Compilers . . . . . . . . . . . . 641
2
Foundation Elements of MPSoC Compilers . . . . . . . . . . . . . . . . . . . 642
2.1
Programming Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 643
2.2
Granularity, Parallelism and Intermediate Representation 649
2.3
Platform Description for MPSoC compilers . . . . . . . . . . . . 656
2.4
Mapping and Scheduling . . . . . . . . . . . . . . . . . . . . . . . . . . . 659
2.5
Code Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 664
3
Case Studies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 666
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 675
DSP Instruction Set Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 679
Florian Brandner and Nigel Horspool and Andreas Krall
1
Introduction/Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 679
2
Interpretive Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 681
2.1
The Classic Interpreter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 682
2.2
Threaded Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 683
2.3
Interpreter Optimizations . . . . . . . . . . . . . . . . . . . . . . . . . . . 685
3
Compiled Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 686
3.1
Basic Principles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 686
3.2
Simulation of Pipelined Processors . . . . . . . . . . . . . . . . . . . 688
3.3
Static Binary Translation . . . . . . . . . . . . . . . . . . . . . . . . . . . 689
4
Dynamically Compiled Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . 690
4.1
Basic Simulation Principles . . . . . . . . . . . . . . . . . . . . . . . . . 690
4.2
Optimizations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 690
5
Hardware Supported Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 691

Contents

xxiii

5.1
Interfacing Simulators with Hardware . . . . . . . . . . . . . . . . 691
5.2
Simulation in Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . 692
6
Generation of Instruction Set Simulators . . . . . . . . . . . . . . . . . . . . . . 694
6.1
Processor Description Languages . . . . . . . . . . . . . . . . . . . . 694
6.2
Retargetable Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 696
7
Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 697
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 702
Optimization of Number Representations . . . . . . . . . . . . . . . . . . . . . . . . . . . 707
Wonyong Sung
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 707
2
Fixed-point Data Type and Arithmetic Rules . . . . . . . . . . . . . . . . . . 708
2.1
Fixed-Point Data Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 708
2.2
Fixed-point Arithmetic Rules . . . . . . . . . . . . . . . . . . . . . . . . 710
2.3
Fixed-point Conversion Examples . . . . . . . . . . . . . . . . . . . . 711
3
Range Estimation for Integer Word-length Determination . . . . . . . . 713
3.1
L1-norm based Range Estimation . . . . . . . . . . . . . . . . . . . . 714
3.2
Simulation based Range Estimation . . . . . . . . . . . . . . . . . . 714
3.3
C++ Class based Range Estimation Utility . . . . . . . . . . . . . 715
4
Floating-point to Integer C Code Conversion . . . . . . . . . . . . . . . . . . 717
4.1
Fixed-Point Arithmetic Rules in C Programs . . . . . . . . . . . 717
4.2
Expression Conversion Using Shift Operations . . . . . . . . . 719
4.3
Integer Code Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 720
4.4
Implementation Examples . . . . . . . . . . . . . . . . . . . . . . . . . . 721
5
Word-length Optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 726
5.1
Finite Word-length Effects . . . . . . . . . . . . . . . . . . . . . . . . . . 726
5.2
Fixed-point Simulation using C++ gFix Library . . . . . . . 728
5.3
Word-length Optimization Method . . . . . . . . . . . . . . . . . . . 729
5.4
Optimization Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 735
6
Summary and Related Works . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 736
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 737
Intermediate Representations for Simulation and Implementation . . . . . . 739
Jerker Bengtsson
1
Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 739
2
Untimed Representations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 742
2.1
System Property Intervals . . . . . . . . . . . . . . . . . . . . . . . . . . . 742
2.2
Functions Driven by State Machines . . . . . . . . . . . . . . . . . . 746
3
Timed Representations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 752
3.1
Job Configuration Networks . . . . . . . . . . . . . . . . . . . . . . . . . 752
3.2
IPC Graphs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 753
3.3
Timed Configuration Graphs . . . . . . . . . . . . . . . . . . . . . . . . 758
3.4
Set of Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 758
3.5
Construction of Timed Configuration Graphs . . . . . . . . . . 762
4
Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 765
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 766

xxiv

Contents

Embedded C for Digital Signal Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . 769

Bryan E. Olivier
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 769
2
Typical DSP Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 770
3
Fixed Point Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 771
3.1
Fixed Point Sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 772
3.2
Fixed Point Constants . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 773
3.3
Fixed Point Conversions And Arithmetical Operations . . 774
3.4
Fixed Point Support Functions . . . . . . . . . . . . . . . . . . . . . . . 777
4
Memory Spaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 778
5
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 780
5.1
FIR Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 780
5.2
Sine Function in Fixed Point . . . . . . . . . . . . . . . . . . . . . . . . 781
6
Named Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 782
7
Hardware I/O Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 783
8
History and Future of Embedded C . . . . . . . . . . . . . . . . . . . . . . . . . . 785
9
Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 786
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 787
Part IV Design Methods
Managing Editor: Ed Deprettere
Signal Flow Graphs and Data Flow Graphs . . . . . . . . . . . . . . . . . . . . . . . . . 791
Keshab K. Parhi and Yanni Chen
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 791
2
Signal Flow Graphs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 792
2.1
Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 792
2.2
Transfer Function Derivation of SFG . . . . . . . . . . . . . . . . . 793
3
Data Flow Graphs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 796
3.1
Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 796
3.2
Synchronous Data Flow Graph . . . . . . . . . . . . . . . . . . . . . . 797
3.3
Construct an Equivalent Single-rate DFG from the
Multi-rate DFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 797
3.4
Equivalent Data Flow Graphs . . . . . . . . . . . . . . . . . . . . . . . 799
4
Applications to Hardware Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . 802
4.1
Unfolding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 803
4.2
Folding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 808
5
Applications to Software Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 811
5.1
Intra-iteration and Inter-iteration Precedence Constraints . 811
5.2
Definition of Critical Path and Iteration Bound . . . . . . . . . 811
5.3
Scheduling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 812
6
Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 816
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 816

Contents

xxv

Systolic Arrays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 817

Yu Hen Hu and Sun-Yuan Kung
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 817
2
Systolic Array Computing Algorithms . . . . . . . . . . . . . . . . . . . . . . . . 819
2.1
Convolution Systolic Array . . . . . . . . . . . . . . . . . . . . . . . . . 819
2.2
Linear System Solver Systolic Array . . . . . . . . . . . . . . . . . 820
2.3
Sorting Systolic Arrays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 822
3
Formal Systolic Array Design Methodology . . . . . . . . . . . . . . . . . . . 823
3.1
Loop Representation, Regular Iterative Algorithm
(RIA), and Index Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . 823
3.2
Localized and Single Assignment Algorithm Formulation 824
3.3
Data Dependence and Dependence Graph . . . . . . . . . . . . . 826
3.4
Mapping an Algorithm to a Systolic Array . . . . . . . . . . . . . 827
3.5
Linear Schedule and Assignment . . . . . . . . . . . . . . . . . . . . 829
4
Wavefront Array Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 831
4.1
Synchronous versus Asynchronous Global On-chip
Communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 831
4.2
Wavefront Array Processor Architecture . . . . . . . . . . . . . . 832
4.3
Mapping Algorithms to Wavefront Arrays . . . . . . . . . . . . . 832
4.4
Example: Wavefront Processing for Matrix Multiplication 833
4.5
Comparison of Wavefront Arrays against Systolic Arrays 835
5
Hardware Implementations of Systolic Array . . . . . . . . . . . . . . . . . . 835
5.1
Warp and iWARP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 835
5.2
SAXPY Matrix-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 837
5.3
Transputer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 839
5.4
TMS 32040 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 840
6
Recent Developments and Real World Applications . . . . . . . . . . . . . 841
6.1
Block Motion Estimation . . . . . . . . . . . . . . . . . . . . . . . . . . . 841
6.2
Wireless Communication . . . . . . . . . . . . . . . . . . . . . . . . . . . 844
7
Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 847
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 848
Decidable Signal Processing Dataflow Graphs: Synchronous and
Cyclo -Static Dataflow Graphs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 851
Soonhoi Ha and Hyunok Oh
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 851
2
SDF (Synchronous Dataflow) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 852
2.1
Static Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 853
2.2
Software Synthesis from SDF graph . . . . . . . . . . . . . . . . . . 855
2.3
Static Scheduling Techniques . . . . . . . . . . . . . . . . . . . . . . . 858
3
Cyclo-Static Data Flow (CSDF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 860
3.1
Static Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 861
3.2
Static Scheduling and Buffer Size Reduction . . . . . . . . . . . 862
3.3
Hierarchical Composition . . . . . . . . . . . . . . . . . . . . . . . . . . . 863
4
Other Decidable Dataflow Models . . . . . . . . . . . . . . . . . . . . . . . . . . . 864

xxvi

Contents

4.1
FRDF (Fractional Rate Data Flow) . . . . . . . . . . . . . . . . . . . 864
4.2
SPDF (Synchronous Piggybacked Data Flow) . . . . . . . . . . 868
4.3
SSDF (Scalable SDF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 871
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 873
Mapping Decidable Signal Processing Graphs into FPGA
Implementations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 875
Roger Woods
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 875
1.1
Chapter breakdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 876
2
FPGA hardware platforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 877
2.1
FPGA logic blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 878
2.2
FPGA DSP functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . 879
2.3
FPGA memory organization . . . . . . . . . . . . . . . . . . . . . . . . 880
2.4
FPGA design strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 881
3
Circuit architecture derivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 882
3.1
Basic mapping of DSP functionality to FPGA . . . . . . . . . . 883
3.2
Retiming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 884
3.3
Cut-set theorem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 885
3.4
Application to recursive structures . . . . . . . . . . . . . . . . . . . 888
4
Circuit architecture optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 890
4.1
Folding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 890
4.2
Unfolding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 892
4.3
Adaptive LMS filter example . . . . . . . . . . . . . . . . . . . . . . . . 892
4.4
Towards FPGA-based IP core generation . . . . . . . . . . . . . . 894
5
Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 895
5.1
Incorporation of FPGA cores into data flow based systems896
5.2
Application of techniques for low power FPGA . . . . . . . . 896
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 897
Dynamic and Multidimensional Dataflow Graphs . . . . . . . . . . . . . . . . . . . . 899
Shuvra S. Bhattacharyya, Ed F. Deprettere, and Joachim Keinert
1
Multidimensional synchronous data flowgraphs (MDSDF) . . . . . . . 899
1.1
Basics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 900
1.2
Arbitrary sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 901
1.3
A complete example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 904
1.4
Initial tokens on arcs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 905
2
Windowed synchronous/cyclo-static dataflow . . . . . . . . . . . . . . . . . . 906
2.1
Windowed synchronous/cyclo-static data flow graphs . . . 907
2.2
Balance equations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 909
3
Motivation for dynamic DSP-oriented dataflow models . . . . . . . . . . 912
4
Boolean dataflow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 914
5
The Stream-based Function Model . . . . . . . . . . . . . . . . . . . . . . . . . . . 916
5.1
The concern for an actor model . . . . . . . . . . . . . . . . . . . . . . 916
5.2
The stream-based function actor model . . . . . . . . . . . . . . . 917
5.3
The formal model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 918

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5.4
Communication and scheduling . . . . . . . . . . . . . . . . . . . . . . 919
5.5
Composition of SBF actors . . . . . . . . . . . . . . . . . . . . . . . . . 920
6
CAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 921
7
Parameterized dataflow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 923
8
Enable-invoke dataflow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 926
9
Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 928
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 929
Polyhedral Process Networks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 931
Sven Verdoolaege
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 931
2
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 932
3
Polyhedral Concepts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 934
3.1
Polyhedral Sets and Relations . . . . . . . . . . . . . . . . . . . . . . . 934
3.2
Lexicographic Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 937
3.3
Polyhedral Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 937
3.4
Piecewise Quasi-Polynomials . . . . . . . . . . . . . . . . . . . . . . . 939
3.5
Polyhedral Process Networks . . . . . . . . . . . . . . . . . . . . . . . . 939
4
Polyhedral Analysis Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 940
4.1
Parametric Integer Programming . . . . . . . . . . . . . . . . . . . . . 941
4.2
Emptiness Check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 942
4.3
Parametric Counting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 942
4.4
Computing Parametric Upper Bounds . . . . . . . . . . . . . . . . 943
4.5
Polyhedral Scanning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 944
5
Dataflow Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 946
5.1
Standard Dataflow Analysis . . . . . . . . . . . . . . . . . . . . . . . . . 946
5.2
Reuse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 949
6
Channel Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 950
6.1
FIFOs and Reordering Channels . . . . . . . . . . . . . . . . . . . . . 950
6.2
Multiplicity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 951
6.3
Internal Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 953
7
Scheduling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 954
7.1
Two Processes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 955
7.2
More than Two Processes . . . . . . . . . . . . . . . . . . . . . . . . . . . 956
7.3
Blocking Writes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 957
7.4
Linear Transformations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 959
8
Buffer Size Computation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 961
8.1
FIFOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 961
8.2
Reordering Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 962
8.3
Accuracy of the Buffer Sizes . . . . . . . . . . . . . . . . . . . . . . . . 964
9
Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 964
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 964

xxviii

Contents

Kahn Process Networks and a Reactive Extension . . . . . . . . . . . . . . . . . . . . 967

Marc Geilen and Twan Basten
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 968
2
Denotational Semantics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 971
3
Operational Semantics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 973
3.1
Labeled transition systems . . . . . . . . . . . . . . . . . . . . . . . . . . 974
3.2
Operational Semantics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 977
4
The Kahn Principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 979
5
Analizability Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 981
6
Implementing Kahn Process Networks . . . . . . . . . . . . . . . . . . . . . . . 982
6.1
Implementing Atomic Processes . . . . . . . . . . . . . . . . . . . . . 982
6.2
Correctness Criteria . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 982
6.3
Run-time Scheduling and Buffer Management . . . . . . . . . 984
7
Extensions of KPN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 987
8
Reactive Process Networks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 990
8.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 990
8.2
Design Considerations of RPN . . . . . . . . . . . . . . . . . . . . . . 994
8.3
Operational Semantics of RPN . . . . . . . . . . . . . . . . . . . . . . 996
8.4
Implementation Issues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 998
8.5
Analyzable Models Embedded in RPN . . . . . . . . . . . . . . . . 1000
9
Bibliography . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1003
Methods and Tools for Mapping Process Networks onto Multi-Processor
Systems-On-Chip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1007
Iuliana Bacivarov, Wolfgang Haid, Kai Huang, Lothar Thiele
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1007
2
KPN Design Flows for Multiprocessor Systems . . . . . . . . . . . . . . . . 1009
3
Methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1011
3.1
System Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1012
3.2
System Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1013
3.3
Performance Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1014
3.4
Design Space Exploration . . . . . . . . . . . . . . . . . . . . . . . . . . 1017
4
Specification, Synthesis, Analysis, and Optimization in DOL . . . . . 1019
4.1
Distributed Operation Layer . . . . . . . . . . . . . . . . . . . . . . . . . 1019
4.2
System Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1020
4.3
System Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1022
4.4
Performance Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1026
4.5
Design Space Exploration . . . . . . . . . . . . . . . . . . . . . . . . . . 1030
4.6
Results of the DOL Framework . . . . . . . . . . . . . . . . . . . . . . 1033
5
Concluding Remarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1036
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1037

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Integrated Modeling using Finite State Machines and Dataflow Graphs . . 1041
Joachim Falk, Joachim Keinert, Christian Haubelt, Jrgen Teich, and
Christian Zebelein
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1041
2
Modeling Approaches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1042
2.1
*charts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1042
2.2
The California Actor Language . . . . . . . . . . . . . . . . . . . . . . 1046
2.3
Extended Codesign Finite State Machines . . . . . . . . . . . . . 1049
2.4
SysteMoC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1053
3
Design Methodologies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1057
3.1
Ptolemy II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1057
3.2
The OpenDF Design Flow . . . . . . . . . . . . . . . . . . . . . . . . . . 1058
3.3
SystemCoDesigner . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1059
4
Integrated Finite State Machines for Multidimensional Data Flow . 1064
4.1
Array-OL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1065
4.2
Windowed Data Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1069
4.3
Exploiting Knowledge about the Model of Computation . 1073
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1074
Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1077

List of Contributors

Kiarash Amiri
Rice University, 6100 Main Street, Houston, TX 77005, USA, e-mail:
kiaa@rice.edu
Iuliana Bacivarov
ETH Zurich, Computer Engineering and Networks Laboratory, CH-8092 Zurich,
Switzerland, e-mail: iuliana.bacivarov@tik.ee.ethz.ch
Hyeon-min Bae
KAIST, Daejeon, South Korea, e-mail: hmbae@ee.kaist.ac.kr
Twan Basten
Eindhoven University of Technology, and Embedded Systems Institute, Den
Dolech 2, 5612AZ, Eindhoven, The Netherlands, e-mail: a.a.basten@tue.nl
Lejla Batina
Katholieke Universiteit Leuven, ESAT/COSIC and IBBT, Kasteelpark Arenberg
10, B-3001 Leuven-Heverlee, Belgium, e-mail: lejla.batina@esat.
kuleuven.be
Jerker Bengtsson
Centre for Research on Embedded Systems, Halmstad University, Box 823, 301 18
Halmstad, Sweden, e-mail: jerker.bengtsson@hh.se
Shuvra S. Bhattacharyya
University of Maryland, Dept. of Electrical and Computer Engineering, and
Institute for Advanced Computer Studies, College Park MD 20742, e-mail:
ssb@umd.edu
Florian Brandner
Institut fr Computersprachen, Technische Universitt Wien, Argentinierstrae 8,
A-1040 Wien, Austria, e-mail: brandner@complang.tuwien.ac.at
Michael Brogioli
xxxi

xxxii

List of Contributors

Freescale Semiconductor Inc., 7700 W. Parmer Lane, MD: PL63, Austin, TX

78729, USA, e-mail: michael.brogioli@freescale.com
Luigi Carro
Federal University of Rio Grande do Sul, Bento Gonalves 9500, Porto Alegre, RS,
Brazil, e-mail: carro@inf.ufrgs.br
Jeronimo Castrillon
RWTH Aachen University, Software for Systems on Silicon, Templergraben 55,
52056 Aachen, Germany, e-mail: castrill@iss.rwth-aachen.de
Joseph R. Cavallaro
Rice University, 6100 Main Street, Houston, TX 77005, USA, e-mail:
cavallar@rice.edu
Liang-Gee Chen
Graduate Institute of Electronics Engineering and Department of Electrical
Engineering, National Taiwan University, No. 1 Sec. 4 Roosevelt Rd., Taipei
10617, Taiwan, R.O.C., e-mail: lgchen@video.ee.ntu.edu.tw
Yanni Chen
Marvell Semiconductor Incorporation, 5488 Marvell Lane, Santa Clara, CA 95054,
USA, e-mail: yannic@marvell.com
Yu-Han Chen
Graduate Institute of Electronics Engineering and Department of Electrical
Engineering, National Taiwan University, No. 1 Sec. 4 Roosevelt Rd., Taipei
10617, Taiwan, R.O.C., e-mail: doliamo@video.ee.ntu.edu.tw
Katherine Compton
University of Wisconsin, Madison, WI, e-mail: kati@engr.wisc.edu
Elke De Mulder
Katholieke Universiteit Leuven, ESAT/COSIC and IBBT, Kasteelpark Arenberg
10, B-3001 Leuven-Heverlee, Belgium, e-mail: elke.demulder@esat.
kuleuven.be
Ed F. Deprettere
Leiden University, Leiden Institute of Advanced Computer Science, Niels Bohrweg
1, 2333 CA Leiden, The Netherlands, e-mail: edd@liacs.nl
Bjorn De Sutter
Computer Systems Lab, Ghent University, Sint-Pietersnieuwstraat 41, 9000 Gent,
Belgium, and Department of Electronics and Informatics, Vrije Universiteit
Brussel, Pleinlaan 2, 1050 Brussel, Belgium, e-mail: bjorn.desutter@elis.
ugent.be
Ramani Duraiswami
Department of Computer Science and Institute for Advanced Computer Studies
(UMIACS), University of Maryland, College Park MD 20742 USA, e-mail:
ramani@umiacs.umd.edu

List of Contributors

xxxiii

Joachim Falk
University of Erlangen-Nuremberg, Hardware-Software-Co-Design, Am
Weichselgarten 3, 91058 Erlangen, Germany, e-mail: joachim.falk@
informatik.uni-erlangen.de
Junfeng Fan
Katholieke Universiteit Leuven, ESAT/COSIC and IBBT, Kasteelpark Arenberg 10,
B-3001 Leuven-Heverlee, Belgium, e-mail: junfeng.fan@esat.kuleuven.
be
Bjrn Franke
Institute for Computing Systems Architecture, School of Informatics, University
of Edinburgh, 10 Crichton Street, Edinburgh, EH8 9AB, United Kingdom, e-mail:
bfranke@inf.ed.ac.uk
Marc Geilen
Eindhoven University of Technology, Den Dolech 2, 5612AZ, Eindhoven, The
Netherlands, e-mail: m.c.w.geilen@tue.nl
Benedikt Gierlichs
Katholieke Universiteit Leuven, ESAT/COSIC and IBBT, Kasteelpark Arenberg
10, B-3001 Leuven-Heverlee, Belgium, e-mail: benedikt.gierlichs@
esat.kuleuven.be
Anthony Gregerson
University of Wisconsin, Madison, WI, e-mail: agregerson@wisc.edu
Oscar Gustafsson
Division of Electronics Systems, Department of Electrical Engineering, Linkping
University, SE-581 83 Linkping, Sweden, e-mail: oscarg@isy.liu.se
Soonhoi Ha
Seoul National University, 599 Gwanak-ro, Gwanak-gu, Seoul 151-744, Korea,
e-mail: sha@snu.ac.kr
Wolfgang Haid
ETH Zurich, Computer Engineering and Networks Laboratory, CH-8092 Zurich,
Switzerland, e-mail: wolfgang.haid@tik.ee.ethz.ch
Timo D. Hmlinen
Department of Computer Systems, Tampere University of Technology, P.O. Box
553, FI-33101 Tampere, Finland, e-mail: timo.d.hamalainen@tut.fi
Marko Hnnikinen
Department of Computer Systems, Tampere University of Technology, P.O. Box
553, FI-33101 Tampere, Finland, e-mail: marko.hannikainen@tut.fi
Christian Haubelt
University of Erlangen-Nuremberg, Hardware-Software-Co-Design, Am
Weichselgarten 3, 91058 Erlangen, Germany, e-mail: christian.haubelt@
informatik.uni-erlangen.de

xxxiv

List of Contributors

Nigel Horspool
Department of Computer Science, University of Victoria, Victoria, BC V8W 3P6,
Canada, e-mail: nigelh@cs.uvic.ca
Yu Hen Hu
University of Wisconsin - Madison, Dept. Electrical and Computer Engineering,
1415 Engineering Drive, Madison, WI 53706, e-mail: hu@engr.wisc.edu
Kai Huang
ETH Zurich, Computer Engineering and Networks Laboratory, CH-8092 Zurich,
Switzerland, e-mail: kai.huang@tik.ee.ethz.ch
Jrn W. Janneck
Department of Automatic Control, Lund University, SE-221 00 Lund, Sweden,
e-mail: jwj@acm.org
Ville Kaseva
Department of Computer Systems, Tampere University of Technology, P.O. Box
553, FI-33101 Tampere, Finland, e-mail: ville.kaseva@tut.fi
Joachim Keinert
Fraunhofer Institute for Integrated Circuits IIS, Am Wolfsmantel 33, 91058
Erlangen, Germany, e-mail: joachim.keinert@iis.fraunhofer.de
Christoph W. Kessler
Dept. of Computer and Information Science, Linkping University, 58183
Linkping, Sweden, e-mail: chrke@ida.liu.se
Miroslav Knezevic
Katholieke Universiteit Leuven, ESAT/COSIC and IBBT, Kasteelpark Arenberg
10, B-3001 Leuven-Heverlee, Belgium, e-mail: miroslav.knezevic@esat.
kuleuven.be
Mikko Kohvakka
Department of Computer Systems, Tampere University of Technology, P.O. Box
553, FI-33101 Tampere, Finland, e-mail: mikko.kohvakka@tut.fi
Konstantinos Konstantinides,
x e-mail: k.konstantinides@ieee.org
Andreas Krall
Institut fr Computersprachen, Technische Universitt Wien, Argentinierstrae 8,
A-1040 Wien, Austria, e-mail: andi@complang.tuwien.ac.at
S. Y. Kung
Princeton University, e-mail: kung@princeton.edu
Andy Lambrechts
IMEC, Kapeldreef 75, 3001 Heverlee, Belgium, e-mail: lambreca@imec.be
Yong Ki Lee
University of California, Los Angeles, Electrical Engineering, 420 Westwood

List of Contributors

xxxv

Plaza, Los Angeles, CA 90095-1594, USA, e-mail: jfirst@ee.ucla.edu

Rainer Leupers
RWTH Aachen University, Software for Systems on Silicon, Templergraben 55,
52056 Aachen, Germany, e-mail: leupers@iss.rwth-aachen.de
William S. Levine
Department of ECE, University of Maryland, College Park, MD 20742, USA,
e-mail: wsl@eng.umd.edu
Yiran Li
Rensselaer Polytechnic Institute, 110 8th street, Troy, NY 12180, USA, e-mail:
liy16@rpi.edu
Dake Liu
Department of Electrical Engineering, Linkping University, 58183, Linkping,
Sweden, e-mail: dake.liu@liu.se
Roel Maes
Katholieke Universiteit Leuven, ESAT/COSIC and IBBT, Kasteelpark Arenberg 10,
B-3001 Leuven-Heverlee, Belgium, e-mail: roel.maes@esat.kuleuven.be
Marco Mattavelli
GR-SCI-MM, EPFL, CH-1015 Lausanne, Switzerland, e-mail: marco.
mattavelli@epfl.ch
John McAllister
Institute of Electronics, Communications and Information Technology (ECIT),
Queens University Belfast, Northern Ireland Science Park, Queens Road, Queens
Island, Belfast BT 9DT, UK, e-mail: j.mcallister@ecit.qub.ac.uk
Hyunok Oh
Hanyang University, Haengdangdong, Seongdonggu, Seoul 133-791, Korea,
e-mail: hoh@hanyang.ac.kr
Bryan E. Olivier
ACE Associated Compiler Experts bv., De Ruyterkade 113, 1011 AB Amsterdam,
The Netherlands, e-mail: bryan@ace.nl
Yangyang Pan
Rensselaer Polytechnic Institute, 110 8th street, Troy, NY 12180, USA, e-mail:
pany2@rpi.edu
Keshab K. Parhi
University of Minnesota, Dept. of Elect. & Comp. Eng., Minneapolis, MN 55455,
USA, e-mail: parhi@umn.edu
William Plishker
Department of Diagnostic Radiology and Nuclear Medicine, University of
Maryland, 22 S. Greene St., Baltimore, MD 21201, USA, and Department of

xxxvi

List of Contributors

Electrical and Computer Engineering, University of Maryland, 1423 AV Williams,

College Park, MD 20742, USA, e-mail: plishker@umd.edu
Praveen Raghavan
IMEC, Kapeldreef 75, 3001 Heverlee, Belgium, e-mail: ragha@imec.be
Mickal Raulet
IETR/INSA Rennes, F-35708, Rennes, France, e-mail: mickael.raulet@
insa-rennes.fr
Mateus Rutzig
Federal University of Rio Grande do Sul, Bento Gonalves 9500, Porto Alegre, RS,
Brazil, e-mail: mbrutzig@inf.ufrgs.br
Jason Schlessman
Department of Electrical Engineering, Princeton University, Engineering Quad,
Princeton, NJ 08544, USA, e-mail: jschlessman@gmail.com
Michael Schulte
University of Wisconsin, Madison, WI, e-mail: schulte@engr.wisc.edu
Naresh Shanbhag
University of Illinois at Urbana-Champaign, Urbana, e-mail: shanbhag@
illinois.edu
Raj Shekhar
Department of Diagnostic Radiology and Nuclear Medicine, University of
Maryland, 22 S. Greene St., Baltimore, MD 21201, USA, e-mail: rshekhar@
umm.edu
Weihua Sheng
RWTH Aachen University, Software for Systems on Silicon, Templergraben 55,
52056 Aachen, Germany, e-mail: sheng@iss.rwth-aachen.de
Andrew Singer
University of Illinois at Urbana-Champaign, Urbana, e-mail: acsinger@
illinois.edu
Jukka Suhonen
Department of Computer Systems, Tampere University of Technology, P.O. Box
553, FI-33101 Tampere, Finland, e-mail: jukka.suhonen@tut.fi
Yang Sun
Rice University, 6100 Main Street, Houston, TX 77005, USA, e-mail:
ysun@rice.edu
Wonyong Sung
School of Electrical Engineering, Seoul National University, 599 Gwanangno,
Gwanak-gu, Seoul, 151-744, Republic Of Korea, e-mail: wysung@snu.ac.kr
Jarmo Takala
Department of Computer Systems, Tampere University of Technology, P.O. Box

List of Contributors

xxxvii

553, FI-33101 Tampere, Finland, e-mail: jarmo.takala@tut.fi

Jrgen Teich
University of Erlangen-Nuremberg, Hardware-Software-Co-Design, Am
Weichselgarten 3, 91058 Erlangen, Germany, e-mail: teich@informatik.
uni-erlangen.de
Lothar Thiele
ETH Zurich, Computer Engineering and Networks Laboratory, CH-8092 Zurich,
Switzerland, e-mail: lothar.thiele@tik.ee.ethz.ch
Olli Vainio
Department of Computer Systems, Tampere University of Technology, P.O. Box
553, FI-33101 Tampere, Finland, e-mail: olli.vainio@tut.fi
Ingrid Verbauwhede
Katholieke Universiteit Leuven, ESAT/COSIC and IBBT, Kasteelpark Arenberg
10, B-3001 Leuven-Heverlee, Belgium, e-mail: ingrid.verbauwhede@
esat.kuleuven.be
Sven Verdoolaege
Katholieke Universiteit Leuven, Department of Computer Science, Celestijnenlaan
200A, B-3001 Leuven, Belgium, e-mail: sven@cs.kuleuven.be
Vivek Walimbe
GE Healthcare, 3000 N.Grandview Blvd., W-622, Waukesha, WI 53188, USA,
e-mail: vivekwalimbe@ieee.org
Lars Wanhammar
Division of Electronics Systems, Department of Electrical Engineering, Linkping
University, SE-581 83 Linkping, Sweden, e-mail: larsw@isy.liu.se
Marilyn Wolf
School of Electrical and Computer Engineering, Georgia Institute of Technology,
777 Atlantic Drive NW, Atlanta, GA 30332-0250, USA, e-mail: wolf@ece.
gatech.edu
Roger Woods
ECIT, Queens University Belfast, Queens Island, Queens Road, Belfast, BT3
9DT, UK, e-mail: r.woods@qub.ac.uk
Christian Zebelein
University of Erlangen-Nuremberg, Hardware-Software-Co-Design, Am
Weichselgarten 3, 91058 Erlangen, Germany, e-mail: christian.zebelein@
informatik.uni-erlangen.de
Tong Zhang
Rensselaer Polytechnic Institute, 110 8th street, Troy, NY 12180, USA, e-mail:
tzhang@ecse.rpi.edu
Dmitry N. Zotkin

xxxviii

List of Contributors

Institute for Advanced Computer Studies (UMIACS), University of Maryland,

College Park MD 20742 USA, e-mail: dz@umiacs.umd.edu