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Iit 20
Iit 20
Fault Simulation
Problem and motivation Fault simulation algorithms
Serial Parallel Deductive Concurrent
Determine
Fault coverage - fraction (or percentage) of modeled faults detected by test vectors Set of undetected faults
Motivation
Determine test quality and in turn product quality Find undetected fault targets to improve tests
Test generator
Add vectors
Timing:
Zero-delay for combinational and synchronous circuits Mostly unit-delay for circuits with feedback
Serial Algorithm
Algorithm: Simulate fault-free circuit and save responses. Repeat following steps for each fault in the fault list:
Modify netlist by injecting one fault Simulate modified netlist, vector by vector, comparing responses with saved responses If response differs, report fault detection and suspend simulation of remaining vectors
Advantages:
Easy to implement; needs only a true-value simulator, less memory Most faults, including analog faults, can be simulated
a b
c s-a-0 detected
1 0 1
c s-a-0
0
e
0 0 s-a-1 0 0 1
c d
e f
{b0 , d0}
{b0 , d0 , f1}
a0
1 0
b0
0 1
c0
0
1 1
e0
0
a b
c d
1 1 0
e
0
1 0
g
0 1
0 0
a0
0 1 0
b0
1 1 1
0 0 1
c0
0 1 1
0 0 1
e0
0
0 1
b0
0 1
d0
1 1
f1
g0
f1
d0
Testability Measures
Controllability and observability SCOAP measures
Combinational circuit example Sequential circuit example
Purpose
Need approximate measure of:
Difficulty of setting internal circuit lines to 0 or 1 by setting primary circuit inputs Difficulty of observing internal circuit lines by observing primary outputs
Uses:
Analysis of difficulty of testing internal circuit parts redesign or add special test hardware Guidance for algorithms computing test patterns avoid using hard-to-control lines Estimation of fault coverage Estimation of test vector length
Origins Control theory Origins Rutman 1972 -- First definition of controllability Goldstein 1979 -- SCOAP
First definition of observability First elegant formulation First efficient algorithm to compute controllability and observability
Testability Analysis
Involves Circuit Topological analysis, but no test vectors and no search algorithm Static analysis Linear computational complexity Otherwise, is pointless might as well use automatic test-pattern generation and calculate: Exact fault coverage Exact test vectors
Types of Measures
SCOAP Sandia Controllability and Observability Analysis Program Combinational measures: CC0 Difficulty of setting circuit line to logic 0 CC1 Difficulty of setting circuit line to logic 1 CO Difficulty of observing a circuit line Sequential measures analogous: SC0 SC1 SO
Sequential measures:
Roughly proportional to # times a flip-flop must be clocked to control or observe given line
Error Due to Stems & Error Due to Stems & Reconverging Fanouts Reconverging Fanouts SCOAP measures wrongly assume that controlling or observing x, y, z are independent events
x y z
Sequential Example
Number in square box is level from primary outputs (POs). (CC0, CC1) CO
Assume a synchronous RESET line. CC1 (Q) = CC1 (D) + CC1 (C) + CC0 (C) + CC0 (RESET) SC1 (Q) = SC1 (D) + SC1 (C) + SC0 (C) + SC0 (RESET) + 1 CC0 (Q) = min [CC1 (RESET) + CC1 (C) + CC0 (C), CC0 (D) + CC1 (C) + CC0 (C)] SC0 (Q) is analogous CO (D) = CO (Q) + CC1 (C) + CC0 (C) + CC0 (RESET) SO (D) is analogous
D Flip-Flop Equations
After 1 Iteration
After 2 Iterations
After 3 Iterations
Origins of Stuck-Faults
Eldred (1959) First use of structural testing for the Honeywell Datamatic 1000 computer Galey, Norby, Roth (1961) First publication of stuck-at-0 and stuck-at-1 faults Seshu & Freeman (1962) Use of stuckfaults for parallel fault simulation Poage (1963) Theoretical analysis of stuck-at faults
Carry Circuit
214,863,536,422,912 patterns
Using 1 GHz ATE, would take 2.15 x 1022 years
Structural test:
No redundant adder hardware, 64 bit slices Each with 27 faults (using fault equivalence) At most 64 x 27 = 1728 faults (tests) Takes 0.000001728 s on 1 GHz ATE
Exhaustive Algorithm
For n-input circuit, generate all 2n input patterns Infeasible, unless circuit is partitioned into cones of logic, with 15 inputs
Perform exhaustive ATPG for each cone Misses faults that require specific activation patterns for multiple cones to be tested
Circuit and Binary Circuit and Binary Decision Tree Decision Tree
Algorithm Completeness
Definition: Algorithm is complete if it ultimately can search entire binary decision tree, as needed, to generate a test Untestable fault no test for it even after entire tree searched Combinational circuits only untestable faults are redundant, showing the presence of unnecessary hardware
Algebras: Roths 5-Valued Algebras: Roths 5-Valued and Muths 9-Valued and Muths 9-Valued
Failing Good Symbol Meaning Machine Machine 0 D 1/0 1 1 D 0/1 0 Roths 0 0 0/0 0 Algebra 1 1 1/1 1 X X X/X X X G0 0/X 0 X G1 1/X 1 Muths 0 Additions F0 X/0 X 1 F1 X/1 X
Roths and Muths HigherRoths and Muths HigherOrder Algebras Order Algebras
Represent two machines, which are simulated simultaneously by a computer program:
Good circuit machine (1st value) Bad circuit machine (2nd value)
Path Sensitization Method Path Sensitization Method Circuit Example Circuit Example
1 Fault Sensitization 2 Fault Propagation 3 Line Justification
Path Sensitization Method Path Sensitization Method Circuit Example Circuit Example
Try path f h k L blocked at j, since there is no way to justify the 1 on i
1 1 D D 1 0 D D D
Path Sensitization Method Path Sensitization Method Circuit Example Circuit Example
Try simultaneous paths f h k L and g i j k L blocked at k because D-frontier (chain of D or D) disappears
1 1 1 D D D D 1 D
Path Sensitization Method Path Sensitization Method Circuit Example Circuit Example
Final try: path g i j k L test found!
0 1 1 1 0 D D D D D
Branch-and-Bound Search
Efficiently searches binary search tree Branching At each tree level, selects which input variable to set to what value Bounding Avoids exploring large tree portions by artificially restricting search decision choices
Complete exploration is impractical Uses heuristics
0 1 D D
Example Example
Step 7 Consistency Set B = 0
X 0 0 1 D 1 0 0 D
1 D D
sa1
sa1 0
sa1 0
sa1 0
D 1
0 sa1 D
0 sa1 D
Inconsistent
Example Backtrack
Need alternate propagation D-cube for v
1
0 sa1 D
0 sa1 D D
0 sa1 D D
D 1
Sequential Circuits
A sequential circuit has memory in addition to combinational logic. Test for a fault in a sequential circuit is a sequence of vectors, which
Initializes the circuit to a known state Activates the fault, and Propagates the fault effect to a primary output
X Cn+1 1
Time-Frame Expansion
An-1 Bn-1
1 1
Time-frame -1
s-a-0 1 D D X X
An Bn
1 1
Time-frame 0
s-a-0 1 D D D 1
Cn-1
X
Cn
1
Cn+1
1
Combinational logic
Sn-1
X
Combinational logic
Sn
D
FF
Concept of Time-Frames
If the test sequence for a single stuck-at fault contains n vectors,
Replicate combinational logic block n times Place fault in each block Generate a test for the multiple stuck-at fault using combinational ATPG with 9-valued logic Fault
Unknown or given Init. state Vector -n+1 Vector -1 Vector 0
Comb. block
State variables
Timeframe -1 PO -1
Timeframe 0 PO 0
Next state
s-a-1
FF2
Time-frame -1
B X
Time-frame 0
B X
Time-frame -1
B X
Time-frame 0
0/1
Implementation of ATPG
Select a PO for fault detection based on drivability analysis. Place a logic value, 1/0 or 0/1, depending on fault type and number of inversions. Justify the output value from PIs, considering all necessary paths and adding backward time-frames. If justification is impossible, then use drivability to select another PO and repeat justification. If the procedure fails for all reachable POs, then the fault is untestable. If 1/0 or 0/1 cannot be justified at any PO, but 1/X or 0/X can be justified, the the fault is potentially detectable.
Definition
Design for testability (DFT) refers to those design techniques that make test generation and test application cost-effective. DFT methods for digital circuits:
Ad-hoc methods Structured methods:
Scan Partial Scan Built-in self-test (BIST) Boundary scan
Design reviews conducted by experts or design auditing tools. Disadvantages of ad-hoc DFT methods:
Experts and tools not always available. Test generation is often manual with no guarantee of high fault coverage. Design iterations may be necessary.
Scan Design
Circuit is designed using pre-specified design rules. Test structure (hardware) is added to the verified design:
Add a test control (TC) primary input. Replace flip-flops by scan flip-flops (SFF) and connect to form one or more shift registers in the test mode. Make input/output of each scan shift register controllable/observable from PI/PO.
Use combinational ATPG to obtain tests for all testable faults in the combinational logic. Add shift register tests and convert ATPG tests into scan sequences for use in manufacturing test.
Master latch
Slave latch Q
SD CK
MUX
CK
TC
TC or TCK SCANIN
Scan flip-flops can be distributed among any number of shift registers, each having a separate scanin and scanout pin. Test sequence length is determined by the longest scan shift register. Just one test control (TC) pin is essential. PI/SCANIN
Combinational logic SFF SFF TC CK SFF
M U X
PO/ SCANOUT
Scan Overheads
IO pins: Area overhead: Performance overhead:
Multiplexer delay added in combinational path; approx. two gate-delays. Flip-flop output loading due to one additional fanout; approx. 5-6%.
Power
Gate-level netlist Scan hardware insertion Scan netlist Scan chain order Design and test data for manufacturing Chip layout: Scanchain optimization, timing verification
Combinational ATPG Combinational vectors Scan sequence and test program generation
Test program
Mask data
The Slides have been collected form the work of Vishwani D. Agrawal
Thanks !!!!