Design And Application Guide For High Speed MOSFET Gate Drive Circuits

By Laszlo Balogh

ABSTRACT
The main purpose of this paper is to demonstrate a systematic approach to design high performance gate drive circuits for high speed switching applications. It is an informative collection of topics offering a one-stop-shopping to solve the most common design challenges. Thus it should be of interest to power electronics engineers at all levels of experience. The most popular circuit solutions and their performance are analyzed, including the effect of parasitic components, transient and extreme operating conditions. The discussion builds from simple to more complex problems starting with an overview of MOSFET technology and switching operation. Design procedure for ground referenced and high side gate drive circuits, AC coupled and transformer isolated solutions are described in great details. A special chapter deals with the gate drive requirements of the MOSFETs in synchronous rectifier applications. Several, step-by-step numerical design examples complement the paper.

ZET
Bu almann temel amac, yksek performans switchig uygulamalarnda, gate-drive tasarmna sistematik bir yaklam getirmektir. Bu dkman bu konularla ilgililer iin "onestop-shopping" yaklamyla en yaygn tasarm sorunlarn zmek iin hazrlanmtr.. Her dzeyde g elektronii mhendisleri bu dkmann hedef kistlesidir. Popler devre zmleri ve performanslar parazitik bileenleri, srad alma koullar vs. de dahil edilerek analiz edildi. MOSFET teknoljilerinin ve alma zelliklerinin gelenl anlatmyla basitten karmaa doru giden bir yntem kullanld. Tasarm aamalar, AC coupled ve izole edilmi transformatr zmleri ok detayl olarak aklanmtr. Senkron dorultucu uygulamalarnda MOSFETs uygulamalar ilei ilgili kap src gereksinimlerine zel bir blm de dkmanda mevcuttur.

INTRODUCTION
MOSFET is an acronym for Metal Oxide Semiconductor Field Effect Transistor and it is the key component in high frequency, high efficiency switching applications across the electronics industry. It might be surprising, but FET technology was invented in 1930, some 20 years before the bipolar transistor. The first signal level FET transistors were built in the late 1950s while power MOSFETs have been available from the mid 70s. Today, millions of MOSFET transistors are integrated in modern electronic components, from microprocessors,

through discrete power transistors. The focus of this topic is the gate drive requirements of the power MOSFET in various switch mode power conversion applications.

GR
MOSFET - Metal Oksit Alan Etkili Transistr yariletken iin bir ksaltmadr ve yksek frekansl, yksek baarml switching uygulamalar iin ok nemli bir bileendir, Srpriz olabilir ama FET Teknolojisi 1930 ylnda, icat edilmitir, Bipolar Transistorn icadndan 20 yl nce. Sinyal-level FET Transistr 1950 lerin sonuna doru retilmiken g MOSFETleri 70lerin ortalarnda kullanlmaya balanmtr. Bugn, milyonlarca MOSFET transistrleri Mikroilemciler iine yerletirilebilmektedir. Bu konunun odak noktas switch mod power conversion uygulamalarnda gate-drive gereksinimlerin nasl karlanabileceidir.

MOSFET TECHNOLOGY
The bipolar and the MOSFET transistors exploit the same operating principle. Fundamentally, both type of transistors are charge controlled devices which means that their output current is proportional to the charge established in the semiconductor by the control electrode. When these devices are used as switches, both must be driven from a low impedance source capable of sourcing and sinking sufficient current to provide for fast insertion and extraction of the controlling charge. From this point of view, the MOSFETs have to be driven just as hard during turn-on and turn-off as a bipolar transistor to achieve comparable switching speeds.

MOSFET TEKNOLOJS
Bipolar ve MOSFET transistrler temelde ayn alma prensibine sahiptirler. Temelde, iki tip transistrde yk kontroll aletlerdir. Bu ikisininde k degerleri, kontrol backlarnda toplanm olan ykle orantldr. Bu iki transistr switching uygulamalarnda kullanlrken dk empedansl, kontrol yklerin hzl bir ekilde girebilecegi ve kabilecegi , yeterli akm saglayabilecek kaynaklar tarafndan srlmelidir. Bu Bak asndan , karlatrlabilir anahtarlama hz elde edebilmek iin, MOSFET ler turn-on ve turn-off srasnda bipolar transistrler gibi hard olarak srlmelidirler. Theoretically, the switching speeds of the bipolar and MOSFET devices are close to identical, determined by the time required for the charge carriers to travel across the semiconductor region. Typical values in power devices are approximately 20 to 200 picoseconds depending on the size of the device. MOSFET The popularity and proliferation of MOSFET technology for digital and power applications is driven by two of their major advantages over the bipolar junction transistors. One of these benefits is the ease of use of the MOSFET devices in high frequency switching applications. The MOSFET transistors are simpler to drive because their control electrode is isolated from the current conducting silicon, therefore a continuous ON current is not required. Once the MOSFET transistors are turned-on, their drive current is practically zero. Also, the controlling charge and accordingly the storage time in the MOSFET transistors is greatly reduced. Teorik olarak, bipolar ve MOSFET anahtarlama hzlar ideale yakndr. Ve yk tayclarnn yar iletken blgesinin bir ucundan dierine gemesi iin gerek sreye eittir. G cihazlar

iin yaklak deger, yariletken blgenin boyutlarna da bal olmak zere 20-200 pikosaniye arasndadr.. MOSFET transistrlerin bu bu kadar popler olmalarnn sebebi bipolar transistrlere gre iki byk avantajnn olmasdr. Bunlardan birincisi yksek frekanslal swithcing uyulamalarndaki kullanm kolayldr. MOSFET transistrler daha kolay srlebilirler nk kontrol bacaklar akm iletici silikondan izole edilmi durumdadr. Bu nedenle srekli saglanan bir ON akmna ihtiya duymazlar. MOSFET transistrleri birkere ON konumuna getirildikteen sonra drive akm pratik olarak sfrdr. Ayrca kontrol ykn depolanma zaman modfet transistrlerde olduka dktr. This basically eliminates the design trade-off between on state voltage drop which is inversely proportional to excess control charge and turn-off time. As a result, MOSFET technology promises to use much simpler and more efficient drive circuits with significant economic benefits compared to bipolar devices. Furthermore, it is important to highlight especially for power applications, that MOSFETs have a resistive nature. The voltage drop across the drain source terminals of a MOSFET is a linear function of the current flowing in the semiconductor. This linear relationship is characterized by the RDS(on) of the MOSFET and known as the on-resistance. On-resistance is constant for a given gate-to-source voltage and temperature of the device. As opposed to the -2.2mV/C temperature coefficient of a p-n junction, the MOSFETs exhibit a positive temperature coefficient of approximately 0.7%/C to 1%/C. This positive temperature coefficient of the MOSFET makes it an ideal candidate for parallel operation in higher power applications where using a single device would not be practical or possible. Due to the positive TC of the channel resistance, parallel connected MOSFETs tend to share the current evenly among themselves. This current sharing works automatically in MOSFETs since the positive TC acts as a slow negative feedback system. The device carrying a higher current will heat up more dont forget that the drain to source voltages are equal and the higher temperature will increase its RDS(on) value. The increasing resistance will cause the current to decrease, therefore the temperature to drop. Eventually, an equilibrium is reached where the parallel connected devices carry similar current levels. Initial tolerance in RDS(on) values and different junction to ambient thermal resistances can cause significant up to 30% error in current distribution. Bu sayede transistorun ON durumundaki ve OFF durumundaki voltaj deiiklii tasarm sorunlarda ortadan kalkm olur. Sonu olarak MOSFET transistorler bipolar transistorlere gre daha kolay bir kullanmn yansra farkedilir bir ekonomik avantaj sunarlar. Ayrca, zellikle g uygulamalar iin, MOSFETlerin diren zellii olduunu vurgulamakta fayda var. MOSFET zerindeki voltaj d zerinden geen akmla doru orantldr. Bu lineer bamllk RDS olarak tarif edilir ve genelde on-rezistans olarak adlandrlr. On-rezistan transistorn scaklg ve gate-to-sorce voltaj iin sabittir. MOSFETler p-n baglantlarn aksine pozitif scaklk sabitine sahiptirler. Bu yaklak olarak derece bana %0.7 ile %1 arasndadr. Bu pozitif scakl sabiti (TC) nedeniyle MOSFETler tek bir aletin kullanlmasnn pratik olarak pek mmkn olmadg durumlarda, zellikle ysek g devrelerinde, paralel olarak kullanlmak iin idealdirler. Pozitif TC'leri olmas nedeni ile paralel olarak kullanlan MOSFETler akm eit olarak paylama eilimindedirler. Bu akm paylam MOSFETlerin dogas geregi otomatik olarak gerekleir. (fazla akm tayan MOSFET daha fazla snarak direnci digerlerine gre daha fazla artacaktr, direncii artnca dogal olarak zerinden geen akm azalacaktr. Sistem kendiliginden dengeye gelerek aa yukar yakn benzer iddette akm tayacaklardr.

Device types Almost all manufacturers have got their unique twist on how to manufacture the best power MOSFETs, but all of these devices on the market can be categorized into three basic device types. These are illustrated in Figure 1. Double-diffused MOS transistors were introduced in the 1970s for power applications and evolved continuously during the years. Using polycrystalline silicon gate structures and self aligning processes, higher density integration and rapid reduction in capacitances became possible. The next significant advancement was offered by the V-groove or trench technology to further increase cell density in power MOSFET devices. The better performance and denser integration dont come free however,

as trench MOS devices are more difficult to manufacture. The third device type to be mentioned here is the lateral power MOSFETs. This device type is constrained in voltage and current rating due to its inefficient utilization of the chip geometry. Nevertheless, they can provide significant benefits in low voltage applications, like in microprocessor power supplies or as synchronous rectifiers in isolated converters. The lateral power MOSFETs have significantly lower capacitances, therefore they can switch much faster and they require much less gate drive power. Cihaz tipleri Hemen hemen tm reticilerin en iyi g MOSFETleri iin kendi tasarmlar vardr. Ancak bunlarn tamam ana grupta toplanabilir. Bunlar ekil 1 gsterilmektedir. Double-diffused Mos transistrler 70lerin balarnda ortaya ukmlar ve srekli gelitirilmilerdir.Polikristal silikon kullanlarak zel gate yaplar, yksek younluklu entegreler ve kapasitanslarda hzl bir d mmkn oldu.. Sonraki nemli gelime is g MOSFETlerinde hcre yogunlugunu arttrmay salayan V-groove teknolojisi oldu. Daha yksek ve yogun MOS paralar retilebildi. Bir sonraki tip MOSFET is leteral g MOSFETleridir. Bu tip MOSFETlerin kullanm alan, ip zerinde verimli olmayan geometrik yaplarda oluturulabildii iin sadece voltaj ve akm oranlamasyla kstl kald. Ancak dk voltaj uygulamalarnda, zellikle mikroip salayclarda yada senronize rektifirerlarda, olduka baarldrlar. MOSFETler olduka dk kapasitansldr bu nedenle olduka hzl switching yapabilirler ve dk gate voltajlarnda alabilirler. MOSFET Models There are numerous models available to illustrate how the MOSFET works, nevertheless finding the right representation might be difficult. Most of the MOSFET manufacturers provide Spice and/or Saber models for their devices, but these models say very little about the application traps designers have to face in practice. They provide even fewer clues how to solve the most common design challenges. A really useful MOSFET model which would describe all important properties of the device from an application point of view would be very complicated. On the other hand, very simple and meaningful models can be derived of the MOSFET transistor if we limit the applicability of the model to certain problem areas. The first model in Figure 2 is based on the actual structure of the MOSFET device and can be used mainly for DC analysis. The MOSFET symbol in Figure 2a represents the channel resistance and the JFET corresponds to the resistance of the epitaxial layer. The length, thus the resistance of the epi layer is a function of the voltage rating of the device as high voltage MOSFETs require thicker epitaxial layer. Figure 2b can be used very effectively to model the dv/dt induced breakdown characteristic of a MOSFET. It shows both main breakdown mechanisms, namely the dv/dt induced turn-on of the parasitic bipolar transistor - present in all power MOSFETs - and the dv/dt induced turn-on of the channel as a function of the gate terminating impedance. Modern power MOSFETs are practically immune to dv/dt triggering of the parasitic npn transistor due to manufacturing improvements to reduce the resistance between the base and emitter regions. It must be mentioned also that the parasitic bipolar transistor plays another important role. Its base collector junction is the famous bodydiode of the MOSFET. Figure 2c is the switching model of the MOSFET. The most important parasitic components influencing switching performance are shown in this model. Their respective roles will be discussed in the next chapter which is dedicated to the

switching procedure of the device. MOSFET Modelleri MOSFETlerin nasl altklarn modelleyen pek ok MOSFET modeli mevcuttur. Ancak doru gsterimi bulmak zor olabilir. reticiler, rnleri iin pek ok detayl model sunmalarna ragmen , bu modeler uygulama ve tasarm srasnda karlalacak pek ok sorun hakknda pek bilgi vermezler. Bu sorunlarn czm hakknda daha da az bilgi sunarlar. Uygulama asndan pek ok detayl bilgiyi salayabilecek modeller te yandan ok karmak hale geliyor. te yandan, MOSFET transistrlerinin uygulama alann snrlayacak olursak olduka basit ve aolalabilir modeller ortaya konulabilir. Figr2 deki ilk model genel olarak DC analizinde kullanlabilir. Figr 2a daki mosfdet modeli kanal direncini ve ve bytme katmannn direncini temsil etmektedir. Uzunluk, dolaysyla katmann direnci uygulama voltaj zerinde etkilidir. Yksek voltaj MOSFETleri daha kaln bytme katmanna ihtiya duyar. Figr 2b MOSFETin breakdown karektesitigini analiz etmek iin verimli olarak kullanlabilir.

ekil 2. G MOSFET modelleri ekil 2c MOSFET bir gei modelidir. Switching performansn etkileyen grlt/parazit bileenleri bu model zerinde gsterilir. MOSFET Critical Parameters When switch mode operation of the MOSFET is considered, the goal is to switch between the lowest and highest resistance states of the device in the shortest possible time. Since the practical switching times of the MOSFETs (~10ns to 60ns) is at least two to three orders of magnitude longer than the theoretical switching time (~50ps to 200ps), it seems important to understand the discrepancy. Referring back to the MOSFET models in Figure 2, note that all models include three capacitors connected between the three terminals of the device. Ultimately, the switching performance of the MOSFET transistor is determined by how quickly the voltages can be changed across these capacitors. Therefore, in high speed switching applications, the most important parameters are the parasitic capacitances of the device. Two of these capacitors, the CGS and CGD capacitors correspond to the actual geometry of the device while the CDS capacitor is the capacitance of the base collector diode of the parasitic bipolar transistor (body diode). The CGS capacitor is formed by the overlap of the source and channel region by the gate electrode. Its value is defined by the actual geometry of the regions and stays constant (linear) under different operating conditions. The CGD capacitor is the result of two effects. Part of it is the overlap of the JFET region and the gate electrode in addition to the capacitance of the depletion region which is non-linear. The equivalent CGD capacitance is a function of the drain source voltage of the device approximated by the following formula: MOSFET Kritik Parametreler MOSFET kullanmnda switching mod gz nne alndnda ama mmkn olan en ksa zamanda mimimum ve maksimum rdire durumlar arasnda gei yapmaktr.. Teorik swithing performas (20-200 pikosaniye) ve pratik uygulamalarda elde edilen performans (1060 ns) arasndaki bu yksek farkn sebebiini anlamak nemlidir. Figr 2 deki MOSFET modellerine dnecek olursak her modelde de aletin bacaklar arasnda 3 kapasitans mevcuttur. Aletin switching performans bu kapasitrler arasnda voltajn ne kadar hzl deitiine bagldr. CGS ve CGD kapasitrleri aletin geometrisinden kaynaklanyorken CDS base kollektr diyotunun (gvde diyotu) kapasitansdr. CGS kaynak ve kanal glhelerinin st ste gelmesinden kaynaklanr ve degeri blgenin geometrisi tarafndan belirlenir, farkl operasyon koullarnda degeri sabittir. CGD iki faktrn sonucudur. Gate elektrodunun ve JFET blgesinin stste gelmesinin bu kapasitansa etkisi vardr. CGD drenaj kaynagnn fonksiyonudur ve aadaki forml ile testpit edilir

The CDS capacitor is also non-linear since it is the junction capacitance of the body diode. Its voltage dependence can be described as: Unfortunately, non of the above mentioned capacitance values are defined directly in the transistor data sheets. Their values are given indirectly by the CISS, CRSS, and COSS capacitor values and must be calculated as: Further complication is caused by the CGD capacitor in switching applications because it is placed in the feedback path between the input and output of the device. Accordingly, its effective value in switching applications can be much larger depending on the drain source voltage of the MOSFET. This phenomenon is called the Miller effect and it can be expressed as: Since the CGD and CDS capacitors are voltage dependent, the data sheet numbers are valid only at the test conditions listed. The relevant average capacitance for a certain application have to be calculated based on the required charge to establish the actual voltage change across the capacitors. For most power MOSFETs the following approximations can be useful: CDS kapasitans body diyotunun junction kapasitans oldugu iin non-lineer zllik gsterir. Bu kapasitansn voltaj bamllg aadaki gibi gsterilir.

CGD kapasitasnn aletin input ve outputu arasubdaki geridn yolunda olmasndan kaynakl iler daha da karmaklar. Switcing uygulamalarnda , bu deger mosetin drenaj voltajna bagl olarak beklenenden daha ykse olabilir. Bu durum Miller etkisi olarak adlandrlr ve aadaki gibi ifade edilir.

Daha fazla komplikasyon uygulamalar nedeniyle giri ve k aygt arasnda geribildirim yolu yerletirilir anahtarlama iinde CGD kapasitr kaynaklanr. Buna gre, uygulama gei ylnda efektif deeri ok MOSFET ve drenaj kaynak gerilimi bal olarak daha byk olabilir. Bu olgu "Miller" etkisi denir ve bu gibi ifade edilebilir:

CGD ve CDS kapasitrler volaj bagml olduklar iin, datasheetlerde verilen deerler sadece test artlarnda geerlidir. Belli uygulamalr iin ilgili avaraj kapasitans, kapasitrler arasndaki gercek voltaj deiimin gereklemesi temel alnarak hesaplanmaldr. Aadaki yaklam faydal olacaktr.

The next important parameter to mention is the gate mesh resistance, RG,I. This parasitic resistance describes the resistance associated by the gate signal distribution within the device. Its importance is very significant in high speed switching applications because it is in between the driver and the input capacitor of the device, directly impeding the switching times and the dv/dt immunity of the MOSFET. This effect is recognized in the industry, where real high speed devices like RF MOSFET transistors use metal gate electrodes instead of the higher resistance poly-silicon gate mesh for gate signal distribution. The RG,I resistance is not specified in the data sheets, but in certain applications it can be a very important characteristic of the device. In the back of this paper, Appendix A4 shows a typical measurement setup to determine the internal gate resistor value with an impedance bridge. Obviously, the gate threshold voltage is also a critical characteristic. It is important to note that the data sheet VTH value is defined at 25C and at a very low current, typically at 250A. Therefore, it is not equal to the Miller plateau region of the commonly known gate switching waveform. Another rarely mentioned fact about VTH is its approximately 7mV/C temperature coefficient. It has particular significance in gate drive circuits designed for logic level MOSFET where VTH is already low under the usual test conditions. Since MOSFETs usually operate at elevated temperatures, proper gate drive design must account for the lower VTH when turn-off time, and dv/dt immunity is calculated as shown in Appendix A and F. The trans conductance of the MOSFET is its small signal gain in the linear region of its operation. It is important to point out that every time the MOSFET is turned-on or turned-off, it must go through its linear operating mode where the current is determined by the gate-to-source voltage. The trans conductance, gfs, is the small signal relationship between drain current and gate-to-source voltage: Bahsedilmesi gerekn dier nemli bir parametrede gate-mesh direncidir (RG,I). Bu parazitik diren, alet iindeki gate sinyal dalm ile ilgilidir. Bu diren alet zerinde giri kapasitr ve diren arasnda bulunduu iin yksek hzl switing uygulamaladnda ok nem tar.

Dogrudan Mosffetin switching zamanlarn ve dv/dt orann etkiler. Bu etki endstiri tarafndan farkedildilerek gerek yksek frekansl RF mossfet transistrlerinde gate sinyal daglm iin daha yksek direnli poli-silikon gate meshleri kullanlmak yerine metal gate elektrodlar kullanlr. RG,I direnci transistorlerin data sheetlerinde gsterilmesede, baz uygulamalardan sistemin karakteristiini belirleyecek kadar nem kazanabilir. Bu yaznn sonundan EK-4 ksmnda bu i direnci empedns kprs ile lmek iin kullanlacak tipik bir kurulum anlatlmaktadr. Gate eik vaoltajnzn diger bir kritik parametre olduu aktr. Datasheetlerde VTH degerinin 25 derece scaklk ve dk akmlar iin (genel olarak 250 mikro amper) tanmland akldan karlmamaldr. Dolaysyla bu deger genel olaral gate switching waveform olarak bilinen Mller platosu blgesine eit deildir. VTH hakknda dier bir az bahsedilen bilgi ise, -7mV/C bir katsaysnn bulunduudur. VTH'n genel test koullarnn zaten altnda bulunuduu logic level MOSFETler iin tasarlanm gate-drive devrelerinde bile bu deger nemli etkilere sahiptir. Genel olarak MOSFETler belirli scaklklarda altrld iin, uygun gate-drive tasarmnnda turn-off zamannda dk VTH deeride hesaba katlmaldr. Ve dv/dt immuniy EK-A ve F de gsterildii gibi hesaplanmaldr. MOSFETin trans iletkenligi ise, lineer alma srasnda onun kk sinyal kazancdr.. MOSFET her aldnda yada kapatldnda, MOSFET lineer alma aamasndan gemelidir, ki bu aamada akm gate-sorce voltaj tarafndan belirlenir. Trans iletkenlii,gfs, iin drenaj akm ve gate-to-source vaoltaj arasnda kk bir balant vardr.:

Accordingly, the maximum current of the MOSFET in the linear region is given by: Rearranging this equation for VGS yields the approximate value of the Miller plateau as a function of the drain current. Other important parameters like the source inductance (LS) and drain inductance (LD) exhibit significant restrictions in switching performance. Typical LS and LD values are listed in the data sheets, and they are mainly dependent on the package type of the transistor. Their effects can be investigated together with the external parasitic components usually associated with layout and with accompanying external circuit elements like leakage inductance, a current sense resistor, etc. For completeness, the external series gate resistor and the MOSFET drivers output impedance must be mentioned as determining factors in high performance gate drive designs as they have a profound effect on switching speeds and consequently on switching losses. Buna gre, Mostefin liineer belgesinde maksimum akm aadaki gibi bulunur:

Denklemi VGS iin yeniden dzenlediimizde, Miller platosunun yaklak deerini drenaj akmnn bir fonksiyonu olarak elde edebiliriz.

Kaynak (LS) ve drenaj(LD) indktanslar switching performansnda nemli etkilere sahip olan dier parametrelerdir. Genel LS ve LD deerleri datasheetlerde verilmilerdir. Deerleri genel olarak transistr paketinin eitine baldr. Bu parametrelerin etkileri devredeki dier parazit kaynaklarnn etkileri (induktans elemanlar, akm sensrleri vs.) ile birlikte degerlendirilebilir. Tartmay tamamlamak gerekirse, harici gate drenleri ve MOSFET driver k empedanslar da yksek performansl switching uygulamalarnn hzlar ve sonu olarak swhitching kayplar uzerinde byk etkilere sahiptir.

SWITCHING APPLICATIONS
Now, that all the players are identified, lets investigate the actual switching behavior of the MOSFET transistors. To gain a better understanding of the fundamental procedure, the parasitic inductance of the circuit will be neglected. Later their respective effects on the basic operation will be analyzed individually. Furthermore, the following descriptions relate to clamped inductive switching because most MOSFET transistors and high speed gate drive circuits used in switch mode power supplies work in that operating mode. Figure 3. Simplified clamped inductive switching model The simplest model of clamped inductive switching is shown in Figure 3, where the DC current source represents the inductor. Its current can be considered constant during the short switching interval. The diode provides a path for the current during the off time of the MOSFET and clamps the drain terminal of the device to the output voltage symbolized by the battery.

SWITCHING UYGULAMALARI
Yukarda, swhitcing uygulamalarnn performanslar zerinde etkisi olan neredeyse tm etkenlerden bahsettik. imdi switching uygulamalarnn gerek davranlarndan bahsetmeye balayabiliriz. Temel ileyii daha iyi anlayabilmek iin, devrenin parazitik etkisi gzard edilecektir. Ancak bu etkiler daha sonra bamsz olarak tekrar ele alnacaktr. Ayrca aadaki tanmlamalar induktiv stiching iin de geerlidir, nk pekok MOSFET transistorleri ve yksek hzl gate drive devreleri switch mode g kaynaklarnda kullanlr.

ekil 3. Basitletirilmi Sabitlenmi endktif switching modeli Turn on-Sabitlenmi endktif switching'in en sade modeli Figr-3 te gsterilmitir. Burada DC akm kaynag ,indktr gsterir. Buradan salanan akm ksa swtitching sresince sabit olarak kabul edilebilir. Diyot, MOSFETin off-time' sresince akm iin bir yol belirler ve aletin drenaj terminaline balanr. k voltaj batarya ile sembolize edilir.

Turn-On procedure The turn-on event of the MOSFET transistor can be divided into four intervals as depicted in Figure 4. Figure 4. MOSFET turn-on time intervals In the first step the input capacitance of the device is charged from 0V to VTH. During this interval most of the gate current is charging the CGS capacitor. A small current is flowing through the CGD capacitor too. As the voltage increases at the gate terminal and the CGD capacitors voltage has to be slightly reduced. This period is called the turn-on delay, because both the drain current and the drain voltage of the device remain unchanged. Once the gate is charged to the threshold level, the MOSFET is ready to carry current. In the second interval

the gate is rising from VTH to the Miller plateau level, VGS,Miller. This is the linear operation of the device when current is proportional to the gate voltage. On the gate side, current is flowing into the CGS and CGD capacitors just like in the first time interval and the VGS voltage is increasing. On the output side of the device, the drain current is increasing, while the drain-to-source voltage stays at the previous level (VDS,OFF). This can be understood looking at the schematic in Figure 3. Until all the current is transferred into the MOSFET and the diode is turned-off completely to be able to block reverse voltage across its pn junction, the drain voltage must stay at the output voltage level. Turn-on MOSFET transistrn turn-on aamas ekil4 te gsterildii gibi 4 ana ksma ayrlabilir.

Figure4: MOSFET turn-on aamalarnn zamanlamalar

Ilk admda, aletin giri kapasitans 0V den V_th'ye degiir. Bu aamada gate akmnn byk ksm C_GS kapasitrn doldurmakta kullanlr. Kuk bir miktar akm ile C_GD kapasitr doldurulur. Gate terminalindeki voltaj arttka V_GD kapasitrndeki voldaj hafife der. Bu aama turn-on gecikmesi olarak adlandrlr. nk bu aamada, hem drenaj akm hemde drenaj boltaj degimeden kalr. Gate eik degerine kadar arj edildikten sonra, MOSFET akm tamaya hazr hale gelir. Bu ikinci aamada gate V_TH degerinden miller platosu seviyesine V_GS,Miller, ykselir. Bu srada alet lineer olarak alr. Yani akm gate voltajyla doru orantldr. Gate tarafnda, akm C_GS'ye ve C_GD dogru akar ve ilk aamada olduu gibi V_GS degeri artmaya artmaya balar. Output tarafnda ise drain-to-source voltaj nceki degerinde (V_DS,OFF) kalmaya devam ederken, drenaj akm artmaya devam eder. Bu durum figr3 tki emaya bakaklarak anlalabilir. Akmn tamam MOSFET iinde tranfer edile kadar ve diyot kendi pn baglantsndan terst voltaj geiini tamamen engellemek iin turn-off oluncaya kadar voltaj output voltaj seviyesinde kalmaldr. Entering into the third period of the turn-on procedure the gate is already charged to the sufficient voltage (VGS,Miller) to carry the entire load current and the rectifier diode is turned off. That now allows the drain voltage to fall. While the drain voltage falls across the device, the gate to- source voltage stays steady. This is the Miller plateau region in the gate voltage waveform. All the gate current available from the driver is diverted to discharge the CGD capacitor to facilitate the rapid voltage change across the drain-to-source terminals. The drain current of the device stays constant since it is now limited by the external circuitry, i.e. the DC current source. The last step of the turn-on is to fully enhance the conducting channel of the MOSFET by applying a higher gate drive voltage. The final amplitude of VGS determines the ultimate onresistance of the device during its on-time. Therefore, in this fourth interval, VGS is increased from VGS,Miller to its final value, VDRV. This is accomplished by charging the CGS and CGD capacitors, thus gate current is now split between the two components. While these capacitors are being charged, the drain current is still constant, and the drain-to source voltage is slightly decreasing as the on resistance of the device is being reduced. Turn-on aamasnn 3. blmne gelindiinde gate tm akm tamak iin zaten yeteri kadar (V_GS,Miller) yklenmi ve rekfayr diyotu turn-off duruma gemitir. Bu dranaj voltajnn dmesine olanak salar. Alet zerinde drenaj voltaj derken gate-to-source voltaj sabit kalmaya devam eder. Bu ksm Miller platosu blgesidir. Gate akmnn tamam C_GD kapositrn discharge ederek drain-to-sorce terminallerinde ani bir voltaj degiimine olanak saglamak iin yn deitirmitir. Harici bir devre (mesela bir dc akm kayna) tarafndan snrlandrld iin drenaj akm sabit kalmaya devam eder. Turn-on aamasnn son admnda daha yksek bir gate-drive voltaj uygulanarak MOSFETtin iletetim kapasitesi ykseltilir. V_GS'nin son degeri on-resistansnn son deerini (alr durumdayken) belirler. Bu nedenle, bu 4. aamada V_GS degeri V_GS,Miller degerinden son degerine (V_DRV) ykseltilir. Bu C_GS ve C_GD kapasitrlerinin arz edilmesi bylece gate akmnn iki parcaya blnmesi ile salanr. Bu kapasitrler arj edilirken drenaj akm hala

sabittir ve on-resistance degeri dmeye balad iin drain-tosource voltaj hafifce der. Turn-Off procedure The description of the turn-off procedure for the MOSFET transistor is basically back tracking the turn-on steps from the previous section. Start with VGS being equal to VDRV and the current in the device is the full load current represented by IDC in Figure 3. The drain-tosource voltage is being defined by IDC and the RDS(on) of the MOSFET. The four turn-off steps are shown in Figure 5. for completeness. Figure 5. MOSFET turn-off time intervals The first time interval is the turn-off delay which is required to discharge the CISS capacitance from its initial value to the Miller plateau level. During this time the gate current is supplied by the CISS capacitor itself and it is flowing through the CGS and CGD capacitors of the MOSFET. The drain voltage of the device is slightly increasing as the overdrive voltage is diminishing. The current in the drain is unchanged. In the second period, the drain-to-source voltage of the MOSFET rises from IDRDS(on) to the final VDS(off) level, where it is clamped to the output voltage by the rectifier diode according to the simplified schematic of Figure 3. During this time period which corresponds to the Miller plateau in the gate voltage waveform - the gate current is strictly the charging current of the CGD capacitor because the gate-to-source voltage is constant. This current is provided by the bypass capacitor of the power stage and it is subtracted from the drain current. The total drain current still equals the load current, i.e. the inductor current represented by the DC current source in Figure 3. Turn-Off prosedr Turn-off presedr temel olarak turn-on prosedrnn tersten ileyen hali olarak drt aamada ele alnabilir. Balanta V_gs degeri V_DRV degerine eit ve alet zerinden ekil 3 te I_DC olarak gsterilen tam-yk I_DC akm gecmektedir. Drain-to-sorce voltaj I_DC akm ve R_DS(on) direnci tarafndan belirlenmektedir. MOSFETin turn-off prosedr ekil 5 de 4 adm olarak gsterilmitir.

lk aama turn-off gecikmesidir, bu aama C_ISS kapasitrnn kendi ilk degerinden Miller platosu seviyesine kadar boalmas iin gereken sre olarak da tanmlanabilir. Bu aamada gate akm C_ISS tarafndan saglanr ve C_GS ve C_GD zerinden gaer. Drenaj voltaj hahife artarken overdrive voltaj hahife der. Drenaj akm deimez. kinci aamada, MOSFETin drain-to-source voltaj I_DRxR_DS(on) degerinden kendi son deeri olan V_DS(on) degerine ykselir. Ve burada rektifayr tarafndan ekil 3 te gsterildii gibi sabit tutulur. Bu aamada C_GD kapasitr ( Miller platosu blgesi olarak da kabul edilebilir) gate akm tarafndan arj edilir. nk vate-tosource voltaj sabittir. Bu akm bypass kapasitr tarafndan drenaj akm kullanlarak saglanr. Toplam drenaj akm hala yk akmna (mesela figr 3 te belirtilen DC akm kaynag ile gsterilen indktr akm) eittir. The beginning of the third time interval is signified by the turn-on of the diode, thus providing an alternative route to the load current. The gate voltage resumes falling from VGS,Miller to VTH. The majority of the gate current is coming out of the CGS capacitor, because the CGD capacitor is virtually fully charged from the previous time interval. The MOSFET is in linear operation and the declining gate-to-source voltage causes the drain current to decrease and reach near zero by the end of this interval. Meanwhile the drain voltage is steady at VDS(off) due to the forward biased rectifier diode. The last step of the turn-off procedure is to fully discharge the input capacitors of the device. VGS is further reduced until it reaches 0V. The bigger portion of the gate current, similarly to the third turn-off time interval, supplied by the CGS capacitor. The drain current and the drain voltage in the device are unchanged. Summarizing the results, it can be concluded that the MOSFET transistor can be switched between its highest and lowest impedance states (either turn-on or turn-off) in four time intervals. The lengths of all four time intervals are a function of the parasitic capacitance values, the required voltage change across them and the available gate drive current. This emphasizes the importance of the proper component selection and optimum gate drive design for high speed, high frequency switching applications. nc aamann balangc diyotun turn-on aamas ile iaretlenir, bylece yk akm iin alternatif bir gzergah ortaya kar. Gate volyaj VGS,miller degerinden tekrar VTH deerine der. Gate akmn byk bir ksm CGS kapasitr tarafndan salanmaktadr. nk CGD kapasitr bir nceki aamada sanal olarak tamamen arz olmutur. Bu aamada MOSFET lineer olarak alr ve den gate-to-source voltaj bu aaman sonunda drenaj akmnn neredeyse 0'a kadar dmesine sebep olur. Ayn zamanda drenaj voltaj VDS(off) rektifiayr diyotun forvard-biased olamsndan kaynakl sabittir. Turn-off presedrnn son admnda MOSFETin input kapasir tamemen boaltlr. VGS 0 volta kadar der. Gate akmn byk bir ksm 3. adma benzer bir ekilde CGS kapasitr taradndan salanr. Drenaj akm ve drenaj voltaj deimeden kalr. Sonular zetlemk gerekirse, MOSFET transistrleri kendi maksimum ve minimum empedans durumlar arasnda 4 aamada switch edilebiilir. Bu aamalar iin gerekli olan sre parazitik kapasitans degerlerinin, gerekli voltaj deiimi ve uygulanan gate akmnn bir fonksiyonudur. Bu sonu yuksek hzl switching uygulamalar ve gate- drive tasarmlar iin uygun devre elemanlarnn seimin nekadar nemli iaret etmektedir. Characteristic numbers for turn-on, turn-off delays, rise and fall times of the MOSFET

switching waveforms are listed in the transistor data sheets. Unfortunately, these numbers correspond to the specific test conditions and to resistive load, making the comparison of different manufacturers products difficult. Also, switching performance in practical applications with clamped inductive load is significantly different from the numbers given in the data sheets. Turn-on ve turn-off gecikmeleri iin karakteristik deerler (MOSFETin ykselme ve dme sreleri) transistrlerin datasheetlerinde belirtilmektedir. Ne yazkki bu deerler zel test artlarnda ve belirli resistif yklerde llmtr ve farkl reticilerin deerlerini birbiri ile karatrabilmek ok zordur. Ayrca pratikte ortaya kan deerler bu dataheetlerde verilen deerlerden olduka farkldr. Power losses The switching action in the MOSFET transistor in power applications will result in some unavoidable losses, which can be divided into two categories. The simpler of the two loss mechanisms is the gate drive loss of the device. As described before, turning-on or off the MOSFET involves charging or discharging the CISS capacitor. When the voltage across a capacitor is changing, a certain amount of charge has to be transferred. The amount of charge required to change the gate voltage between 0V and the actual gate drive voltage VDRV, is characterized by the typical gate charge vs. gate-to-source voltage curve in the MOSFET data sheet. An example is shown in Figure 6. Figure 6. Typical gate charge vs. gate-to-source voltage G Kayplar MOSFET transistrlerde swithc olay nne geemeyeceimiz bir takm g kayplar ile sonulanr. Bu kayplar iki grupta toplanabilir. Ilki gate driveda oluan kayptr. Daha nce anlatld zere MOSFETin turn on yada turn off aamasnda CISS kapasitr arj ve dearj edilir. Kapasitr zerindeki voltaj deiirken belli bir miktar yk tanmaldr. Gate voltajn oV den gercek drive voltaj olan V_DRV'ye karmak iin gerekli olan yk miktar MOSFETin datasheetinde gsterilen gate yk vs gate-tosource erisi tarafndan karakterize edilir. Bunun bir rnegi figur 6 da gsterilmitir.

ekil 6. Kap vs Tipik kaps arj iin kaynak gerilimi This graph gives a relatively accurate worst case estimate of the gate charge as a function of the gate drive voltage. The parameter used to generate the individual curves is the drain-to source off state voltage of the device. VDS(off) influences the Miller charge the area below the flat portion of the curves thus also, the total gate charge required in a switching cycle. Once the total gate charge is obtained from Figure 6, the gate charge losses can be calculated as: where VDRV is the amplitude of the gate drive waveform and fDRV is the gate drive frequency which is in most cases equal to the switching frequency. It is interesting to notice that the QGfDRV term in the previous equation gives the average bias current required to drive the gate. The power lost to drive the gate of the MOSFET transistor is dissipated in the gate drive circuitry. Referring back to Figures 4 and 5, the dissipating components can be identified as the combination of the series ohmic impedance in the gate drive path. In every switching cycle the required gate charge has to pass through the driver output impedance, the external gate resistor, and the internal gate mesh resistance. As it turns out, the power dissipation is independent of how quickly the charge is delivered through the resistors. Using the resistor designators from Figures 4 and 5, the driver power dissipation can be expressed QG.fDRV arpm

Bu grafik gate ykn gate drive voltajnn bir fonksiyonu olarak verir. Her bir egriyi retmek iin kullanlan parametre drain-to-source -off voltajdr.VDS(off) Miller sarzn (grafikte dz blgenin altnda kalan ksm) ve dolaysyla switching dongsnde gerekli olan gate ykn etkiler. Toplam yk figr 6 dan birkere elde edildikten sonra, ykteki kayp yle hesaplanabilir.

burada VDRV gate-drive genligi, fDRV gate-drive frekansdr ( genellikle switching frekansna eittir). unu belirtmek gerekir ki QG.fDRV arpm gatei srmek iin gerekliolan avaraj bias akmna eittir. Gate drive edilirken oluan g kayb gate devresinde gerekleir. Fir 4 ve 5'e geri dnecek olursak ykteki kayba neden olan paralar gate drive yolunda seri olarak empedanslar olarak dnlebilirler. Her switching dngsnde, gerekli olan gate yk src output empedansn, harici gate direncini ve dahili mesh direncini katetmek zorundadr. Oluan yk kayb ykn direncler zerinden ne kadar abuk aktndan bamszdr. Figr 4 ve 5 teki diren tasarmlar kullanlarak ykteki kayp aadaki gibi hesaplanabilir.

In the above equations, the gate drive circuit is represented by a resistive output impedance and this assumption is valid for MOS based gate drivers. When bipolar transistors are utilized in the gate drive circuit, the output impedance becomes non-linear and the equations do not yield the correct answers. It is safe to assume that with low value gate resistors (<5) most gate drive losses are dissipated in the driver. If RGATE is sufficiently large to limit IG below the output current capability of the bipolar driver, the majority of the gate drive power loss is then dissipated in RGATE. In addition to the gate drive power loss, the transistors accrue switching losses in the traditional sense due to high current and high voltage being present in the device simultaneously for a short period. In order to ensure the least amount of switching losses, the duration of this time interval must be minimized. Looking at the turn-on and turn-off procedures of the MOSFET, this condition is limited to intervals 2 and 3 of the switching transitions in both turn-on and turn-off operation. These time intervals correspond to the linear operation of the device when the gate voltage is between VTH and VGS,Miller, causing changes in the current of the device and to the Miller plateau region when the drain voltage

goes through its switching transition. his is a very important realization to properly design high speed gate drive circuits. It highlights the fact that the most important characteristic of the gate driver is its source-sink current capability around the Miller plateau voltage level. Peak current capability, which is measured at full VDRV across the drivers output impedance, has very little relevance to the actual switching performance of the MOSFET. What really determines the switching times of the device is the gate drive current capability when the gate-to source voltage, i.e. the output of the driver is at ~5V (~2.5V for logic level MOSFETs Yukardaki denklemlede, gate drive devresi resistif k empedans ile tanmlanmtr. Bu kabullenme sadece MOS tabanl gate srcleri iin geerlidir. Gate devresinde bipolar transistr kullanlaca zaman output empedans non-lineer hale gelir ve yukardaki denklemler doru sonucu vermezler. Gate direnlelrinin dk olduu durumlarda (<5Ohm) pek ok gate drive kayplar yokolur. Eger RGATE degeri IG yi bipolar srcnn output akm kapasitesinden alakta tutmak iin yeterince yksek ise gate drive kayplarnn byk ogunlugu RGATE zerinde gerekleir. Gate drive g kayplarna ek olarak, yksek akm ve yksek voltajn ok ksa zaman peryotlar iin bir arada bulunmasndan kaynakl switching kayplar yaanmas da muhtemeldir. Switching kayplarn drebilmek iin bu ksa zaman peryodunun mumkn olduunca ksaltlmas gerekmektedir. MOSFET'in tunr-on ve turn-off prosedrlerine tekrar bakacak olursak, bu durum gz nne alnarak her iki presedrnde 2. ve 3. aamalar tekrar gzden geirilmelidir. Gate voltajnn VTH ve VGS arasnda bulundugu durumlarda, transistor bu zaman aralklarnda lineer olarak alr. Yksek hzl gate drive deverlerinin tasarmnda bu iyi anlalmas gereken bir konudur. Bu gate-srcsnn en nemli karakteristiginin source-sink akm kapasitesinin miller platosu voltaj seviyesi etrafnda oldugunu iarat eder. Peak akm kapasitesi, otuput empedans zerinden tam VDRV llerek bulunur ve MOSFETin switching performas ile ok az ilgilidir. MOSFETin switching performansn belirleyen asl parametre, gate-to-soruce voltaj ( srcn k) 5V civarnda iken gate srcsnn akm kapasitesidir. A crude estimate of the MOSFET switching losses can be calculated using simplified linear approximations of the gate drive current, drain current and drain voltage waveforms during periods 2 and 3 of the switching transitions. First the gate drive currents must be determined for the second and third time intervals respectively: Assuming that IG2 charges the input capacitor of the device from VTH to VGS,Miller and IG3 is the discharge current of the CRSS capacitor while the drain voltage changes from VDS(off) to 0V, the approximate switching times are given as: MOSFET'in switching kayplar, MOSFETin 2. ve 3. zaman aralklar iin denkklemlerde gatedrive akm, deeanaj akm ve direnaj voltaj iin lineer yaklamlar yaplarak kabaca hesaplanabilir. lk olarak gate drive akmlar 2. ve 3. zaman aralklar iin srasyla aadaki gibi bulunmaldr:

IG2 nin input kapasitrn VTH den VGS,Miller seviyesine sarj ettii ve drenaj voltajnn VDS(off)tan 0V a dtgnde IG3 CRSS kapasitrn arj ettiini kabul ederek swtiching zamanlar aadaki gibi bulunabilir.

During t2 the drain voltage is VDS(off) and the current is tamping from 0A to the load current, IL while in t3 time interval the drain voltage is falling from VDS(off) to near 0V. Again, using linear approximations of the waveforms, the power loss components for the respective time intervals can be estimated: t2 sresinde drenaj voltaj VDS(off) dur ve akm 0A dan yk akm IL'ye karken t3 sresinde ise drenaj voltaj VDS(off) dan 0V seviyesine der. Yine lineer yaklamlar kullanlarak ilgili zaman aralklakrnda g kayplar aadaki gibi hesaplanr:

where T is the switching period. The total switching loss is the sum of the two loss components, which yields the following simplified expression: Even though the switching transitions are well understood, calculating the exact switching losses is almost impossible. The reason is the effect of the parasitic inductive components which will significantly alter the current and voltage waveforms, as well as the switching times during the switching procedures. Taking into account the effect of the different source and

drain inductance of a real circuit would result in second order differential equations to describe the actual waveforms of the circuit. Since the variables, including gate threshold voltage, MOSFET capacitor values, driver output impedance, etc. have a very wide tolerance, the above described linear approximation seems to be a reasonable enough compromise to estimate switching losses in the MOSFET. Burada T switching peryodudur. Toplam switching kaybbasitletirilmi ifadeden hesaplanacag gibi iki kayp eidinin toplamdr.

Switching sreleri aslnda iyi anlalm olmasna ragmen, gerek switching kayplarn hesaplayabilmek neredeyse imkanszdr. Bunun sebebi akm ve voltaj degerini ve hatta siwitching zamann ok belirgin bir dzeyde etkileyebilen parazitik etkilerdir. Deiik kaynaklarn devre zerindeki etkileri ikinci dereceden difreansiyel denklemler ile ifade edilebilir. Denklemdeki gate voltaj eik degeri, kapasitr degerleri src in output empedans ve dier degikenler ok deiebilir ve geni toleransa sahip olduklarndan yukardaki denklemde uygulanan lineer basitletirmeler yeterince uygulanabilir ve mantkl hale gelmektedir. Effects of parasitic components The most profound effect on switching performance is exhibited by the source inductance. There are two sources for parasitic source inductance in a typical circuit, the source bond wire neatly integrated into the MOSFET package and the printed circuit board wiring inductance between the source lead and the common ground. This is usually referenced as the negative electrode of the high frequency filter capacitor around the power stage and the bypass capacitor of the gate driver. Current sense resistors in series with the source can add additional inductance to the previous two components. There are two mechanisms in the switching procedure which involve the source inductor. At the beginning of the switching transitions the gate current is increasing very rapidly as illustrated in Figures 4 and 5. This current must flow through the source inductance and will be slowed down based on the inductor value. Consequently, the time required to charge/discharge the input capacitance of the MOSFET gets longer, mainly influencing the turn-on and turn-off delays (step 1). Furthermore, the source inductor and the CISS capacitor form a resonant circuit as shown in Figure 7. Gate drive resonant circuit components Parazitik bileenlerin etkileri: Switching performans zerinde en byk etkiyi source indktans gsterir. Tipik bir devrede parazitik indktansn iki kayna bulunur. MOSFET paketinin baglant kablolar ve kaynak ve ground arasndaki baskdevre kablolamalar. Bu genellikle gate driverinun bypass kapasitr ve yksek firekans filitre kapsitrnn negatif elektrodu olarak da dnlebilir. Devredeki seri

bagl (sense) direnler ektra indktans yaratarak nceki iki parazit gurubuna katkda bulunabilirler. Swithcing mekanizmasnda kaynak indktrn ieren iki eit mekanizma bulunur. Swithing geilerinin balangcnda gate akm sekil 4 ve sekil 5 de gsterildii gibi ok hzl olarak ykselmektedir. Bu akm kaynak indktans zerinden akmak zorundadr ve indkt deerine gre akm iddeti azalacaktr. Sonu olarak MOSFETtin input kapasitrnn dolmas veya boalmas daha fazla zaman alarak step1 deki turn on ve turn off gecikmelerini getkileyecektir. Ayrca kaynak indktr ve CISS kapasitoru ekilde gsterildii gibi bir rezonans devresi olutracaktr.

ekil 7.Gate drive resonans devresi bileenleri The resonant circuit is exited by the steep edges of the gate drive voltage waveform and it is the fundamental reason for the oscillatory spikes observed in most gate drive circuits. Fortunately, the otherwise very high Q resonance between CISS and LS is damped or can be damped by the series resistive components of the loop which include the driver output impedance, the external gate resistor, and the internal gate mesh resistor. The only user adjustable value, RGATE, can be calculated for optimum performance by: Resonans devresi gate drive voltaj dalgasndaki addm kenarlar tarafndan uyarlrslar. Pek ok gate drive devrelerinde gzlenen dalgal spike'larn sebebi budur. Bu sayede CISS ve LS arasndaki ok yksek Q resonans seri dirensel bileenlererrle (driver output empedans, harici gate direnci ve i meh direnci) drlr. Kullanc tarafnda kontol edilebilen tek deger RGATE optimum performans elde edebilmek iin aadaki gibi hesaplanr:

Smaller resistor values will result an overshoot in the gate drive voltage waveform, but also result in faster turn-on speed. Higher resistor values will under-damp the oscillation and extend the switching times without offering any benefit for the gate drive design. The second effect of the source inductance is a negative feedback whenever the drain current of the device is changing rapidly. This effect is present in the second time interval of the turn-on and in the third time interval of the turn-off procedure. During these periods the gate voltage is between VTH and VGS,Miller, and the gate current is defined by the voltage across the drive impedance, VDRV-VGS. In order to increase the drain current quickly, significant voltage has to be applied across the source inductance. This voltage reduces the available voltage across the drive impedance, thus reduces the rate of change in the gate drive voltage which will result in a lower di/dt of the drain current. The lower di/dt requires less voltage across the source inductance. A delicate balance of gate current and drain di/dt is established through the negative feedback by the source inductor. The other parasitic inductance of the switching network is the drain inductance which is again composed of several components. They are the packaging inductance inside the transistor package, all the inductances associated with interconnection and the leakage inductance of a transformer in isolated power supplies. Their effect can be lumped together since they are in series with each other. They act as a turn-on snubber for the MOSFET. During turn-on they limit the di/dt of the drain current and reduce the drain-to-source voltage across the device by the factor of LDdi/dt. In fact, LD can reduce the turnon switching losses significantly. While higher LD values seem beneficial at turn-on, they cause considerable problems at turn-off when the drain current must ramp down available in the literature but points beyond the scope of this paper. Kk direnc degerleri gate drive coltajnn ok yuksek degere kmasna sebep olurken daha hzl bir turn-on saglar. Yksek diren degerleri gate drive tarasmnda herhangi bir avantaj salamad gibi switching zamanlarnn uzamasna neden olur. Drenasj akm hzlca deitike kaynak indktans negatif geribesleme etkisi gsterir. Bu etki turn on prosedrnn 2. zaman aralnde ve turn off presedrnn 3. zaman aralnda gzlenir. Bu peyotlar boyunca, gate voltaj VTH ve VGS,MILLER arasnda gate akm ise driver empedansndaki voltaj deerine (VDRV-VGS) gre bir deger alr. Drenaj akmn abucak ykseltmek iin kaynak indktansna belirgin bir voltaj uygulanmak zorundadur. Bu voltaj driver empedansndaki voltaj degerini drr. Bu voltaj dmesi drenaj akmnda dk bir di/dt oranna neden olur. Bu dk di/dt oran kaynak indktansn zerinden daha dk bir voltajn gemesine nedene olur. Kaynak indktr tarafndan negatif bir geribesleme uygulanmas ile gate akm ve drenaj di/dti zerinde hasass bir denge salanr. Swithing networknn Dier bir parazitik indktans ise yine pek ok bileenden olumu olan drenaj indktansdr. Transistr paketlerinin paketleme indktanslar, arabalantlardan oluan tm indktanslarve isole edilmi g kaynaklarnn transformatorlerinden kayakl bir indktanslar. Tm bunlarn etkileri bir btn olarak dnlebilir. nk hepsi birbirine seri baldr. MOSFET'n turn-on sndrcs (snubber) olarak etki ederler. Turn on srasnda drenaj akmnn di/dt ( I'nin zaman iindeki deiim oran) deerini limitleyerek alet zerindeki drainto-soruce voltaj deerini LD.di/dt oradnda drrler. Aslnda, LD turn-on swithing kayplarn da belirgin bir ekilde azaltr. Yksek LD degerleri turn on srasnda faydal grnrken turn-off srasnda drenaj akm derken dikkate alnmas gerekensorunlara neden olurlar. Ancak bunlar bu yaznn deinecekleri arasnda deildir.

LK BLMN SONU 2010-01-14

GROUND REFERENCED GATEDRIVE

PWM Direct drive In power supply applications, the simplest way of driving the gate of the main switching transistor is to utilize the gate drive output of the PWM controller as shown in Figure 8. Figure 8. Direct gate drive circuit The most difficult task in direct gate drives is to optimize the circuit layout. As indicated in Figure 8, there might be considerable distance between the PWM controller and the MOSFET. This distance introduces a parasitic inductance due to the loop formed by the gate drive and ground return traces which can slow down the switching speed and can cause ringing in the gate drive waveform. Even with a ground plane, the inductance can not be completely eliminated since the ground plane provides a low inductance path for the ground return current only. To reduce the inductance linked to the gate drive connection, a wider PCB trace is desirable. Another problem in direct gate drive is the limited drive current capability of the PWM controllers. Very few integrated circuits offer more than 1A peak gate drive capability. This will limit the maximum die size which can be driven at a reasonable speed by the controller. Another limiting factor for MOSFET die size with direct gate drive is the power dissipation of the driver within the controller. An external gate resistor can mitigate this problem as discussed before. When direct gate drive is absolutely necessary for space and/or cost savings, special considerations are required to provide appropriate bypassing for the controller. The high current spikes driving the gate of the MOSFET can disrupt the sensitive analog circuitry inside the PWM controller. As MOSFET die size increases, so too does gate charge required. The selection of the proper bypass capacitor calls for a little bit more scientific approach than picking the usual 0.1F or 1F bypass capacitor. PWM direkt src G kayna uygulamalarnda, ana anahtarlama taransistrn srmenin en basit yolu PWM denetleyicinin gate src kn Fig. 8 deki gibi kullanmaktr.

ekil 8. direkt gate src devresi. Direkt gate src tasarmlarndaki en byk zorluk devre dzeni optimize etmektir. Figr 8 de gsterildii gibi, Mosfet ve PWD denetleyicisi arasnda farkedilebilir bir uzaklk bulunabilir. Bu uzaklk, gate dive ve ground arasnda oluan akm dngs nedeniyle parazitik indiksiyonlara neden olabilir. Bu da switching hzn ve performansn etkiler. Ground tabakas olmasna ragmen, bu parazitik indktans yok etmek herzaman mmkn olmayabilir. Bu gate drive baglantsndan kaynakl oluan indktans yok etmek iin, geni PCB yollar kullanlmaldr. Direkt gatelerle ilgili bir baka problem ise, PWM denetleyicilerinin akm kapasitelerinin genelde dk olmasdr. ok az saydaki entegre devre 1A dan yksek peak akm kapasitesine sahiptir. Bu denetleyici taradndan makul bir hzda srlebilecek maksimum die boyutunu snrlandracaktr. Direkt gate tasarmnda Mosfet die boyutunu snrlandracak bir bake etken ise denetleyicideki g kayplardr. Harici bit gate direnci bu g kaybn azaltmaya yardmc olabilir. Gate srclerinin alan ve maliyet asndan kesinlikle gerekli olduu uygulamalarda, denetleyiciyi bypass edecek birtakm etkenler gz nne alnmaldr. Yksek akm atlamalar PWM ierisindeki hashas analog dervereler zarar verebilit. Mosfet die boyutu arttka, dolaysyla gerekli olan gate yk de artmaktadr. Bu blmde uygun bypass kapasitr seimi zerine biraz bilimsel aklam getirilecektir. Sizing the bypass capacitor In this chapter the calculation of the MOSFET gate drivers bypass capacitor is demonstrated. This capacitor is the same as the PWM controllers bypass capacitor in direct gate drive application because that is the capacitor which provides the gate drive current at turn-on. In case of a separate driver circuit, whether a gate drive IC or discrete solution, this capacitor must be placed close, preferably directly across the bias and ground connection of the driver.

There are two current components to consider. One is the quiescent current which can change by a 10x factor based on the input state of some integrated drivers. This itself will cause a duty cycle dependent ripple across the bypass capacitor which can be calculated as: Bypass kapasitrnn boyutlandrlmas Bu blmde Mosfet gate srcs iin uygun bypass kapasitr hesab anlatlacaktr. Bu kapasitr, turn-on srasnda gate drive akmn salamas nedeniyle, direkt gate src uygulamalarndaki PWM denetleyicin bypass kapasitr ile ayndr. Ayr src devrelerinin mevcut oldugu durumlarda, bu kapasitr tercihen srcn bias' ve groundu arasna yada mmkn olduu kadar yakna yerletirilmelidir. Gz nnde bulundurulmas gereken iki akm vileeni vardr. lki istirahat akm, ki devrenin input durumna gre bu akm anlk olarak 10 katna kadar deiebilir. Aadaki formule gre hesaplanabilen bir akm dngsne neden olur.

where it is assumed that the drivers quiescent current is higher when its input is driven high. The other ripple component is the gate current. Although the actual current amplitude is not know in most cases, the voltage ripple across the bypass capacitor can be determined based on the value of the gate charge. At turn-on, this charge is taken out of the bypass capacitor and transferred to the MOSFET input capacitor. Accordingly the ripple is given by:

Burada input yksee ekildiinde devrenin istirehat akmnn daha yksek olduunu kabul ediyoruz. Dalalanma gsteren dier bir devre bileeni de gate akmdr. Aslnda gercek akm degeri ou durumda bilinemez, bypass kapasitr stndeki ykten yola klarak voltaj dalgalanmas belirlenir. Turn-on srasnda, bu yk bypass pakasitr tarasndan alnarak Mosfet input kapasitrne aktarlr. Voltajdaki dalalanma aadaki gibi bulunur

Sperposizyon ilkesini kullanarak ve denklemleri CDRV iin zerek, tolalere edilebilir ripple voltaj (AV) iin baypass kapasitr degeri aadaki gibi hesaplanabilir.

where IQ,HI is the quiescent current of the driver when its input is driven high, DMAX is the maximum duty cycle of the driver while the input can stay high, fDRV is the operating frequency of the driver, and QG is the total gate charge based on the amplitude of the gate drive and drain-tosource off state voltages. Burada IQ,HI devrenin input degeri yksek olduu durumdaki istirahat akm, DMAX inputun yksek dumdaki maksimum grev dngs, fDRV ise srcnn alma frekansdr. QG ise gate-drive genlii ve drenaj-kaynak off state voltajlar tarafndan belirlenen toplam yktr. Driver protection Another must-do with direct drive and with gate drive ICs using bipolar output stage is to provide suitable protection for the output bipolar transistors against reverse currents. As indicated in the simplified diagram in Figure 9, the output stage of the integrated bipolar drivers is built from npn transistors due to their more efficient area utilization and better performance. Src korumas Gz nne alnmas ve kesinlikle uygulanmas gereken konulardan birtanesi de ters akmlara kar src korumasdr. Figr9 da gsterildii zere entegre bipolar devrelerin output ksmlar npn transistrlerden yaplmtr. nk daha verimli ve daha performasnldrlar.

Figure 9. Gate drive with integrated bipolar transistors The npn transistors can handle currents in one direction only. The high side npn can source but can not sink current while the low side is exactly the opposite. Unavoidable oscillations between the source inductor and the input capacitor of the MOSFET during turn-on and turnoff necessitate that current should be able to flow in both directions at the output of the driver.

To provide a path for reverse currents, low forward voltage drop Schottky diodes are generally needed to protect the outputs. The diodes must be placed very close to the output pin and to the bypass capacitor of the driver. It is important to point out also, that the diodes protect the driver only, they are not clamping the gate-to-source voltage against excessive ringing especially with direct drive where the control IC might be far away from the gate-source terminals of the MOSFET. Npn transistrler akm sadece tek ynde geirirler. Yksek kenar npn akm kaynana balyken dk kenar akmn gidecei yere baldr. Her iki kenarda ters ekilde balanamaz. Turn-on ve Turn-off aamasnda, kaynak indktr ve input kapasitr arasnda gerekleen, nleyemediimiz dalgalanmalar devernin output ucunda akmn her iki yne de akmasna neden olur. Ters akma zerinden akabilecegi bir yn belirleyerek outputlar koruma altna almak iin dk voltajl ileri ynl chottky diyotlar kullanlmaldr. Bu diyotlar devrenin bypass kapasitr outpu ularna ok yakn balanmaldr. zellikle belirtmek gerekir ki bu diyotlar sadece devreyi korumaktadr, Ar gate-to-source voltaj yklenmelerine kar bir gvence deildir. Bipolar totem-pole driver One of the most popular and cost effective drive circuit for driving MOSFETs is a bipolar, noninverting totem-pole driver as shown in Figure 10. Figure 10. Bipolar totem-pole MOSFET driver Like all external drivers, this circuit handles the current spikes and power losses making the operating conditions for the PWM controller more favorable. Of course, they can be and should be placed right next to the power MOSFET they are driving. That way the high current transients of driving the gate are localized in a very small loop area, reducing the value of parasitic inductances. Even though the driver is built from discrete components, it needs its own bypass capacitor placed across the collectors of the upper npn and the lower pnp transistors. Ideally there is a smoothing resistor or inductor between the bypass capacitor of the driver and the bypass capacitor of the PWM controller for increased noise immunity. The RGATE resistor of Figure 10 is optional and RB can be sized to provide the required gate impedance based on the large signal beta of the driver transistors. Bipolar totem-pole driver MOSFET'leri srmek iin en popler ve maliyet asndan en etkin devre ekil 10 da gsterilen bipolar, non-inverting totem-pole src devresidir.

ekil 10. Bipolar totem-pole Mosfet src devresi Harici dier devreler gibi bu devre de, ani akm sramalarn ve g kayplarn kontrol altnda tutarak PWM denetleticisinin daha dzgn alabilmesi iin gerekli alma koullarnn oluturur. Tabiki ve mutlak suretle srdkleri g Mosfetinin sag bitiiine yerletirilmelidir. Bu ekilde, srlen kapnn yksek akm geileri kk bir dng alanna hapsedilmi olur. Boylece bundan kaynaklanan pek ok parazitik indktans mmkn olan en alt seviyelere indirilmi olur. Src bitbirinden ayr bileenlerden olumu olsa bile Upper npn ve Lower pnp transistrlerin kollektrleri arasna yerletirilmi kendi bypass kapasitrne ihtiya duyar. Sistemin grlt toleransn arttrmak iin src devresinin bypass kapasite ve PWM devresinin bypass kapasitr arasna yumuatc bir direncin yada indktrn eklenmesi faydal olacaktr. ekil 10'da gsterilen RGATE direnci opsiyoneldir . Src transistrlerinin geni-sinyal-beta degerlerinini gz nne alarak RB'nin degeri ihtiya duyulan gate empedansn saglamak zere deitirilebilir. An interesting property of the bipolar totem-pole driver that the two base-emitter junctions protect each other against reverse breakdown. Furthermore, assuming that the loop area is really small and RGATE is negligible, they can clamp the gate voltage between VBIAS+VBE and GND-VBE using the base-emitter diodes of the transistors. Another benefit of this solution, based on the same clamp mechanism, is that the npn-pnp totem-pole driver does not require any Schottky diode for reverse current protection. MOSFET totem-pole driver The MOSFET equivalent of the bipolar totempole driver is pictured in Figure 11. All the benefits mentioned about the bipolar totem-pole driver are equally applicable to this implementation. Figure 11. MOSFET based totem-pole driver Unfortunately, this circuit has several drawbacks compared to the bipolar version which explain that it is very rarely implemented discretely. The circuit of Figure 11 is an inverting driver, therefore the PWM output signal must be inverted. In addition, the suitable MOSFET transistors are more expensive than the bipolar ones and they will have a large shoot through current when their common gate voltage is in

transition. This problem can be circumvented by additional logic or timing components which technique is extensively used in IC implementations. Speed enhancement circuits When speed enhancement circuits are mentioned designers exclusively consider circuits which speed-up the turn-off process of the MOSFET. The reason is that the turn-on speed is usually limited by the turn-off, or reverse recovery speed of the rectifier component in the power supply. As discussed with respect to the inductive clamped model in Figure 3, the turnon of the MOSFET coincides with the turn-off of the rectifier diode. Therefore, the fastest switching action is determined by the reverse recovery characteristic of the diode, not by the strength of the gate drive circuit. In an optimum design the gate drive speed at turn-on is matched to the diode switching characteristic. Considering also that the Miller region is closer to GND than to the final gate drive voltage VDRV, a higher voltage can be applied across the driver output impedance and the gate resistor. Usually the obtained turn-on speed is sufficient to drive the MOSFET. Bipolar totem-pole srcnn ilgin bir zellii ise, iki base-emiter junction birbirlerini ters akma kar korur. Ayrca loop blgesinin gerekten ok kk ve RGATE degerinin gz ard edilebilecek kadar kk olduunu kabul edesek, transistrlerin base-emiter diyotlarn kullanarak VBIAS+VBE ve GND-VBE arasndaki gate voltajn kenetleyebilirler. Bu zmn ayn kenetlemeke mekanizmaz temelinde bir baka avantaj ise npn-pnp totem-pole src ters akm korunmas iin Shottky diyotuna gerek duymaz. Mosfet totem-pole src ekil 11 de gsterilmi olan bipolar totem-pole srcnn Mosfet karldr. Bipolar totempole src iin yukarda bahsedilmi olan avantajlarn tamam bu src iin de geerlidir.

Ne yazk ki, bu devre bipolar versiyonuna gre baz zorluklar ierir ve bu nedenden dolay ok nadiren tercih edilir. ekil 11'de gsterilmi olan devre srcy invert etmektedir. Bu

nedenle PWM k sinyali de invert edilmelidir. Ek olarak, Bu i iin uygun Mosfet transistrler benzer ileri gren bipolar transistrlere gre olduka pahaldrlar ve gate voltaj akar durumdayken geni bir shoot throuht akma sahiptirler. Bu problem ek mantk ve zamanlama deverleri eklenerek zlebilir. Bu zm IC uygulamalarnda olduka yaygn olarak kullanlr. Hz iyiletirilmi devreler Hzn iyiletirilmesindenden bahsedildiinde, tasarmclar genellikle Mosfet srcnn turn-off srecinin hzlandrlmasn gz nne getirirler. nk torn-on hz genellikle turn-off tarafndan yada g salaycnn rektifayr bileenlerinin reverse recover hz tarafndan belirlenir. Figr 3 te tartld zere, Mosfetin turn-on sreci rectifayr diyodun turn-off sreci ile rtr. Bu nedenle anahtarlama ileminin hz diyodun reverse recover karakteristii ile belirlenir, gate src devresinin gcyle deil. Optimum bir tasarmda gate src hz diyotun anahtarlama karakteristii ile rtr. Miller blgesinin GND ye yakn olduu dnldnde src output empedansndan ve gate direncinden daha yksek bir voltaj geirerek turn-on aamasnda blirgin bir hzlanma gzlenebilir.

The situation is vastly different at turn-off. In theory, the turn-off speed of the MOSFET depends only on the gate drive circuit. A higher current turn-off circuit can discharge the input capacitors quicker, providing shorter switching times and consequently lower switching losses. The higher discharge current can be achieved by a lower output impedance MOSFET driver and/or a negative turn-off voltage in case of the common N-channel device. While faster switching can potentially lower the switching losses, the turn-off speed-up circuits increase the ringing in the waveforms due to the higher turnoff di/dt and dv/dt of the MOSFET. This is something to consider in selecting the proper voltage rating and EMI containment for the power device. Durum turn-off srecinde tamamen farkldr. Teorik olarak Mosfetin turn-off hz sadece gate src devresine baldr. Yksek akmlo bir turn-of devresi input kapasitrn abucak discharge derek daha hzl anahtarlama dolaysyla daha dk anahtarlama kayb salayabilir. Yksek discharge akm dk empedansl Mosfet output devresi veya Nchannel aletlerde negatif turn-off voltaj ile elde edilebilir. Daha hzl swiitchingler genellikle daha dk switching kayplar salarlar. Devrenin turn-off hz artar. Bu power devreleri iin uygun voltaj semekte gz nne alnmas gereken bir faktrdr. Turn-off diode The following examples of turn-off circuits are demonstrated on simple ground referenced gate drive circuits, but are equally applicable to other implementations discussed later in the paper. The simplest technique is the anti-parallel diode, as shown in Figure 12. Figure 12. Simple turn-off speed enhancement circuit In this circuit RGATE allows adjustment of the MOSFET turn-on speed. During turn-off the antiparallel diode shunts out the resistor. DOFF works only when the gate current is higher than: Turn-off diyotu Aadaki turn-off rnek develeri basit toprak referansl gate src devreleri zerinde

hazrlanmtr. Ancak bu yaznn devamnda bahsedilecek dier devreler zerinde de eit derecede uygulanabilir. En basit teknik ekil 12 de gsterilen anti-paralel diyottur

Figure 12.Turn off hz arttrlm basit devre. Bu devrede RGATE Mosfetin turn-off hznn ayarlanmasna imkan vermektedir. Turn off srasnda antiparalel diyot resistre shunts out yapar. DOFF yanlzca gate akm daha yksekken alr:

typically around 150mA using a 1N4148 and around 300mA with a BAS40 Schottky antiparallel diode. Consequently, as the gate-tosource voltage approaches 0V the diode helps less and less. As a result, this circuit will provide a significant reduction in turn-off delay time, but only incremental improvement on switching times and dv/dt immunity. Another disadvantage is that the gate turn-off current still must flow through the drivers output impedance. 1N4148 kullanldnda genellikle 150mA seviyesinde, BAS40 Schottky antiparallel diyot kullanldnda ise 300mA seviyesindedir. Sonu olarak gate-to-source voltajo 0V ye yaklarken diyot giderek daha az yardmc olur. Bylece, bu devre turn-off gecikme zamann farkedilir dzeyde azaltr, bu seitching zamannda ve dv/dt deerinde sacede artal bir iyilemedir. Dier bir dezavantaj ise gate turn-off akm halen srcnn output empedans

zerinden akmaya devam etmek zorundadr. PNP turn-off circuit Undoubtedly the most popular arrangement for fast turn-off is the local pnp turn-off circuit of Figure 13. With the help of QOFF, the gate and the source are shorted locally at the MOSFET terminals during turn-off. RGATE limits the turnon speed, and DON provides the path for the turnon current. Also, DON protects the base-emitter junction of QOFF against reverse breakdown at the beginning of the turn-on procedure. The most important advantage of this solution is that the high peak discharge current of the MOSFET input capacitance is confined in the smallest possible loop between the gate, source and collector, emitter connections of the two transistors. PNP turn-off devesi phesiz, hzl turn-off performansn elde etmek iin en ok kullanlan devre ekil13 te gsterilen blgesel pnp turn-off devresidir. QQFF yardmyla, turn off srasnda gate ve kaynak Mosfetin terminallerinde local olarak ksadevre yaptrlr. Rgate turn-on hzn snrlar, DON turn-on akm iin bir gzargah salar. Ayrca turn-on srecinin balancnda reversebrekdownlara kar DON QQFF'in base-emiter junctionunu korur. Bu zn en nemli avantaj ise, Mosfet input kapasitansnn yksek peak discharge akm iki transistrn gate,source ve kollektor,emiter balantlar arasnda mmkn olan en kk loop a hapsedilmitir.

The turn-off current does not go back to the driver, it does not cause ground bounce problems and the power dissipation of the driver is reduced by a factor of two. The turn-off transistor

shunts out the gate drive loop inductance, the potential current sense resistor, and the output impedance of the driver. Furthermore, QOFF never saturates which is important to be able to turn it on and off quickly. Taking a closer look at the circuit reveals that this solution is a simplified bipolar totem-pole driver, where the npn pull-up transistor is replaced by a diode. Similarly to the totem-pole driver, the MOSFET gate is clamped by the turn-off circuit between GND-0.7V and VDRV+0.7V approximately, eliminating the risk of excessive voltage stress at the gate. The only known shortcoming of the circuit is that it can not pull the gate all the way to 0V because of the voltage drop across the base-emitter junction of QOFF. NPN turn-off circuit The next circuit to examine is the local npn turnoff circuit, illustrated in Figure 14. Similarly to the pnp solution, the gate discharge current is well localized. The npn transistor holds the gate closer to GND than its pnp counterpart. Also, this implementation provides a self biasing mechanism to keep the MOSFET off during power up. Turn-off akm srcye geri dnmez, topraa srama sorunlar yaratmaz ve bu nedenlede g kaybn en az iki kat azaltr. Turn-off transistr gate src loop indktansn, potansiyel akm al direncini ve srcnn output empedansn shunt out eder. Ayrca QQFF hi bir zaman satre olmaz, bylece ok hzl bir ekilde turn-off ve turn-on olabilir. Devre biraz daha iyi incelenecek olursa bu zm npn transistrnn bir diyot ile deitirildii basit bir bipolartotem-pole srcsdr. Totem-pole srcsne benzer olarak Mosfetin gate degeri GND0.7V ve VDRV+0.7V arasnda tutularak gatede valtaj am riski elimine edilmi olunur. Bu devrenin bilinen tek bir kt yan QQFF'in base-emiter junctionndaki voltaj dsmesi nedeniyle gate'i herzaman 0V' a ekememesidir. NPN turn-off devresi nceleyecegimiz dier bir devre ise ekil14 te gsterilen npn turn-off devresidir. Pnp devresine benzer olarak gate discharge akm iyi lokalize edilmitir. Npn transistr pnp zme gate'i GNDye daha yakn tutabilir. Ayrca b zm power-up srasnda Mosfeti kapal tutarak self-biasing mekanizmas salar. Unfortunately, this circuit has some significant drawbacks. The npn turn-off transistor, QOFF is an inverting stage, it requires an inverted PWM signal provided by QINV. Figure 14. Local npn self biasing turn-off circuit The inverter draws current from the driver during the on time of the MOSFET, lowering the efficiency of the circuit. Furthermore, QINV saturates during the on-time which can prolong turn-off delay in the gate drive. NMOS turn-off circuit An improved, lower parts count implementation of this principle is offered in Figure 15, using a dual driver to provide the inverted PWM signal for a small N-channel discharge transistor. Malesef bu devrenin ok nemli bir sorunu vardr. Npn turn-off transistr QINV tarafndan invert edilmi bir PWM sinyaline ihtiya duymaktadr.

Mosfetin almas srasnda inverter devre eleman akm srcden eker, bude devrenin veriminin dmesine neden olur. Ayrca QINV alma srasnda satre olarak turn-off ssrecinin uzamasna neden olur. NMOS turn-off devresi Bu devrenin iyiletirilmi hali olan NMOS turn-off devres ekil 15 de verilmitir. Bu deverede kk N-channel discharge transistrine invert PWM sinyalini elde etmek iin iki src kullanlmaktadr.

This circuit offers very fast switching and complete discharge of the MOSFET gate to 0V. RGATE sets the turn-on speed like before, but is also utilized to prevent any shoot through currents between the two outputs of the driver in case of imperfect timing of the drive signals. Another important fact to consider is that the COSS capacitance of QOFF is connected in parallel to the CISS capacitance of the main power MOSFET. This will increase the effective Total Gate Charge the driver has to provide. Also to consider, the gate of the main MOSFET is floating before the outputs of the driver IC becomes intelligent during power up. dv/dt protection There are two situations when the MOSFET has to be protected against dv/dt triggered turnon. One is during power up where protection can usually be provided by a resistor between the gate and source terminals of the device. The pull down resistor value depends on the worst case dv/dt of the power rail during power up according to: Bu devre ok hzl alr. Ayrca Mosfetin =V'a kadar tamamen desarj olmasn salar.RGATE daha ncesindede olduu gibi turn-on hzn belirler, ayrca srcnn iki k arasnda oluan akm atlamalarn engeller. Gz nnde bulundurulmas gereken dier nemli bir nokta ise QQFF'in COSS kapasitansnn ana g devresinin CISS kapasitansna paralel bal olduudur. Bu durum srcnn salamas gereken Total Gate Charge verimliliini arttrr. Ayrca, Ana Mosfetin gate deeri power-up srasnda IC nin klar intelligent olmadan nce dalalanmaktadr. dv/dt Korumas dv/dt tarafndan tetiklenen turn-on srecine kar Mosfet korunutken iki durum nnde bulundurulmaldr.. Birincisi, gate ve source terminalleri arasna yerletirilen bir diren powerup srasnda bir koruma oluturur. Pull-down diren deeri power-up srasnda dv/dt'nin en kt durumuna gre aadaki gibi belirlenir.

In this calculation the biggest challenge is to find the highest dv/dt which can occur during power up and provide sufficient protection for that particular dv/dt. The second situation is in normal operation when turn-off dv/dt is forced across the drain-to-source terminals of the power switch while it is off. This situation is more common than one may originally anticipate. All synchronous rectifier switches are operated in this mode as will be discussed later. Most resonant and soft switching converters can force a dv/dt across the main switch right after its turn-off instance, driven by the resonant components of the power stage. Since these dv/dts are significantly higher than during power up and VTH is usually lower due to the higher operating junction temperature, protection must be provided by the low output impedance of the gate drive circuit. The first task is to determine the maximum dv/dt which can occur under worst case conditions. The next step in evaluating the suitability of a particular device to the application is to calculate its natural dv/dt limit, imposed by the internal gate resistance and the CGD capacitance of the MOSFET. Assuming ideal (zero Ohm) external drive impedance the natural dv/dt limit is:

Bu hesaplamada, kalalacak en byk sorun dv/dt'nin en byk deerinin hesaplanmasdr, ki bylece power up srasnda dv/dt'nin herhangi bir deeri iin bir koruma yaratlabilsin. Ikinci durum ise devrenin normal almas srasnda gerekleir yani turn-off da dv/dt power anahtarnn drain-to-source terminalinden akmaya zorlanrken. Bu durum daha hazla meydana gelen bir durumdur. Daha sonra tartlaca zere tm senkronize rektifyr switchler bu modda alr. En resonant ve soft switching dntrcler turn-off dan hemen sonra dv/dt'yi ana switchten geirmeye alr. dv/dt power up srasnda belirgin bir ekilde yksek olduu ve junctiondaki yksek operasyon scakl nedeniyle VTH genellikle dk olduu iin koruma gate drive devresinin dk k empedensnda salanmaldr. Birinci grev en kt koullarda oluabilecek en yksek dv/dt oranna karar verilmesidir. Sonraki adm ise kullanlacak aletin bu ulgulama iinn ne kadar uygun olup olmadn anlamak iin dv/dt din doal limitlerinin bulunmasdr. Bu limit dahili gate direnci ve Mosfetin CGD kapasitans tarafndan belirlenir. deal (sfr Ohm) harici src empedans olduunu kabul ederek, doal dv/dt limiti aadaki gibi bulunur:

where VTH is the gate threshold at 25C, -0.007 is the temperature coefficient of VTH, RG,I is the internal gate mesh resistance and CGD is the gateto- drain capacitor. If the natural dv/dt limit of the MOSFET is lower than the maximum dv/dt of the resonant circuit, either a different MOSFET or a negative gate bias voltage must be considered. If the result is favorable for the device, the maximum gate drive impedance can be calculated by rearranging and solving the previous equation according to: where RMAX=RLO+RGATE+RG,I. Once the maximum pull down resistor value is given, the gate drive design can be executed. It should be taken into account that the drivers pull down impedance is also temperature dependent. At elevated junction temperature the MOSFET based gate drive ICs exhibit higher output resistance than at 25C where they are usually characterized. Turn-off speed enhancement circuits can also be used to meet dv/dt immunity for the MOSFET since they can shunt out RGATE at turn-off and during the off state of the device. For instance, the simple pnp turn-off circuit of Figure 13 can boost the maximum dv/dt of the MOSFET. The equation modified by the effect of the beta of the pnp transistor yields the increased dv/dt rating of: burada VTH 25 C de gate eik deeri, -0.007 is VTH in scaklk katsays, RG,I dahili gate mesh direnci ve VGD gate-to-drain kapasitrdr. Eer Mosfetin doga dv/dt snr resonant devrenin maksimum dv/dt oradndan kk ise, baka bir mosfet yada negatif gate bias volta kullanlmaldr. Eer elde edilen sonu, uygulama iin kullanlabilir durumdaysa, maksimum gate drive empedans nceki denkelemleri yeniden dzenleyerek aadaki gibi hesaplanabilir.

Burada RMAK=RLO+RGATE+RG,I dr. Maksimum pulldown diren deeri birkere vedildiinde, gate tasarm kolayca yaplabilir. Diriver'n pull down empedansnn da scaklkla deiebildii unutulmamaldr. Hesaplanan junction scaklgnda, Mosfet tabanl gate dver IC'ler 25 C de belirtilen karakterizzasyon deerlerinden ok daha yksek output direnci gsterirler. Turn-off hz iyiletirilmi devereler Mosfet'in dv/dt ye immunitysini karlamak iin kullanlabilir. unk aletin off zamannda ve turn-off srasnda RGATE'i shunt out ederler. rnek olarak, figr 13 de gsterilen basist pnp turn-off deversi modfetin maksimum dv/dt deerini karlayabilir. Pnp transistrn beta'snn etkisini de hesaba katarak arttrlm dv/dt oran aadaki gibi hesaplanr.

In the dv/dt calculations a returning factor is the internal gate resistance of the MOSFET, which is not defined in any data sheet. As pointed out earlier, this resistance depends on the material properties used to distribute the gate signal, the cell density, and the cell design within the semiconductor. dv/dt hesaplarnda bir geri dn faktrde Mosfetin dahili gate direncidir ki bundan hic bir datasheette bahsedilmez. Daha ndedende bahsedildii gibi, bu diren deeri sinyali datmak iin kullanlan maddenin zeliklerine, hcre yogunluuna ve yar iketken iindeki hcre tasarmna baldr.

KNC BLMN SONU

SYNCHRONOUS RECTIFIER DRIVE

The MOSFET synchronous rectifier is a special case of ground referenced switches. These devices are the same N-channel MOSFETs used in traditional applications, but applied in low voltage outputs of the power supplies instead of rectifier diodes. They usually work with a very limited drain-to-source voltage swing, therefore, their CDS and CGD capacitors exhibit relatively large capacitance values. Moreover, their application is unique because these devices are operated in the fourth quadrant of their V-I plane. The current is flowing from the source toward the drain terminal. That makes the gate drive signal kind of irrelevant. If the circumstances, other components around the synchronous switch require, current will flow in the device, either through the resistive channel or through the parasitic body diode of the MOSFET. The easiest model to examine the switching behavior of the MOSFET synchronous rectifier is a simplified buck power stage where the rectifier diode is replaced by the QSR transistor as shown in Figure

SENKRON RECTIFIER SRC

Mosfet senkronize rektifier srs ground-referansl awitchlerin zel bir uyulamasdr. Bu aletler geleneksel uygulamalarda kullanlan N-kanal Mosfetlerle ayndrlar. Ancak rektifier diyotlar yerine g nitesinen klarna dk voltaj uygulanr. Genellikle ok snrl bir drain-to-source voltaj salnm ile alrlar. Bu nedenle CDS ve CGD kapasitrleri ok yksek kapasitans deerlerine sahiptirler. Ayrca, kullanldklar alanda tektirler nk V-I planinin 4. ereinde alrlar. Akm kaynaktan drenaj terminaline doru akar. Bu gate drive sinyalini alakasz klar. Senkronize switch drivein evresindeki elemanlar ihtiya gsterirse akm resistif kanal yada mosfetin parazitik body diyotunu kullanarak device iinden akar. Mosfet senkronize rektifier swictci anlamak iin en basit model, rectifier diyotun QSR tansistr ile deitirildii ekilde gsterilmi olan basitletirilmi buck power stage uygulamasdr.

ekil 16. Basitletirilmi senkronize rektifier The first thing to recognize in this circuit is that the operation of the synchronous rectifier MOSFET depends on the operation of another controlled switch in the circuit, namely the forward switch, QFW. The two gate drive waveforms are not independent and specific timing criteria must be met. Overlapping gate drive signals would be fatal because the two MOSFETs would short circuit the voltage source without any significant current limiting component in the loop. Ideally, the two switches would turn-on and off simultaneously to prevent the body diode of the QSR MOSFET to turn-on. Unfortunately, the window of opportunity to avoid body diode conduction is very narrow. Very accurate, adaptive timing and fast switching speeds are required, which are usually out of reach with traditional design techniques.

Bu devrede gze arpmas gereken ilk ey, Mosfet senronize rectifier n almasnn devredeki bir baka kontroll switche bal olmasdr. Yani QFW forward switch. ki gate drive dalga formu birbirinden bamsz deillerdir ve zel zamanlama kriterleri karlanmaldr. st ste binen gate drive sinyalleri lmcl olabilir nk loop zerinde bekirgin hibir akm snrlayc eleman olmadan iki Mosfet ksadevre edeceklerdir. deal olarak iki switch QSR Mosfetin body diyotunun zarar grmesini engellemek iim ayn anda turn-on ve turn-off yaplmaldrlar. Malesef body diyot ksadevresini engellemek iin zamanlama ok ksa ve ok

hassas olmaldr ve bu geneleksel tasarm teknikleri ile pek kolay deildir. Consequently, in most cases a brief period from 20ns to 80ns of body diode conduction precedes the turn-on and follows the turn-off of the synchronous MOSFET switch. Sonu olarak, ou zaman bu ksa zaman dilimi 20 ile 80 nanosaniye arasndadr, bu dilim iinde body diyotu iletkenligi salanp Mosfetin Turn-on ve Turn-off sreleri tamamlanr. Gate charge During the body diode conduction period the full load current is established in the device and the drain-to-source voltage equals the body diode forward voltage drop. Under these conditions the required gate charge to turn the device on or off is different from the gate charge needed in traditional first quadrant operation. When the gate is turned-on, the drain-tosource voltage is practically zero and the CGD and CDS capacitors are discharged. Also, the Miller effect is not present, there is no feedback between the drain and gate terminals. Therefore, the required gate charge equals the charge needed to raise the voltage across the gate-to-source and gate-todrain capacitors from 0V to the final VDRV level. For an accurate estimate, the low voltage average value of the CGD capacitor between 0V and VDRV has to be determined according to: Gate charge Gvde diyotu iletim sresi boyunca, tm yk akm alet (device) zerinden akar ve drain-tosource voltaj body diyodu zerinde forward voltaj dmesine eit olur. Bu koullar altnda device'i on yada off yapmak iin gereken yk ilk erekte gereken gate yknden farkldr. Gate turn-on olduunda, drain-to-source voltaj pratik olarak 0 'dr ve CGD ve CDS kapasitrleri dearj olmu durumdadr. Ayrca drain ve gate arasnda geribildirim olmad iin burada Miller etkisi yoktur. Bu nedenle ihtiya duyula gate yk gate-to-source ve gate-tofrain kapasitrlerini 0V den VDRV seviyesine karmak iin gereken yke eittir. Doru bir tahmin iin CGD kapasitrnn 0V ve VDRV arasndaki dk voltaj ortalamas aadaki denkleme gre hesaplanr:

The following equation can then be used to estimate the total gate charge of the synchronous MOSFET rectifier: This value is appreciably lower than the total gate charge listed in the MOSFET data sheets. The same MOSFET with an identical driver circuit used for synchronous rectification can be turned on or off quicker than if it would be driven in its first quadrant operation. Unfortunately, this advantage can not be realized since the low RDS(on) devices, applicable for synchronous rectification, usually have pretty large input and output capacitances due to their large die size. Another important note from driver power dissipation point of view is that the total gate charge value from the data sheet should be considered. Although the gate charge delivered by the driver during turn-on is less than the typical number listed in the data sheet,

that covers a portion of the total charge passing through the driver output impedance. Before turn-on, while the drain-to-source voltage changes across the device, the Miller charge provided by the power stage must flow through the driver of the synchronous MOSFET causing additional power dissipation. This phenomenon can be seen in Figure 17, which is part of the next discussion on dv/dt considerations. The turn-off procedure of the synchronous MOSFET obeys the same rules as the turn-on procedure, therefore all the previous considerations with respect to gate charge are applicable. Aadaki denklem Mosfet senkronize rektifiern toplam gate ykn hesaplamak iin kullanlabilir.

Bu deer, Mosfet datasheetlerinde verilen deerlerden bariz bir ekilde daha dktr. Senkronize fektifying ilerinde kullanlan ayn ideal Mosfety devresi, srecin ilk ereinde ok daha hzl bir ekiklde tuyrn-on ve turn-off yaplabilir. Malesef bu avantaj, dk RDS cihazlar iin kullanlamamaktadir. nk genel olarak boyutlar nedeniyle yksek input ve output kapasitanslar vardr. Dier bir nemli nokta ise data sheetlerde verilen toplam yk deerleri gz nnde bulundurulmaldr. Datasheetlerde verilen tipik deerlere gre turn on srasnda src tarafndan datlan akmn daha dk olmasna ramen, bu deerler driver output empedansndan geen ykn byk bir ksmn bu deer kapsar. Turn on ncesinde drain-to-source voltaj device zerinde deitigi srada, power katman tarafndan beslenen miller senkronize mosfet zerinden akarak ekstra yk kaybna yol aarlar. Bu fenoma figur17de gsterilmektedir. Bu ayn zamanda bi sonraki blmde bahsedilecek olaan dv/dt etkenleri ksmnda elealnacaktr. Mosfetin turn-off sreci turn-on sreci ile ayn kurallar ierisinde gerekleir. Bu nedenle bundan nceki ksmlarada gate yk ile ilgili bahsedilen herey turn-off iin de geerlidir. dv/dt considerations Figure 17 shows the most important circuit and current components during the turn-on and turnoff procedures of QSR. Actually, it is more accurate to say that the switching actions taking place in QFW forces QSR to turn-on or off independently of its own gate drive signal. Figure 17. Synchronous switching model The turn-on of QSR starts with the turn-off of QFW. When the gate drive signal of QFW transitions from high to low, the switching nodetransitions from the input voltage level to GND. The current stays in the forward switch until the CRSS capacitor is discharged and the body diode of QSR is forward biased. At that instant the synchronous MOSFET takes over the current flow and QFW turns off completely. After a short delay dominated by the capabilities of the controller, the gate drive signal of QSR is applied and the MOSFET is turned on. At that time the current transfers from the body diode to the channel of the device. At the end of the conduction period of QSR the MOSFET must be turned off. This procedure is initiated by removing the drive signal from the gate of the synchronous switch. This event itself will not cause the turn-off of the device. Instead, it will force the current to flow in the body diode instead of the channel. The operation of the circuit is indifferent to this change. Current starts to shift from QSR to QFW when the gate of the forward switch transitions from low to high.

Once the full load current is taken over by QFW and the body diode is fully recovered, the switching node transitions from GND to the input voltage level. During this transition the CRSS capacitor of QSR is charged and the synchronous MOSFET is susceptible to dv/dt induced turn-on. Summarizing this unique operation of thesynchronous MOSFET and its gate drive, the most important conclusion is to recognize that both turn-on and turn-off dv/dt of the synchronous MOSFET is forced on the device by the gate drive characteristics (i.e. the switching speed) of the forward switch. Therefore, the two gate drive circuits should be designed together to ensure that their respective speed and dv/dt limit matches under all operating conditions. This can be ensured by adhering to the steps of thefollowing simple calculations: dv/dt etkenleri Figr17 QSR'n turn-on ve turn-off sreleri srasnda en nemli dere ve akm elemanlarn gstermektedir. Switching srecinin QFW'un QSR turn-on/turn-off'a zorlamas ile yada bamsz bir ekilde kendi drive sinyalini deitirmesiyle gerekletiini sylemek daha doru olur.

QSR'n turn-on srecei QFW'n turn-off sreci ile balar. QFW'un gate drive sinyali yksekten de getiinde, node geileride input voltajlar GND seviyesine ekilerek gerekleir. CRSS kapasitr boalana kadar akm forward haldedir ve QSR'n body diyotu forward bias dir. O anda Senkronize mosfet akm akn alr ve QFW'u tamamen turn-off eder. Kontrolorleririn kapasitanlar ile domine edilmi kk bir gecikmeden sonra QSR'n gate drive sinyadi uygulanr ve Mosfet turn-on edilir. Bu srada alo nody diyottan aletin kanallarna akmaya balar. QSR'n bu iletim peryodunun sonunda Mosfet turn-off olmaldr. Bu sre drive sinyalinin senkronize swithchin gatinden alnmas ile balatlr. Bu olay aletin

turn-off olmasn tek bana salamaz. Bunun yerine, bu olay akmn kanallar yerine bodydiyot zerinden akmasn zorlar. Forward switchin dkten yksek seviyeye gemesi ile akm QSRdan QFW'a kaymaya balar. Birkere tam yk akm QFW tarafndan alndnda ve body diyotu tamamen recover edildilir. GND dzeyinden input dzeyine Switching node geileri gerekleir. Bu geiler srasnda QSR'n CRSS kapasitr arj olur ve senkronize Mosfet, dv/dt tarafndan indklenen turn-on'a duyarldr. Bu operasyonu zetleyecek olursak, turn-on ve turn-off srelerinin ikisinde de senkronize Mosfet 'in dv/dt 'si forwar switchin gate drive karekteristii tarafndan zorlanr. Bu nedenle, iki gate drive devresi de birlikte tasarlanarak, birbirlerine gre hzlar ve dv/dt snrlar birbirleri ile uyumlu hale getirilmelidir. Bu aadaki hesap admlar gerekletirilerek baarlabilinir.

Assuming the same devices for QSR and QFW, no external gate resistors, and that the internal gate resistance is negligible compared to the drivers output impedance, the ratio of the driver output impedances can be approximated by: QSR ve QFW 'ayn devicelar olduu, harici bir gate direncinin bulunmad ve driver output empedansna re gate i direncinin ok ok kk olduu durumlarda, driver output empedans oran yaklak loarak aadaki gibi hesaplanabilir:

A typical example with logic level MOSFETs driven by a 10V drive signal would yield a ratio of 0.417, which means that the pull down drive impedance of QSR must be less than 42% of the pull up drive impedance of QFW. When carrying out these calculations, remember that every parameter except VDRV is temperature dependent and their values might have to be adjusted to reflect the worst case operating conditions of the design. 10V lik bir drive sinyaliyle srem tipik bir logic Mosfette bu oaran 0.417 gibi bir deere denkgelir ki bu QSR'n pull-down drive empedansnn QWF'nin pull-up drive empedansndan %42 daha dk olmas gerektii anlamna gelir. Bu hesaplar yapllrken VDRV dndaki tm parametrelerin scaklk ile deitii aklda tutulmal ve deerler en kt senerya iin seilmelidir.

HIGH SIDE NON-ISOLATED GATE DRIVES

High side non-isolated gate drive circuits can be classified by the device type they are driving or by the type of drive circuit involved. Accordingly, they are differentiated whether P-channel or N-channel devices are used or whether they implement direct drive, level shifted drive, or bootstrap technique. Which ever way, the design of high side drivers need more attention and the following checklist might be useful to cover all aspects of the design: Efficiency Bias / power requirements Speed limitations Maximum duty-cycle limit dv/dt implications Start-up conditions Transient operation Bypass capacitor size Layout, grounding considerations

YKSEK TARAFI ZOLE EDLMEM GATE DRIVELAR

Yksek taraf izole edilmemi gate drive devreleri src deverleri olarak yada src ieren devreler olarak snflandrlabilir. Dolaysyla P-channel / N-chanel olmalarna yada direcktdrive yada bootstrap almalarna gre gre birbirlerinden ayrrlar. Hangisi olursa olsun, yksek taras izole edilmemi srclerin tasarmlarna daha zen gsterilmeli ve aadaki kontrol listesinin tm gerekleri yerine getirilmelidir. Verimlilik Bias / g gereksinimleri Hz snrlamalar Maksimum grev dngs (duty-cycle) snr dv/dt gereklilikleri Start-up artlar Gei sreleri Bypass kapasitr byklkleri Grounding

High side drivers for P-channel devices In this group of circuits the source terminal of the P-channel MOSFET switch is connected to the positive input rail. The driver applies a negative amplitude turn-on signal to the gate with respect to the source of the device. This means that the output of the PWM controller has to be inverted and referenced to the positive input rail. Because the input voltage can be

considered as a DC voltage source, high side P-channel drivers do not have to swing between large potential differences on the switching frequency basis, but they must work over the entire input voltage range. Moreover, the driver is referenced to an AC ground potential due to the low AC impedance of the input voltage source. P-Channel yksek kenar srcler Bu eit devrelerde P-Channel Mosfet'in source terminali pozitif input giriine balanmtr. Src gate'e aletin kaynagna gre negatif genlikli turn-on sinyali uygular. Bu PVM kontrol devresinin knn invert edilmesi ve referansn pozitif input railinden almas anlamna gelir. nput voltaj DC volyaj kaynagi gibi dnlebileceinden , yksek kenar P-Channel srcler seitching frekans temelinde geni bir voltaj araln taramak zorunda deildir. Ancak tm voltaj aralnda alabilir olmak zorundadrlar. Ayrca, input voltaj kaynann dk AC empedans nedeniyle, src AC ground'a referanslanmtr. P-channel direct drive The easiest case of P-channel high side drivers is direct drive, which can be implemented if the maximum input voltage is less then the gatetosource breakdown voltage of the device. A typical application area is 12V input DC/DC converters using a P-channel MOSFET, similar to the schematic in Figure 18. Note the inverted PWM output signal is readily available in some dedicated controllers for P-channel devices. P-Channel direct src P-channel srclerin en kolay hali direct srclerdir. Eer maksimum input voltaj gate-tosource breakdown voltajndan daha dkse bu yaklam uygulanabilir. Tipik uygulama alan 12 volt input DC/DC eviricilerdir. Benzer bir uyguluma figr 18 de gsterilmektedir. nvert edilmi PVM output sinyalinin baz P-channel adanm (dedicated) kontrolrlerde mevcut olduunu not etmekte fayda var.

ekil 18. Dorudan src P-channel MOSFET

The operation of the circuit is similar to the ground referenced direct driver for N-channel devices. The significant difference is the path of the gate drive current, which never flows in the ground connections. Instead, the high charge and discharge currents of the gate are conducted by the positive rail interconnection. Consequently, to minimize the loop inductance in the gate drive, wide traces or a plane is desirable for the positive input. Devrenin almas ground referansl N-channel direct srclere benzerdir. En temel farklar gate-drive akmnn izleyecegi yoldur. Bunda akm hi bir zaman ground balantlardan akmaz. Bunun yerine, yksek sarj ve desarj akmlar pozitif rail ile birletirilmitir. Sonu olarak, gate drive iindeki loop'u minimize etmek iin pozitif inputlarda geni yollar ve geni tabla vazgeilmezdir. P-channel level shifted drive For input voltages exceeding the gate-to-source voltage limit of the MOSFET, level shifted gate drive circuits are necessary. The simplest level shift technique is using an open collector driver as shown in Figure 19. Unfortunately, open collector level shifters are not suitable for driving MOSFETs directly in a high speed application. P-channel level shifted src Mosfetin gate-to-source voltaj snrn aan input voltajlar iin level-shifted gate src devrelerinin kullanlmas gerekmektedir. En basit level-shifted teknii figr 19 gsterildii gibi bir ak kollektr driver kullanmaktr. Neyazk ki k-kollektr level-shifters yksek hzl uygulamalarda mosfetleri srmek iin uygun deillerdir.

ekil 19. Ak kollektr PMOS src Problems are numerous with this implementation starting with the limited input voltage range due to the voltage rating of the open collector transistor. But the most inhibiting obstacle is the high drive impedance. Both resistors, ROFF and RGATE must be a high value resistor to limit

the continuous current in the driver during the conduction period of the switch. Furthermore, the gate drive amplitude depends on the resistor divider ratio and the input voltage level. Switching speed and dv/dt immunity are severely limited which excludes this circuit from switching applications. Nevertheless, this very simple level shift interface can be used for driving switches in inrush current limiters or similar applications where speed is not an important consideration. Figure 20 shows a level shifted gate drive circuit which is suitable for high speed applications and works seamlessly with regular PWM controllers. The open collector level shift principle can be easily recognized at the input of a bipolar totempole driver stage. The level shifter serves two purposes in this implementation; it inverts the WM output and references the PWM signal to the input rail. The turn-on speed is fast, defined by RGATE and R2. During the on-time of the switch a small DC current flows in the level shifter keeping the driver biased in the right state. Both the gate drive power and the level shift current are provided by the positive input of the power stage which is usually well bypassed. Bu implementasyon pekok sorunuda beraberinde getirir. Bunlardan birtanesi, ak kollektr transistrn voltaj oranlamasndan kaynakl giri voltaj aralnn ok snrl olmasdr. Ancak daha nemli bir sorun yksek src empedansdr. ki dire de (ROFF ve RGATE) switchingin iletim sresi boyunca srekli akm lsnrlayabilecek kadar yksek deerli olmaldrlar. Dahas, gate src genlii diren src oran ve input voltaj seviyesine baldr. Switching hz ve dv/dt bamll bu devrenin bulunmad switching uygulamalarnda olduka snrldr. Yinede bu ok basit seviyedi shift uygulamas, hzn ok nemli olmad inrush akm snrlayclarda yada benzeri uyulamalarda switchleri srmek iin kullanlabilir. elik 20 de level ykseltilmi bir gate drive uygulamas gsterilmektedir. Bu uygulama yksek hzl uygulamalar ve normal PWM denetleyiciler iin olduka uygundur. Ak kollektr level-ykseltme prensibi burda bipolar totempole src ksmnda net olarak grlebilmektedir.. Bu uygulamada level-ykseltici iki amaca hizmet eder. Birincisi WM kn invert ederek PWM sinyalini input railine referanslar. RGATE ve R2 tarafndan kontrol edilen turn-on hz yksektir. alma sreci boyunda kk bir DC akm level-ykseltici zerinden akarak srcy bias eder ve onu dogru durumda tutar. Gate dtive enerjisi ve level-shift akm ou zaman bypass edilen power nitesinin pozitif inputu tarafndan salanr.

ekil 20. Level-shifted MOSFETdriver P-kanal src

The power consumption of the driver has a frequency dependent portion based on the gate charge of the main switch and a duty-cycle and input voltage dependent portion due to the current flowing in the level shifter. One of the drawbacks of this circuit is that VDRV is still a function of the input voltage due to the R1, R2 divider. In most cases protection circuits might be needed to prevent excessive voltage across the gate-to-source terminals. Another potential difficulty is the saturation of the npn level shift transistor, which can extend the turnoff time otherwise defined by R1 and RGATE. Fortunately both of these shortcomings can be addressed by moving R2 between the emitter of QINV and GND. The resulting circuit provides constant gate drive amplitude and fast, symmetrical switching speed during turn-on and turn-off. The dv/dt immunity of the driver scheme is primarily set by the R1 resistor. A lower value resistor will improve the immunity against dv/dt induced turn-on but also increases the power losses of the level shifter. Also, notice that this solution has a built in self-biasing mechanism during power up. While the PWM controller is still inactive, QINV is off and the gate of the main MOSFET is held below its threshold by R1 and the upper npn transistor of the totempole driver. Pay specific attention to rapid input voltage transients though as they could cause dv/dt induced turn-on during the off state of the P-channel MOSFET transistor. Srcnn g tketimimin frekansa bal ksm main switchin gate ykne ve grev dngsnne baldr. G tketiminin input voltajna bal ksm ise level-shiftern zerinden akan akma baldr.

Bu devrenin kt noktalarndan birtanesi ise VDRV hala R1ve R2 den kaynakl olarak input voltajnn bir fonksiyonudur. ou zaman gate-to-source terminallerinden akabilecek ar voltaja kar koruma devereleri ne ihtiya vardr. Bir dier potansiyel tehlike ise npn level shift transistrnn satre olma ihtimalidir ki bu turn-off zamannn uzamansna neden olur. Ancak bu iki problemi R2 yi QINVnin emiteri ve GND arasna yerletirerek zmek mmkndr. Ortaya kacak devre sabit gate drive genlii salamakla birlikte hzl ve simetrik bir un-on turn-off sreci salar. Ayrca bu devre power-up srasnda dahili bir self-biasing mekanizmasna sahiptir. PWM denetleyicinin aktif olmad durumda, QINV off ve Mosfetin ana gate'i R1 taradndan eik deerinin altnda , totem pole driverin npn transistrnnn zerinde tutar. In general, the DC level shift drivers have relatively low efficiency and are power dissipation limited above a certain input voltage level. The fundamental trade-off is to balance the switching speed and the power consumption of the level shifter to meet all requirements under the entire input voltage range.

Genel olarak, DC level-shift srcler greceli dk verimlidirler ve g kayb belli bir input

seviyesinin zerine snrlanmtr. Level-shifter yaklamnda switching hz g harcamasndan daha nemlidir.

High side direct drivers for N-channel devices The majority of power supply applications utilize N-channel MOSFETs as the main power switch because of their lower price, higher speed and lower on-resistance. Using N-channel devices as a high side switch necessitates a gate drive circuit which is referenced to the source of the MOSFET. The driver must tolerate the violent voltage swings occurring during the switching transitions and drive the gate of the MOSFET above the positive supply rail of the power supply. In most cases, the gate drive voltage must be above the highest DC potential available in the circuit. All these difficulties make the high side driver design a challenging task. N-channel sistemler iin yksek kenar direct srcler Dk fiyat avantajlar, daha yksek hzlar ve dk direnleri nedeniyle, power supply uygulamalarnn byk ounluunda ana power switch olarak N-channel Mosfetler kullanlr. N-channel aletleri yksek kenar switch olarak kullanmak Mosfet source'una referans edilmi bir gate drive deveresi gerektirir. Driver switching geileri srasnda oluabilecek ani voltaj dalgalanmalarn totare edebilecek nitelikte olmaldr. ou durumda, gate drive voltaj devredeki bulunablecek potansiyel DC deerinden yksek olmaldr. Tm bu zorluklar yksek kenar src tasarmn nemli kllamktadr. High side direct drive for N-channel MOSFET In the easiest high side applications the MOSFET can be driven directly by the PWM controller or by a ground referenced driver. Two conditions must be met for this application: A typical application schematic is illustrated in Figure 21 with an optional pnp turn-off circuit. N-channel Mosfet iin yksek kenar direct src En basit uygulamada, Mosfet dogrudan PWM denetleyici yada ground-referansl src taradndan srlebiliri. Bunun iin iki art olumaldr.

Bu uygulama ekil 21 de opsiyonel pnp turn-off devresi ile ematik olarak verilmitir.

ekil 21. N Dorudan src kanall MOSFET Looking at the basic operation of the circuit neglect the pnp turn-off transistor for now there are two major differences with this configuration compared to the ground referenced drive scheme. Since the drain is connected to the positive DC input rail, the switching action takes place at the source terminal of the device. It is still the same clamped inductive switching with identical turnon and turn-off intervals. But from gate drive design point of view this is a completely different circuit. Notice that the gate drive current can not return to ground at the source terminal. Instead it must go through the load, connected to the source of the device. In discontinuous inductor current mode the gate charge current must go through the output inductor and the load. In continuous inductor current mode, however, the loop can be closed through the conducting pn junction of the rectifier diode. At turn-off, the gate discharge current comes through the rectifier diode connected between ground and the source of the MOSFET. In all operating modes, both the charge and discharge currents of the CGD capacitor flow through the high frequency bypass capacitor of the power stage. The net result of all these differences is the increased parasitic source inductance due to more components and larger loop area involved in the gate drive circuitry. As presented earlier, the source inductance has a negative feedback effect on the gate drive and slows down the switching actions in the circuit. The other significant difference in high side direct drive is the behavior of the source the switching node of the circuit. Paying close attention to the source waveform of the MOSFET during turn-off, a large negative voltage can be observed. Figure 22 illustrates this rather complex switching action. As the turn-off is initiated by pulling the gate terminal toward ground, the input capacitances of the MOSFET are quickly discharged to the Miller plateau voltage. The device is still fully on, the entire load current is flowing through the drain to the source and the voltage drop is small. Next, in the Miller region, the MOSFET works as a source follower.

The source falls together with the gate, and while the voltage across the drain-to-source increases,the gate-to-source voltage remains constant at the VGS,Miller level. The dv/dt is limited by the gate drive impedance and the CGD capacitor of the device. Once the source falls 0.7V or so below ground, the rectifier diode is supposed to clamp the switching node to ground.

Devernin temel almasna baktmzda, burada imdilik pnp turn-off transistrn gz ard edelim. Ground referansl src emasyla karlatrldnda iki temel farkllk vardr. Drain pozitif DC giri rail'ine baland iin, switching olay aletin source terminalinde gerekleir. Bu hala turn-off ve turn-on srecleri ayn olan bir swtiching olaydr. Ancak gate tasarm tarafndan bakacak olursak bu tamamen farkl bir devredir. Dikkat edecek olursak gate drive akm source terminali zerinden grounda geri dnmemektetir. Onun yerine aletin source'una balanm olan load zerinden gitmektedir. Srekli olamayan (kesintili) akm modunda gate yk akm output indktr ve load' zerinden gitmelidir. Srekli indktr akm modunda ise rekfier diyodun pn balantsn geerek kapal bir loop olturur. Turn off srecinde gate dearj akm mosfetin kayna ve ground arasna balanm rectifier diyotu zerinden gelir. Tm akma modelarnda CGD'nin hem arj hem dejarz akm power katmannn yksek frekans bypass kapasitr zerinden akar. Tm bunlarn sonucu olarak, deveredki loop alan geniledigi iin parazitik source indktans artm olur. Daha ncede anlatld gibi source indktans gate drive zerinde negatif feedback'e sahiptir. Devredeki svitching olayn yavalatr. Yksek kenar direct drive uygulamasndaki dier bir nemli fark ise, source2un davranlardr. Turn-off srasnda Mosfetin source dalga yapsna zel bir zen gsterdiimizde byk bir negatif voltaj gzlenebilir. Figr 22 de daha az kark bir durum gsterilmektedir. Turn-off olay gate terminalinin grounda ekilmesiye tetiklendii iin Mosfetin input kapasitanslar hzlca desarj olarak Miller platosu seviyesine gelir. Alet hala alyor durumdadr, yk akmnn tamam drainden kaynaga doru akar ve voltaj dmesi kktr. Sonrasnda, Miller blgesinde, Mosfet bir kaynak takipcisi gibi davranr. Kaynak gate ile birlikte der, drain-to-source voltaj geii artarken gate-to-source voltaj degeri VGS_Miller seviyesinde sabit kalr. dv/dt gate drive empedans ve CGD kapasitr tarafndan snrlandrlmtr. Kaynak birkere 0.7 V yada grounda dtnde rektifier diyodunun switchig ucunu grounda kenetlemesi beklenir.

Actually, the source can fall way below ground for a short period of time until the rectifier diode gets through its forward recovery process and the current overcomes the effect of the parasitic inductances. After the load current is completely transferred from the MOSFET to the diode, the switching node can return to its final voltage, adiode drop below ground. This negative excursion of the source voltage represents a significant problem for the gate drive circuit. Slow diodes, high parasitic inductance values can cause excessive negative voltage at the source of the MOSFET, and can pull the output pin of the driver below ground. To protect the driver, a low forward voltage drop Schottky diode might be connected between the output pin and ground as indicated in Figure 21. Another aspect to consider is when the gate terminal reaches 0V, the gate discharge current would become zero. Further negative pull on the gate terminal and the MOSFET starts turning back on. Ultimately the system finds a very delicate equilibrium where the gate discharge current and the voltage drop across the parasitic inductances result the same di/dt in the device current. Even the optional turn-off speed-up circuit shown in Figure 21 can not help during the negative voltage spike of the switching junction. The pnp transistor will turn-off when the gate falls to a VBE above ground and the MOSFET is left on it own during the negative voltage transient. Also, pay attention to the reduced noise tolerance during the off state of the main switch. The source is several hundred millivolts below ground and the gate is held at approximately 0.7V above ground. This positive voltage across the gate with respect to the source is dangerously close to the threshold voltage especially for logic level devices and at elevated temperatures. Aslnda source ksa bir zaman dilimi iin rektifier diyodu forward recovery ilemine balayana kadar ve akm parazitik indktanslarn etlilerini alt edene kadar groundun altna debilir. Load akm Mosfetten diyoda tamamen aktarldktan sonra, switching ucu final voltaj deerine geri dnerbilir. Source voltajnn bu negatif yolculugu gate drive devresininin nemli bir problemine iaret etmektedir. Yava diyodlar, yksek parazitik inktans degerleri Mosfetin source voltaj deerinde ar deerlere neden olabilir ve srcnn output pinini groundun altna drebilir. Srcy korumak iin, dk forward voltaj schottky diyotu gorunt ve output pini arasna ekil 21 de gsterildii gibi yerletirilebilir. Gz nnde bulundurulmas gereken bir baka ey ise, gate terminali 0V a ulatnda, gate deraj akm da 0 olur ve mosfetin gate terminalinde yeni bir nagatif d tekrar olumaya balar. Sonu olarak sistem ok hassas bir dengeye ular ki burada gate desarj akm ve parazitik indktanslar zerindeki voltaj dmesi aletin akmnda ayn di/dt ye neden olur. Bootstrap gate drive technique Where input voltage levels prohibit the use of direct gate drive circuits for high side N-channel MOSFETs, the principle of bootstrap gate drive technique can be considered. This method utilizes a gate drive and accompanying bias circuit, both referenced to the source of the main MOSFET transistor. Both the driver and the bias circuit swing between the two input voltage rails together with the source of the device. However, the driver and its floating bias can be implemented by low voltage circuit elements since the input voltage is never applied across their components. The driver and the ground referenced control signal are linked by a level shift circuit which must tolerate the high voltage difference and

considerable capacitive switching currents between the floating high side and ground referenced low side circuits. Bootstrap driver gate teknii N-Channel Mmosfetlerde input voltaj seviyesinin direct drive gate devresinin kullanmna olanak tanmado durumlarda bootstrap gatedirve tekniinin kullanm bir seenek olarak deerlendirilebilir. Bu method, gate drive bisas devresi ile kullanr. kiside mosfet transistrnn sorsuna referans edilmitir. Hem driver hem de bias devresi iki imput voltaj seviyesi arasnda haraket eder. Ncak src ve onun deiken bias' dk voltaj devre elemanlar ile implement edilebilir. nk input voltaj hi bir zaman devre alemanlar arasna uyulanmayacaktr. Src ve ground referansl kontrol sinyali level-shift devresine ilikilendirilmitir. Bylece devre yksek voltaj deiimlerini toolore edebilecektir. Discrete high performance floating driver A typical implementation representing the bootstrap principle is displayed in Figure 23. The ground referenced PWM controller or MOSFET driver is represented by its local bypass capacitor and the output pin. The basic building blocks of the bootstrap gate drive circuit can be easily recognized. The level-shift circuit is comprised of the bootstrap diode QBST, R1, R2 and the level shift transistor, QLS. The bootstrap capacitor, CBST, a totem-pole bipolar driver and the usual gate resistor are the floating, source referenced part of the bootstrap solution This particular implementation can be used very effectively in 12V to approximately 24V systems with simple low cost PWM controllers which have no floating driver on board. It is beneficial that the IC voltage rating does not limit the input voltage level. Furthermore, the level shift circuit is a source switched small NMOS transisto which does not draw any current during the on time of the main MOSFET from the bootstra capacitor. It is an important feature to maintain high efficiency in the level shifter, and to extend the maximum on-time of the main switch. The operation can be summarized as follows: when the PWM output goes high to turn on the main MOSFET, the level shift transistor turns off. R1 supports the base current to the upper npn transistor in the totem-pole driver and the main MOSFET turns on. The gate charge is taken fro the bootstrap capacitor, CBST. As the switch turns on, its source swings to the positive input rail. The bootstrap diode and transistor block the input voltage and power to the driver is provided from the bootstrap capacitor. At turn-off, the PWM output goes low turning on the level shift transistor. Ayrk yksek performans kayan src Bootstrap tegniini gsteren tipik bir uygulama figr 23 de gsterilmitir. Grounda refareansl PWM denetleyici yada Mosfet src kendi local bypass kapasitrleri ive output pinleri ile gsterilmitir. Bootstrap gate drive devresinin temel yaptalar kolayca grlebilir. Level-shift devresi botstrapn QBST,R1,R2 ve QLS (level-shift transistmr) ne denk gelir. Bootstrap kapasitr CBST, bipolar devresi ve genel gate direncleri bootstrap zmnn floatin (kayan, dalalanana) paralardr. Bu zm 12V- ve 24 V arasndaki sistemlerde dk maliyetli zerinde floating devresi olmayan sistemlerde ok etkin bir biimde kullanlabilir. IC voltaj oranlarnn input voltaj seviyelerini snrlamamas ok fayda salar. Ayrca level-shift devresi Mosfetin on olduu

zaman boyunca bootstrap kapasitrnden hi akm geirmeyen source anahtarlamal basit bir NMOS transistrdr. Ana switchin maksimum alma zamann arttrmak ve level-shifter in yksek verimliligini koruyabilmek nemli bir itir. Tm ileyi yle zetlenebilir: PWM k ana fosfeti turn-on yapmak iin high olduunda level-shifter transistr turn-off olur. R1 direnci base akmnda totem-pole srcnn npn transistrn destekler. Ve ana mosfet turn-on olur. Gate yk bootstrap kapasitrt olan C_BST'den alnr. Switch turn-on olduundan, switchin kayna pozitif input rail'ine kayar. Bootstrap diyodu ve transistr input voltajn ve bootsrap kapasitr tarafndan salanan power' bloke eder. Turn-off srasnda PWM k der ve level-shifter transistr turn-on olur.

Current starts to flow in R1 and R2 towards ground and the lower pnp transistor of the totempole driver turns on. As the gate of the main MOSFET discharges, the drain-to-source voltage increases and the source transitions to ground, allowing the rectifier to turn-on. During the off time of the main switch, the bootstrap capacitor is recharged to the VDRV level through the bootstrap diode. This current is supplied by the CDRV bypass capacitor of the ground referenced circuitry and it goes through DBST, CBST, and the conducting rectifier component. This is the basic operating principle of the bootstrap technique. Integrated bootstrap drivers In medium input voltage applications, mainly 24V or 48V telecom systems, most of the bootstrap components can be integrated into the PWM controller as illustrated in Figure 24. Akmm R1 ve R2 zerinden grounda doru akmaya balar ve totem-pole srcnn dk pnp transistr turn-on olur. Ana mosfetin gatei dearj oldugundan drain-to-source voltaj ve grounda geiler artarak rektifiern turn-on olmasn salar. Ana switchin off sresi boyunda, bootstrap kapasitr VDRV seviyesine kadar yeniden arj olur. Akm, ground referansl devrenin CDRV bypass kapasitr tarafndan salanr ve DBST,CBST zerinden akarak

rektifier bileenlerine ular. Bu bootstrap tekniinin en basit uygulamasdr. Entegre bootstrap srcleri Orta seviye giri voltaj uygulamalarnda, genellikle 24V yada 48V telekom sistemlerinde, bootstrap bileenlerinin byk bir ksm fir 24 te belirtildii gibi PWM denetleyici ierisine dahil edilebilir.

ekil 24 bootstrap srcs For even higher voltages, dedicated driver ICs are available to ease the design of bootstrap gate drive with up to 600V rating. These high voltage ICs are differentiated by their unique level shift design. In order to maintain high efficiency and manageable power dissipation, the level shifters should not draw any current during the on-time of the main switch. Even a modest 1mA current In the level shift transistors might result in close to 0.5W worst case power dissipation in the driver IC. A widely used technique for these applications is called pulsed latch level translators and they are revealed in Figure 25. Daha yksek voltajlar iin dahi, adanm IC devreler mevcuttur ve 600V a kadar bootstrap gate drive tasarmlarnn kolayca gerekletirilmelerine katkda bulunurlar. Bu yksek voltaj IC devreleri zgn tasarmlar ile dierlerinden ayrlmaktadlar. Yksek verimlilii ve g kayplarn ynetebilmek iin level shifterlar zerinden ana switchin on sresi boyunca akm gememelidir. Level-shifter transistrlerinden akacak 1mA akm bile IC srcsnde 0.5W 'a yakn bir g kaybna neden olabilir. Bu tr uygulamalar iin oka kullanlan bir teknik ise ekil 25 de gsterildii gibi pulsed-latch level transistrlerin kullanlmasdr.

ekil 25 Yksek voltaj IC srclerde tipik level-shifter As indicated in the drawing, the PWM input signal is translated to ON/OFF commands. The short pulses generated at the rising and falling edges drive the level shift transistor pair which interfaces with the high side circuitry. Accordingly, the floating portion of the driver is modified as well, the level shifted command ignals have to be differentiated from noise and 24 must be latched for proper action. This operation results in lower power dissipation because of the short duration of the current in the level shifter but lowers noise immunity since the command signal is not present at the input of the driver continuously. The typical pulse width in a 600V rated pulsed latch level translator is around 120 nanoseconds. This time interval adds to natural delays in the driver and shows up as turn-on and turn-off delays in the operation and is indicated in the data sheet of the drivers. Due to the longer than optimum delays, the operating frequency range of the high voltage gate driver ICs is limited below a couple of hundreds of kHz. Some lower voltage high side driver ICs (up to 100V) use continuous current DC level shift circuits to eliminate the delay of the pulse discriminator, therefore they support highe operating frequency. izimde belirtildii gibi, PWM input sinyalleri ON/OFF komutlarna tercme edilir. Ykselen ve den kenarlarda retilen ksa sinyallerle level-shift transistr hangi interfacin yksek kenar devresiyle elecei belirlenir. Dolaysyla srcnn kayan (floating) ksm modifiye edilmi olur, seviyesi kaydrlm (level-shifted) komut sinyalleri devredeki grltden ayrlarak gerekli eylemler yerine getirilmi olmaldr. Bu operasyon level-shifterdan akan akmn ksa sreli olmas deneniyle g kaybnn dmesini salar ancak dk grlt baklgna neden olur nk komut sinyalleri srcnn inputunda srekli olarak bulunmamaktadr. 600Vluk latch-level-transistr bir sistemde tipik sinyal geniligi 120 nanosaniye civarndadr. Bu sreye datasheetlerde verilen srcnn turn-on ve turn-off gibi doal gecikmelerde eklenmitir. Optimum gecikmelerden daha uzun olmas sebebiyle Icli yksek voltaj src devrelerinin alma frekanslar birka Khznin altndadr. Baz dk voltaj yksek kenat src Icleri (100V ye kadar) kesintisiz (srekli) DC akm level-shift devreleri kullanarak pulse ayracncaki gecikmeleri nler ve bu sayede maksimum alma frekans elde edilir.

Bootstrap switching action Bootstrap gate drive circuits are used with high side N-channel MOSFET transistors as shown in Figure 26. The switching transitions of the high side switch were explored previously with respect to the high side N- hannel direct drive scheme and are equally applicable with bootstrap drivers. The biggest difficulty with this circuit is the negative voltage present at the source of the device during turn-off. As shown previously, the amplitude of the negative voltage is proportional to the parasitic inductance connecting the source of the main MOSFET to ground (including the parasitic inductance associated with the rectifier) and the turn-off speed (di/dt) of the device as determined primarily by the gate drive resistor, RGATE and input capacitor, CISS. This negative voltage can be serious trouble for the drivers output stage since it directly affects the source pin often called SRC or VS pin of the driver or PWM IC and might pull some of the internal circuitry significantly below ground. The other problem caused by the negative voltage transient is the possibility to develop an over voltage across the bootstrap capacitor. Capacitor CBST will be peak charged by DBST from CDRV. Since CDRV is referenced to ground, the maximum voltage which can build on the bootstrap capacitor is the sum of VDRV and th amplitude of the negative voltage at the source terminal. A small resistor in series with the bootstrap diode can mitigate the problem. Unfortunately, the series resistor does not provide a foolproof solution against an over voltage and it also slows down the recharge process of the bootstrap capacitor. Bootstrap switching Bootstrap gate src devreleri figr26 da gsterildii gibi yksek kenar N-Channel Mosfet transistrleri ile kullanlrlar. Yksek kenar switchin geileri daha ncesinden yksek-kenar N-channel dricet drive src emalarnda gsterilmiti. Burada da ayn yaklam geerlidir. Budaraki en byk zorluk chazn off olduu durumlarda da kaynakta mevcut olan negatif voltajn varldr. Daha nceden de gsterildii gibi, Negatif voltajn genlii ana Mosfetin kaynan grounda balayan parazitik induktansla orantldr ve cihazn turn-off hz (di/dt) byk lde gate drive denci olan RGATE ve input kapasitr CISS tarafndan belirlenir. Bahsedilen negafit voltaj srcnn outputu iin diddi sorunlar yaratabilir nk dorudan PWMin ICsinin source pinleri olan SRC yasa VS pinini etkiler ve dahili devrelerin bir ksmn groundun altna ekebilir. Negatif voltajn neden olduu bir baka sorun ise, bootsrap kapasitrnn zerinde ar boltaj geiinin oluma ihtimalidir. CBST kapasitr CDRV deki DBST tarafndan peak olarak arj edilecektir. CDRV ground referansl olduu in bootstrap kapasitr tarafndanoluturulacak maksimum voltaj VDRVnin ve soruce terminalindeki voltajn toplam kadar olacaktr. Bootstrap diyodyba seri olarak balanmi bir diren bu sorunu zmeye yardmc olabilir. Ancak Bu zm ne yazkki garanti bir zm deildir ve ayrca bootstrap kapasitrnn arjn da yavalatr.

Figr 26: Bootstrap gate srcs iin yksek voltaj IC devresi A circuit to deliver very effective protection for the SRC pin is given in Figure 27. It involves relocating the gate resistor from the gate to the source lead between the driver and the main MOSFET and adding a small, low forward voltage drop Schottky diode from ground to the SRC pin of the driver. Yukarda bahseilen probklem iin daha iyi bir ozm ekil 27'de gsterilmitir. Bu zmde SRC pininden grounda low forward Schotky diyodu eklenmi ve gate drenci yeniden konumlandrlmtr.

In this circuit, RGATE has a double purpose; it sets the turn-on and turn-off speed in the MOSFET and also provides current limiting for the Schottky diode during the negative voltage transient of the source terminal of the main switch. Now, the switching node can swing several volts below ground without disturbing the operation of the driver. In addition, the bootstrap capacitor is protected against over voltage by the two diodes connected to the two ends of CBST. The only potential hazard presented by this circuit is that the charge current of the bootstrap capacitor must go through RGATE. The time constant of CBST and RGATE slows the recharge process which might be a limiting factor as the PWM duty ratio approaches unity. Bootstrap biasing, transient issues and start-up Figure 28 shows a typical application diagram of the bootstrap gate driv technique. There are four important bypass capacitors marked on the schematic. The bootstrap capacitor, CBST is the most important component from the design point of view, since it has to filter the high peak current charging the gate of the main MOSFET while providing bias for the source referenced floating circuitry. In every switching cycle during normal operation, the bootstrap capacitor provides the total gate charge (QG) to turn-on the MOSFET, the reverse recovery charge (QRR) and leakage current of the bootstrap diode (ILK,D, the quiescent current of the level shifter (IQ,LS) and the gate driver (IQ,DRV), and the leakage current between the gate-source terminals (IGS), including the current drawn by a potential gateto- source pullv down resistor. Some of these currents flow only during the ontime of the main switch and some of them might be zero depending on the actual implementation of the driver and level shifter.

Bu devrede, RGATE ift amaladr. lk olarak Mosfet'in turn-on ve turn-off hzn ayarlar. Ikinci olarak ana switchin source terminalinde negatif voltaj geii srasnda Schottky diyotunun akmn snrlar. Bu sayede bu swiching nodu , ihazn normal almasn etkinenmeden deiik voltaj aralklarnda hareket edebilir. Ek olarak, bootstrap kapasitr CBST'nin iki ucuna balanm iki diyot tarafondan yksek voltaj gei ihtimallerine kar korunmu bulunmaktadr. Bu devrede oluabilecek tek bir potansiyel tekhike bulunmaktadr, o da, bootsrap kapasitrnn arj olmas iin gereken akm RGATE zerinden akmaktadr. CBST ve RGATEin zaman sabitleri resarj ilemini bir miktar yavalatarak PWM grev zamanlamalarnda, gelerde bir limit faktr gibi rol oynayabilir. Bootstrap biasing, transient issues and start-up ekil 28'de bootstrap gatte drive tekniinin tipik bir uygulama diyagram gsterilmektedir. emada 4 nemli bypass kapasitr bulunmaktadr. Bootstrap kapasitr CBST, tasarm bak asndan bunlar arasndaki en nemlisidir. Cnk ana mosfetin gateinin arj srasnda devreye bias yaparken ayn zmanada yksek peak akmlar da filitreler. Her bir swithing dngsnde, bootstrap kapasitr Mosfet'in turn-on ilemi srasnda toplam gate ykn (QG) , reverse recovery ykn (QRR) ve dootsrab diyodunun kesinti akmnu (ILK,D)

ce level-shifter iin IQ,LS akmn, gate src iin IQ,DRv akmn ce gate-source terminalleri arasnda IGS akmn salar. Bu akmlardan bazlar sadece on-time srasnda akarken bazlar o srada 0 dr. Bu devrenin tasarmna gre deiebiilir.

ekil 28. Bootstrap bypass rnegi

Assuming steady state operation, the following general equation can be used to calculate the bootstrap capacitor value to achieve the targeted ripple voltage, VBST: stikrarl alma durumu gz nne alndnda, ihtiya duyulan bootstrap bypass kapasitr deerini hesaplamak iin aadaki formuller kullanlabilir.

burada

To finalize the bootstrap capacitor value, two extreme operating conditions must be checked as well. During load transients it might be necessary to keep the main switch on or off for several switching cycles. In order to ensure uninterrupted operation under these circumstances, the CBST capacitor must store enough energy to hold the floating bias

voltage above the under voltage lockout threshold of the high side driver IC for an extended period of time. Going from light load to heavy load, certain controllers can keep the main switch on continuously until the output inductor current reaches the load current value. The maximum on time (tON,MAX) is usually defined by the value and the voltage differential across the output inductor. For these cases, a minimum bootstrap capacitor value can be established as: Bootstrap kapasitr deerinin son haline erimek iin, alma koullarnn iki ar ucu gz nne alnmaldr. Yk geileri srasnda birka swtiching dngsnde ana switchi on yada off tutmak gerekli oabilir. Bu koullarda cihazn kesintisiz bir ekilde alacandan emin olmak iin , CBST kapasitr yeterli kadar byk olmal ve floatin bias voltajn high site IC devresnin lockout eiinin zerinde uzam alma evresinin sonuna kadar tutabilmelidir. Hafif ykten ar yke doru giderken, output indktr akm load akm deerine ulancaya kadar baz temel kontroller ana switchin srkliligini salamada yardmc olabilir. Maksimum on-time (tON,MAX) genellikle output indktrndeki voltaj farkllklar tarafndan belirlenir. Byle durumlar iin, minimum bootstrap kapasitr deeri aadaki gibi bulunabilir.

where VBST is the initial value of the bootstrap bias voltage across CBST and VUVLO is the under voltage lockout threshold of the driver. With a discrete floating driver implementation, VUVLO could be substituted by the minimum safe gate drive voltage. Any load transient in the other direction will require pulse skipping when the MOSFET stays off for several switching cycles. When the output inductor current reaches zero, the source of the main switch will settle at the output voltage level. The bootstrap capacitor must supply all the usual discharge current components and store enough energy to be able to turn-on the switch at the end of the idle period. Similar to the previous transient mode, a minimum capacitor value canbe calculated as: burada VBST bootsrap bias voltajnn CBST zerindeki ilk deeridir ve VUVLO srcnn lockout voltaj eik deeridir. Ayrk floating src uygulamasnda VUVLO yerine minimum gvenli gate drive voltaj kullanlabilir. Dier ynde herhangi bir yk geii Mostefin birka switching dngs srasnda off kalmasn gerektirir. Output indiktrn zerindeki akm 0'a ulatnda ana switching source'u output voltaj seviyesine set edilir. Bootstrap kapasitr tm akmn ve idle peryodunun sonunda switch'i turn-on yapmak iin gerekli olan enerjiyi salayabilmelidir. ncekine benzer bir ekilde minimum kapasitr deeri aadaki gibi hesaplanr.

In certain applications, like in battery chargers, the output voltage might be present before input power is applied to the converter. In these cases, the source of the main MOSFET and the negative node of CBST are sitting at the output voltage and the bootstrap diode might be reverse biased at start-up. Delivering the initial charge to the bootstrap capacitor might not be possible depending on the potential difference between the bias and output voltage levels. Assuming there is enough voltage differential between the input and output voltages, a simple circuit comprised of RSTART resistor, DSTART diode, and DZ zener diode can solve the startup problem as shown in Figure 29. Baz tip uygulamalarda, (rnek olarak batarya sarj uygulamalarnda) output voltaj konverter'a input power' uygulanmadan nce mevcut bulunabilir. Bu tr durumlarda, ana mosfet ve CBST'nin negatif ucu output voltajnda oturuyot olabilir ve vootstrap diyotu start-up srasnda reverse biased olabilir. Bias ve output voltaj seviyeleri arasndaki farka bal olarak bootstrap kapasitrne ilk yk gndermek herzaman mmkn olmayabilir. nput ve output voltajlar arasnda yeterli farkn bulunduunu kabul ederek, ekil 29 da gsterilen RSTART direnci, DSTART diyodu ve DZ zener diyotundan olumu basit devre ile bu start-up problemini amak mmkndr.

ekil 29. Bootstrap start-up devresi In this start-up circuit, DSTART serves as a second bootstrap diode used for charging the bootstrap capacitor at power up. CBST will be charged to the zener voltage of DZ which is supposed to be higher than the drivers bias voltage during normal operation. The charge current of the bootstrap capacitor and the zener current are limited by the start-up resistor. For best efficiency the value of RSTART should be selecte to limit the current to a low value

since the second bootstrap path through the start-up diode is permanently in the circuit. Bu stat-up devresinde, DSTART power-up srasnda bootstrap kapasitrn arj etmek iin kullanlan ikinci bir bootstrap diyodu gibi i grr. CBST kapasitr Dznin voltaj deerine kadar sarj edilecektir ki bu normal almada srcnn bias voltaj deerinden yksektir. Bootstrap kapasitrnn sarj akm ve zener akm start-up direnci tarafndan snrlandrlmtr. En iyi verim iin RSTART direncinin deeri akm deerini dk tutacak ekilde seilmelidir, nk startup diyodu ile oluturulan ikinci bootstrap yolu devrede kalc bir biimde bulunacaktr. Grounding considerations There are three important grounding issues which have to be addressed with respect to the optimum layout design of the bootstrap gate drivers with high side N-channel MOSFETs. Figure 28 can be used to identify the most critical high current loops in a typical application. The first focus is to confine the high peak currents of the gate in a minimal physical area. Considering the path the gate current must pass through, it might be a challenging task. At turnon, the path involves the bootstrap capacitor, the turn-on transistor of the driver, the gate resistor, the gate terminal, and finally, the loop is closed at the source of the main MOSFET where CBST is referenced. The turn-off procedure is more complicated as the gate current has two separate components. The discharge current of the CGS capacitor is well localized, it flows through the gate resistor, the turn-off transistor of the driver and from the source to the gate of the power MOSFET. On the other hand, the CGD capacitors current must go through RGATE, the turn-off transistor of the driver, the output filter, and finally the input capacitor of the power stage (CIN). All three loops carrying the gate drive currents have to be minimized on the printed circuit board. The second high current path includes the bootstrap capacitor, the bootstrap diode, the local ground referenced bypass capacitor of the driver, and the rectifier diode or transistor of the power stage. CBST is recharged on the cycle-by-cycle basis through the bootstrap diode from the ground referenced driver capacitor, CDRV, connected from the anode of DBST to ground. The recharge happens in a short time interval and involves high peak current. Therefore, the high side driver must be bypassed locally on its input side as well. According to the rule-ofthumb, CDRV should be an order of magnitude larger than CBST. Minimizing this loop area on the printed circuit board is equally important to ensure reliable operation. The third issue with the circuit is to contain the parasitic capacitive currents flowing between power ground and the floating circuitry in a lo impedance loop. The goal is to steer these currents away from the ground of the sensitive analog control parts. Figure 30 reveals the parasitic capacitive current paths in two representative applications with high side driverICs Topraklama zerine Yksek kenar N-Channel Mosfetlerle bootstrap gate driverlarn bir arada kullanld tarasmlarda topraklama ile ilgili 3 nemli konu gz nnde bulundurulmaldr. Figr 28, tipik bir uygulamada en kritik yksek akm loopunu gstermek iin kullanlabilir. Birinci nemli konu, gatin yksek peak akmn olabildiince kk bir fizksel alanda tutmaktr. Gate akmnn gececei yolu gz nnde bulundurarak, bu zor ve nemli bir i

olabilir. Turn-on srasnda, bu yol bootsrap kapasitrn, srcnn turn-on transistrn, gate direncini, gate terminalini ve CBST ye referanslanm ana mosfeti de iine alarak bir loop oluturur. Gate iki ayr bileenden olutuu iin turn-of sreci daha da karktr. CGD kapasitrnn dearj akm iyi lokalize olmutur. Bu akm gate direnci, turn off transistr ve power moosfetinin kayna zerinden akar. Dier taraftan aslnda CGD akm RGATE , turn off transistr, output filitresii ce power katmannn input kapasitr (CIN) zerinden akmaldr. Tm bu loop da akan gate akm minimize edilmelidir. kinci yksek akm yolu bootstrap kapasitr, bootstrap diyodu, devrenin lokal ground referansl bypass kapasitr rektifier diyodu yada power katmannn transistrnden oluur. CBST bootsrap diyodu zerinden ground referasnl driver kapasitr CDRV ve DBST tarafndan cycle-by_cycle (adm adm, dng dng) rearj edilir. Rearj ksa bir sre iinde yksek bir peak akm ile gerekleir. Dolaysyla yksek kenar src local olarak kendi inputu tarafndan bybass edilmelidir. Sa el (ba parmak ) kuralna gre, CDRV CBSTnin deerinin ok ok zerinde olmaldr. Bu loopu bask devre zerinde minimize etmek sistemin dzgn almas asndan da ok nemlidir. Gz ninde bulundurulmas gereken 3. ey ise, empedans loopunda power ground ve devre aranda akan parazitik etkili akmdr. Kural olarak bu akm hassas anolog kontrol bileenlerinin olabildiince uzendan gemelidir. Figur30 da yksek kenar Iclerin ullanld iki uygulamada bu parazitik kapasitif akm yolununun durumu gsterilmektedir.

ekil 30. Yksek kenar uygylamalarda kapasitif akmlar. Single high side driver ICs usually have only one GND connection. Since the capacitive currents must return to the ground potential of the power stage, the low side portion of the IC should be referenced to power ground. This is counterintuitive, since the control signal of the driver is referenced to signal ground. Nevertheless, eliminating the high capacitive current component between analog and power ground will also ensure that the potential difference between the two grounds are minimized. The situation is greatly improved with general purpose half bridge driver ICs which contain one low side and one high side driver in the same package. These circuits have two ground connections usually labeled as GND and COM, providing more flexibility in layout. To return the capacitive currents to power ground in the shortest possible route, the COM pin is connected to power ground. The GND pin can be utilized to provide connection to the signal ground of the controller to achieve maximum noise immunity. For completeness, the bypass capacitor of the PWM controller should be mentioned as well, which is placed near to the VCC and GND pins of the IC. Referring to Figure 28 again, CBIAS is a relatively small capacitor with respect to CBST and CDRV since it provides only high frequency bypassing and it is not involved in the gate drive process. Tek yksek kenar IC genellikle sadece bir adet GND balantsna sahiptir. Kapastif akmlarn power katmannn grounduna geri gnmesi gerektiinden, Icnin dk kenar blm power katmanna referasnlanmaldr. Bu beklenenin aksine bi durumdur, nk srcnn kontrol sinyali sinyal grounduna referasnlanmtr. Yinede analog ve power gorundlar arasndaki yksek kapasitif akm bielenlerini elimine etmek iki ground arasndaki potansiyel fark minimize edecektir. Bu durum genel amal yar-kpr (half-bridge) src ICleri ile daha da iyi hale getirilmitir. Bunlar bir dk kenar ve bir yksek kenar srcy ayn paket iinde sunmaktadrlar. Vu deveker iki ground balantsna sahiptirler ve bu baglantlar tasarmda esneklik salamak amacyla genelliklle GND ve COM olarak adlandrlrlar. Kapasitif akmlarn power grounduna mmkn olan en ksa yoldan geri dnmesi iin, COM pini power grounduna balanr. GND pini maksimum grlt bakl salanmas amac ile denetleyicinin sinyal grounduna balanr. Btnlk asndan PWM denetleyicinin bypass kapasitrnden de bahsedilmelidir. Bu kapasitr Icnin VCC ve GND pinlerinin yaknlarna yerletirilmelidir. Tekarar figr 28'e bakacak olursak CBIAS CBST ve CDRV ye gre kk bir kapasitr saylr. nk sadece yksek firekans bypass salar ve gate drive srecinde yer almaz.

NC KISIMIN SONU

AC COUPLED GATE DRIVE CIRCUITS

AC coupling in the gate drive path provides a simple level shift for the gate drive signal. The primary purpose of AC coupling is to modify the turn-on and turn-off gate voltages of the main

MOSFET as opposed to high side gate drives where the key interest is to bridge large potential differences. In a ground referenced example like the one in Figure 31, the gate is driven between -VCL and VDRV-VCL levels instead of the original output voltage levels of the driver, 0V and VDRV. The voltage, VCL is determined by the diode clamp network and it is developed across the coupling capacitor. The benefit of this technique is a simple way to provide negative bias for the gate at turn-off and during the off state of the switch to improve the turn-off speed and the dv/dt immunity of the MOSFET. The trade-off is slightly reduced turn-on speed and potentially higher RDS(on) resistance because of the lower positive drive voltage. The fundamental components o f AC coupling are the coupling capacitor CC and the gate-tosource load resistor RGS.

AC COUPLED GATE SRC DEVRELERI

Gate src yolunda AC elemesi gate drive sinyali iin kolay bir level shift salar. AC elemesinin temel amac, yksek voltajlarlar ilgilenen yksek kenar gate srclerinin tersine ana Mosfetin turn-on ve turn-off voltajlarn modifiye edebilmektir. Figr 31 deki gibi ground referansl rneklerde, orjinal output voltaj seviyesi (0V ve VDRV) yerine gate -VCL ve VDRV-VCL voltaj seviyeleri arasnda srrr. VCL degeri kenetlenme network ve onun eleme kapasitr tarafndan belirlenir. Bu teknigin temel amac, turn-off ve switchin off sresi boyunca gatee negatif bias salamaktr. Bylece Mosfetin turn-off hz ve dv/dt bakl artmaktadr. Bunun bedeli, turn-off hznda birazck dme ve dk pozitif src voltajndan kaynakl daha yksek bir RDS direncidir. AC coupling'in temel bileenleri eleme (coupling)kapasitr CC ve gate-to-source direnci RGS'dir.

The resistor plays a crucial role during power up, pulling the gate low. This is the only mechanism keeping the MOSFET off at start up due to the blocking effect of the coupling capacitor between the output of the driver and the gate of the device. In addition, RGS provides a path for a current across the coupling capacitor. Without this current component the voltage would not be allowed to build across CC. Theoretically, in every switching cycle the same amount of total ate charge would be delivered then removed hrough the capacitor and the net charge passing through CC would be zero. The same concept can be applied for steady state operation to determine the DC voltage across the coupling capacitor with RGS in the circuit. Assuming no clamp circuitry, a constant VC voltage across the capacitor, and a constant duty cycle D, the current of RGS can be represented as an additional charge component passing through CC. Accordingly, the total charge delivered through the coupling capacitor during turn-on and consecutive on-time of the MOSFET is: Diren power up srasnda, gate'i lowa ekerek hayati bir rol oynamaktadr. Bu Mosfeti startup srasnda off tutabilmek iin uygulanabilecek tek yntemdir. Ek olarak RGS eleme kapasitr akm iin bir yol salar. Bu akm bileeni olmadan voltaj CC zerinden akmay gerekletiremez. Teorik olarak, her bir switching dngsnde ayni miktarda toplam gate yk datlr ve sonrasnda kapasitrden uzaklatrlr ve CC den geen net yk 0 olur. Ayn yaklam, steady-state operasyonlara uygulanarak eleme kapasitr zerinden akan voltaja RGS ile karar mmkndr. Kapasitr zerinden akan akmn voltajnn sabit ve VC olduunu, grev sabir dngsnn D olduunu varsayarak RGS zerinden geen akm CC nin ek bir yk bileeni olarak tanmlanabilir. Ayrca Mosfetin turn-on srasnda ve devamndaki on- sresi boyunda CC tarafndan datlan toplam yk aadaki gibi hesaplanr:

Following the same considerations for the turnoff and successive off-time of the switch, the total charge can be calculated as: For steady state operation, the two charges must be equal.. Solving the equations for VC determines the voltage across the coupling capacitor. This well know relationship highlights the duty ratio dependency of the coupling capacitor voltage. As duty cycle varies, VC is changing and the turn-on and turn-off voltages of the MOSFET adjust accordingly. As Figure 32 exemplifies, at low duty cycles the negative bias during turn-off is reduced, while at large duty ratios the turn-on voltage becomes insufficient.

Ayn yaklamlar turn-off ve devamndaki off sresi iin uyulayarak, toplam yk aadaki gibi hesaplanabilir.

Steady-state operasyonlar iin, iki yk birbirine eit olmaldr. VC iin denklemleri ozerek CC zerindeki voltaj aadaki gibi hesaplanr:

Bu iyi bilinen balant, CC voltajnn duty ratio'suna bamlln gstermektedir. Duty deitii in VC de deiit ve Mosfetin turn on turn off voltajlar buna gre ayarlanr. Figr 32 gsterilirki dk drev dnglerinde negatif bias ile turn-off azaltlrken geni grev ratiolarnda turn of voltaj yetersiz kalmaktadr.

The inadequate turn-on voltage at large duty ratios can be resolved by using a clamp circuit connected in parallel to RGS as shown in Figure 31. Its effect on the coupling capacitor voltage is also shown in Figure 32. As the coupling capacitor voltage is limited by the clamp, the nmaximum negative bias voltage of the gate is determined. Since the gate drive amplitude is not effected by the AC coupling circuit, a minimum turn-on voltage can be guaranteed for the entire duty cycle range. Figr 31 de gsterildii gibi, geni duty oranlarnda yetersiz turn-on voltaj RGSye paralel balanm bir clamp devresi ile yeterli hale getirilebilir. Bu devrenin etkisi figr32 de de gsterilmitir. Eleme kapasitrnn voltaj deeri clamp taradmdan snrlandrlarak, gate'teki maksimum negatif bias deeri belirlenmi olmaktadr. Gate drive genlii AC eleme devresinden etkilenmedii iin, minimum turn-on voltaj tm grev dngs srasnda garani edilmi olunur. Calculating the coupling capacitor The amount of charge going through CC in every switching cycle causes an AC ripple across thecoupling capacitor on the switching frequency basis. Obviously, this voltage change should be kept relatively small compared to the amplitude of the drive voltage. The ripple voltage can be calculated based on the charge defined previously as: Coupling kapasitrnn hesaplanmas Her switching dngsnde CC resinden geen yk miktar, CC zerinde frekans temelli bir AC dalalanmasna neden olur. Bu voltaj dalalanmas, src voltajyla karlatrldnda olabildiince kk tutulmaldr. Bu dalgalanan voltaj yk temelinde aadaki gibi hesaplanr.

Taking into account that Vc=DVDRV, the equation can be rearranged to yield the desired capacitor value as well: Vc = D VDRV olduunu dikkate alarak, denklem aadaki gibi yeniden dzenlenerek ihtiya duyulan kapasitr deeri aadaki gibi olur.

The expression reveals a maximum at D=0.5. A good rule of thumb is to limit the worst case AC ripple amplitude (Vc) to approximately 10% of VDRV.

Bu ifadeden D=0.5 maksimum deereri eldedeilir. Buradanda AC dalalanma genlii ( vc) yaklak olarak VDRV nin %10'udur.

Start up transient of the coupling capacitor Before the desired minimum coupling capacitor value could be calculated, one more parameter must be defined. The value of RGS has to be selected. In order to make an intelligent decision the start up transient of the AC coupling circuit must be examined. At power up, the initial voltage across CC is zero. As the output of the driver start switching the DC voltage across the coupling capacitor builds up gradually until it reaches its steady state value, VC. The duration to develop VC across CC depends on the time constant defined by CC and RGS. Therefore, to achieve a target start-up transient time and a certain ripple voltage of the coupling capacitor at the same time, the two parameters must be calculated together. Fortunately, there are two equations for two unknowns: Eleme (coupling) kapasitrnn start-up sreleri Gerek duyulan eleme kapasitr deerinin hesaplanmasndan nce, bir paremetre daha tanmlanmaldr. RGS degeri seilmelidir. Uygun bir seim yapabilmek iin AC eleme devresinin star-up sreleri dikkatlice incelenmelidir. Power-up srasnda, CC zerindeki balang voltaj deeri 0'dr. Srcnn outputu swithinge balad iin, CC zerindeki DC voltaj deeri giderek bymektedir taki steady deerine (VC) ulaana kadar. Bu srenin uzunlugu CC ve RGS tarafndan belirlenen zaman sabitlerine baldr. Bu nedenle, hedeflenen start-up zamann ve belirli kapasitr voltaj dalgalanma genliini elde etmek iin iki paremetre birlikte hesaplanmaldr. Bu iki bilinmeyen iin iki denklemimiz mevcuttur.

which will yield a single solution. Substituting the expression for RGS from the second equation, D=0.5 for worst case condition and targeting Vc=0.1VDRV, the first equation can be solved and simplified for a minimum capacitor value: Bu denklemlerin tek bir zm vardr. RGS iin olan ifadeyi ikinci deklemden alp yerine koyarak D=0.5 , en kt artlarda ve tek bir zm verecek. , D = 0.5 kt durumda durum iin ve Vc = 0,1 VDRV 'yi heefleyerek, ilk denklem minimum kapasitr deeri iin zlerel aadaki deer elde edilir:

Once CC,MIN is calculated, its value and the desired start-up time constant () defines the required pull down resistance. A typical design trade-off for AC coupled drives is to balance efficiency and transient time constant. For quicker adjustment of the coupling capacitor voltage under varying duty ratios, higher current must be allowed in the gate-to-source resistor. CC deeri birke hesaplandktan sonra, bu deer ve ihtiya duyulan start-up zaman sabiti () kullanlarak ihtiya duyulan pull-down direnci hesaplanabilir. Bu tr devrelerin temel tasarm amaz verimliligi ve gei zaman sabitlerini dengelemektir. Deien duty ratio'lar altnda eleme kapasitrnn abucak ayarlanmas iin gate-to-sorce direncinde yksek akm geilerine izin verilmelidir.

TRANSFORMER COUPLED GATE DRIVES

Before the appearance of high voltage gate drive ICs, using a gate drive transformer was the only viable solution to drive high side switches in offline or similar high voltage circuits. The two solutions coexist today, both have their pros and cons serving different applications. The integrated high side drivers are convenient, use smaller circuit board area but have significant turn-on and turn-off delays. The properly designed transformer coupled solution has negligible delays and it can operate across higher potential differences. Usually it takes more components and requires the design of a transformer or at least the u nderstanding of its operation and specification. Before concentrating on the gate drive circuits, some common issues pertinent to all transformer designs and their correlation to gate drive transformers will be reviewed. Transformers have at least two windings. Theuse of separate primary and secondary windings facilitates isolation. The turns ratio between primary and secondary allows voltage scaling. In the gate drive transformer voltage scaling is usually not required, but isolation is an important feature. Ideally the transformer stores no energy, there is no exemption. The so called flyback transformer really is coupled inductors. Nevertheless, small amounts of energy are stored in real transformers in the nonmagnetic regions between the windings and in small air gaps where the core halves come together. This energy storage is represented by the leakage and magnetizing inductance. In power transformers, reducing the leakage inductance is important to minimize energy storage thus to maintain high efficiency. The gate drive transformer handles very low average power, but it delivers high peak currents at turn-on and turn-off. To avoid time delays in the gate drive path, low leakage inductance is still imperative. Faradays law requires that the average voltage across the transformer winding must be zero over a period of time. Even a small DC component can cause flux walk and eventual

core saturation. This rule will have a substantial impact on the design of transformer coupled gate drives controlled by single ended PWM circuits. Core saturation limits the applied volt-second product across the windings. The transformer design must anticipate the maximum voltsecond product under all operating conditions which must include worst case transients with maximum duty ratio and maximum input voltage at the same time. The only relaxation for gate drive transformer design is their regulated supply voltage. A significant portion of the switching period might be reserved to reset the core of the main power transformer in single ended applications, (working only in the first quadrant of the B-H plane) such as the forward converter. The reset time interval limits the operating duty ratio of the transformer. This is rarely an issue even in single ended gate drive transformer designs because they must be AC coupled thus they operate with bi-directional magnetization.

TRANSFORMATR COUPLED GATE SRCLER

Yksek voltaj IC devrelerinin ortaya kndan nce, yksek kenar switchleri srmek icin offline yada benzer yksek voltaj devrelerinde gate drive transformator kullanmak neredeyse bir zorunluluktu. Bugn iki zm ayn anda mevcut bulunmakta. Uygulamann eitine gre iki zmn de artlar ve eksileri bulunmakta. Yksek voltaj IC devreleri boar zerinde az yer kaplayp kullanm kolay olmasna ragmen turn-off ve turn-on gecikmeleri okyksektir. Uygyun bir ekilde tasarlanm transformatr coupled devresi ile neredeyse hic bir gecikme olmadan yksek voltajlarda anahtarlama yaplabilmektedir. Genellikle bu tr bir devre tasarlamak daha fazla devre bileeni kullanmay ve ou zaman bir transformatr yapmn, en azndan trasformatrn tm yapsn ve zelliklerini ok iyi bilmeyi gerektirmektedir. Gate drive devrelerine konssantre olmadan nce, tm transformatr tasarmlar il ve onlarn gate src trasformatrleri ile alakal baz temel konular gzden geirmekte fayda bulunmaktadr. Trasformatrlerde en az iki sarg bulunmaktadr. Primary ve sekondary sarglarn kullanlmas izalasyonu salar. Sarlarn birbirine oran output voltaj seviyesini deitirir (scaling). Gate drive transformatrlerde voltaj deiimi (scaling) ok gerekli deildir. Ancak izalosyon ok nemli bir zelliktir. deal trasnformatrler enerji depolamaz. BU konuda herhangi bir muafiyet yoktur. Trasformatorler aslnda iki aded elenmi (soupled) indiktrdr. Ancak gerek hayatta, trasformatrler manyetik olmayan blgelerinde zellikle iki sarnn ve aradaki trasformatr ekirdeinin birletii hava boluklarnda kk bir miktar enerjiyi depolarlar. Bu enerji depolanmas kayp ve mknatslayan indktans solarak gsterilecektir. G trasnformatrlerinde, kayp indktans enerji depolanmasn minimize etmek ve dolaysyla verimi arttrmak iin ok nemlidir. Gate drive trasnformatrleri ok dk ortalama glerde alr ancak turn on ve turn off srasnda yksek peak akm degerlerini salayabilir.Gate drive path'inde zaman gecikmelerinden kanmak iin yinede dk kayp indktans elzemdir. Faraday yasasna gre, bir zaman peryodunda trasformatr sarglar zerindeki ortalama voltaj 0'dr. Trasformatr tasarmlarnn, maksimm i yk ve en kt artlarda bile voltsaniye arpmnn maksimum olacak ekilde yaplmas gerekmektedir. Gate drive

transformatr iin tek relaxation sadece kendi regle edilmi power supply voltajlardr. Single-end uygulamalarda (B-H dzleminin sadece ilk ereinde alan) uygulamalarda, switching peryodunun nemli bir ksm ana transformatrnn ekirdeinin resetlenmesi iin rezerve edilmi olabilir. Bu single-ended gate drive transformatr tasatmlarnda ok nadir olan bireydir. nk AC coupled olmak ve di-directional manyetizasyon ile almak zorundadrlar. Single ended transformer coupled gate drive circuits These gate drive circuits are used in conjunction with a single output PWM controller to drive a high side switch. Figure 33 shows the basic circuit. The coupling capacitor must be placed in series with the primary winding of the gate drive transformer to provide the reset voltage for the magnetizing inductance. Without the capacitor there would be a duty ratio dependent DC voltage across the winding and the transformer would saturate. Figure 33. Single ended transformer coupledgate drive Single-ended trasformatr elenmi gate drive devreleri Bu eit gate drive devreleri tek kl PWM denetleyiciler ile birlikte yksek kenar switchi srmek iin kullanlr. Figr33 te basit bir devre gsterilmitir. Elenmi (coupling) kapasitr gate drive trasnformatrnn pirimer sarsna seri balanarak manyetize indktans iin reset voltajn salar. Bu kapasitr olmadan sarglar zerinde duty ratio'ya bal bir DC voltaj olurdu ve trasformatr satre olurdu.

The DC voltage (VC) of CC develops the same way as shown in AC coupled direct drives. Th steady state value of the coupling capacitor voltage is:

Similar to AC coupled direct drives, the actual gate drive voltage, VC, changes with duty ratio. In addition, sudden changes in duty ratio will excite the L-C resonant tank formed by the magnetizing inductance of the gate drive transformer and the coupling capacitor. In most cases this L-C resonance can be damped by inserting a low value resistor (RC) in series with CC. The value of RC is determined by the characteristic impedance of the resonant circuit and given as: CC nin DC voltaj (VC) AC coupled gate drivelardaki givi etki gsterir. Coupling kapasitrn steady-state'deki deeri :

AC coupled srclere benzer bir biimde, gerek gate drive voltaj, VC, duty ratio ile deiiklik gsterir. Ek olarak, duty ratiodaki ani deiiklikler gate drive transformatrnn manyetik indktans ve coupling kapasitr tarafndan belirlenmi olan L-C resonant tank'a etki edecektir. Pek ok durumda bu L-C rezonans CC ye seri, dk deerli bir diren (RC) eklenerek damped edilebilir. Rc nin deeri dezonant devrenin karakteristii tarafndan belirlenir.

Keep in mind that the RC value defined in the equation above is the equivalent series resistance which includes the output impedance of the PWM driver. Additionally, consider that a critically damped response in the coupling capacitor voltage might require unreasonable high resistor value. This would limit the gate current, consequently the switching speed of the main switch. On the other hand, underdamped response may result in unacceptable voltage stress across the gate source terminals during the resonance. The current building VC has two components; the magnetizing current of the transformer and the current flowing in the pull down resistor connected between the gate and the source of the main MOSFET. Accordingly, the start-up and transient time constant governing the adjust speed of the coupling capacitor voltage ref lects the effect of the magnetizing inductance of the gate drive transformer and can be estimated by:

Unutmamak gerekir ki, denklem tarafndan verilen Rc deeri e seri diren deerine denktir. Ki bu deer PWM srcnn output empedans deerini de iermektedir. Ek olarak, coupilng

kapasitr voltajnn kritik olarak dumped evab anlamsz olarak cok yksek diren deeri gerektirebilir. Bu gate akm dolaysyla ana switching hzn limitleyecektir. Dier taraftan rezonans srasnda , dk seviyede damped edilmesi gate source terminallerinde kabul edilemeyecek dzeyde voltaj stresi yaratabilir. Vc ile akan akmn iki bileeni vardr; transformatrn manyetize akm ve ana Mosfet'in gate ve source'una balanm pull-down direncinden akan akm. Dolaysyla stur-up ve gei zaman sabitleri coupling kapasitr voltajnn ayar hzn belirleyer. Gate drive transformatrnn manyetize akmnn bu deer zerindeki etkisi aadaki gibi hesaplanr.

The magnetizing inductance has another significant effect on the net current of the driver, and on its direction. Figure 34 highlights the different current components flowing in the circuit and the sum of the current components, IOUT, which has to be provided by the driver. Figure 34. Driver output current with transformer coupled gate drive Manyetize indktans, net src akm ve onun yn zerinde dier bir nemli etkiye daha sahiptir. Figr34 te devre zerinden akkan deiik akm bileenleri ve akm bileenlerinin toplam, IOUT ki src bunu salayabilimeidir, gsterilmektedir.

Figure 34. Trasformatr coupled gate drive srcde src k akmlar Note the gray shaded area in the output current waveform. The output driver is in its low state which means it is supposed to sink current. But because of the magnetizing current component, the driver actually sources current. Therefore, the output must handle bidirectional current with transformer coupled gate drives. This might require additional diodes if the driver is not capable of carrying current in both directions. Bipolar MOSFET drivers are a typical example where a Schottky diode has to be connected between the ground and the output pin. Similar situation can occur during the high state of the driver at different duty cycle or current component values. One easy remedy to solve this problem and avoid the diodes on the drivers output is to increase the resistive current component to offset the effect of the magnetizing current. At wide duty cycles, like in the buck converter, the circuit of Figure 33 does not provide adequate gate drive voltage. The coupling capacitor voltage increases proportionally to the duty ratio. Accordingly, the negative bias during off-time increases as well and the turn-on voltage decreases. Adding two small components on the secondary side of the gate drive transformer can prevent this situation. Figure 35 shows a commonly used technique to restore the original voltage levels of the gate drive pulse. Akm waveformundaki gri taral blgeye dikkatli bakmak gerekir. Driver outputu kendi dk seviyesinde (low state), ki bu akmn buraya akyor olduu dnlebilir. Ancak manyetize akm bileeni nedeniyle aslnda driver akm kaynadr. Bu nedenle trasformer coupled devrelerde kn bi-rirectional olduu unutulmamaldr. Eer src iki ynl akm tamaya uygun deilse, bu nedenle ek diyotlar kullanmak gerekebilir. Bipolar Mosfet srcler Shotky diyotlarnn ground ve output ucuna baland tipik rneklerdir. Benzer durum srcnn yksek dzeyde (high state) olduu farkl grev dngleri yada akm bileenleri iin de geerlidir. Bu durumu kolayca diyot kullanmadan zebilmek iin, rezistif akm bileenini manyetize akmm offsetleyecek dzeye kadar arttrarak zebilirsiniz. Geni grev dnglerinde (meseka buck cevirici uygulamalarnda) figr 33 deki devre uygun gate drive voltajn salayamaz. Coupling kapasitr voltaj duty ratio ile orantl olarak artar. Bylece off-time srasnda negatif bias artar, turn-on srasnda da voltaj der. Gate drive transformatrnn ikincil tarafna iki kk devreelamannn eklenmesi bu durumu zebilir. Figr35 de gate drive sinyalinin orjinal seviseyine kartlmas iin ska kullanlan bir teknik gsterilmektedir.

Figure 35. DC restore circuit in transformer coupled gate drive Here, a second coupling capacitor (CC2) and asimple diode clamp (DC2) are used to restore the original gate drive amplitude on the secondary side of the transformer. If a larger negative bias is desired during the off time of the main switch, a Zener diode can be added in series with the diode in a similar fashion as it is shown in Figure 31, with respect to the AC coupled direct drive solution. Burada ikinci coupling kapasitmr (CC2) ve basit bir ketentleme diyodu (DC') kullanlarak trasformatrn ikincil blmnde gate drive genligi orjinal deerine restore edilmitir. Eer ana switchin off-time' srasnda daha yksek bir negatif bias gerekiyor ise, bir Zener diyot ekil 31 gsterilene benze bir ekilde diyoda seri bir ekilde ekleklenebilir.

Calculating the coupling capacitors The method to calculate the coupling capacitor values is based on the maximum allowable ripple voltage and the amount of charge passing through the capacitor in steady state operation was described in the previous AC coupled circuits. The equation for CC2 is similar to the one identified for direct coupled gate drive circuit. The ripple has two components; one is related to the total gate charge of the main MOSFET and a second component due to the current flowing in the gate pull down resistor: Coupling kapasitrlerin hesaplanmas Coupling kapasitrlerin deerlerinin hesaplanmas iin aada tanmlanan yntem, devrenin stabil alr durumda (steady state), daha nce tanmlanm AC coupled devredeki gibi, kapasitr zerinden geecek maksimum yk ve izin verilen maksimum voltaj dalgalanmas deerine gre oluturulmutur. CC2 iin geerli olan denklem direct-coupled gate drive devresindekine benzerdir. Ripple (dalgalanma) iki bileene sahiptir; ilki na Mosfetin toplam

gate yk ile alakal, ikincisi ise gate pull down direncinden akan akm ile alakaldr.

This expression has a maximum at the maximum on-time of the switch, i.e. at maximum duty ratio. In the primary side coupling capacitor the magnetizing current of the gate drive transformer generates an additional ripple component. Its effect is reflected in the following equation which can be used to calculate the primary side coupling capacitor value: Bu ifade, switchin maksimimum on-time'nda (rnek olarak maksimum duty ratio'da) maksimum deere ular. Coupling kapasitrn birincil tarafnda gate dirive transformatrnn manyetize edici akm ek bir dalgalanma (ripple) bileeni retir. Bu etki aadaki denlemlerde hesaba dahil edil edilerek birincil taraftaki coupling kapasitrnn deerinin hesaplanmasnda kullanlmtr.

The minimum capacitance to guarantee to stay below the targeted ripple voltage under all operating conditions can be found by determining the maximum of the above expression. Unfortunately the maximum occurs at different duty ratios depending on the actual design parameters and component values. In the majority of practical solutions it falls between D=0.6 and D=0.8 range. Also note that the sum of the ripple voltages, VC1+VC2 appears at the gate terminal of the main MOSFET transistor. When aiming for aparticular ripple voltage or droop at the gate terminal, it has to be split between the two coupling capacitors. Tm alma koullarnda ripple voltajnn hedeflenen deerin altnda kalmasn salayacak (garanti edecek) minimum kapasitans deeri yukardaki ifadenin maksimum deerini bularak elde edilebilir. Ne yazk ki maksimum deger devre tasarmna ve kullanlan devre elemanlarna gre farkl duty ratiolarda gereklemektedir. Pratik uygulamalarn pek ogunda bu deer D=0.6 ve D=0.8 arasna dmektedir. Ayrca ripple voltajlarn toplamlarna baktmzda ana Mosfet transistrmn gate terminalinde VC1+VC2 grlmektedir. Gate terminalinde belirli bir voltaj dalgalanmasn yada dmesini hedeflediimizde, deer iki coupling kapasitr arasnda split edilmek zorundadr. Gate drive transformer design

The function of the gate drive transformer is to transmit the ground referenced gate drive pulse across large potential differences to accommodate floating drive implementations. Like all transformers, it can be used to incorporate voltage scaling, although it is rarely required. It handles low power but high peak currents to drive the gate of a power MOSFET. The gate drive transformer is driven by a variable pulse width as a function of the PWM duty ratio and either constant or variable amplitude depending on the circuit configuration. In the single ended circuits the gate drive transformer is AC coupled and the magnetizing inductance sees a variable amplitude pulse. The double ended arrangements, such as half-bridge applications, drive the gate drive transformer with a constant amplitude signal. In all cases, the gate drive transformers are operated in both, the first and third quadrant of the B-H plane. The gate drive transformer design is very similar to a power transformer design. The turns ratio is usually one, and the temperature rise due to power dissipation is usually negligible.Accordingly, the design can be started with the core selection. Typical core shapes for gate drive transformer include toroidal , RM, P or similar cores. The core material is high permeability ferrite to maximize the magnetizing inductance value, consequently lower the magnetizing current. Seasoned designers can pick the core size from experience or it can be determined based on the area product estimation in the same way as it is required in power transformer design. Once the core is selected, the number of turns of the primary winding can be calculated by the following equation: Gate drive tranformer tasarm Gate drive transformatrnn fonksiyonu, ground referansl gate drive sinyalini yksek potansiyel farklarna uyum salayacak ekilde floating drive uygulamalarna aktarmaktr. Btn transformatrler gibi, ok nadiren ihtiya olsa da voltaj scaling yapabilirler. Dk glerde (low power) yksek akm deerlerini power Mosfetin gate drive'na salayabilirler. Gate drive transformatr devre yaplandrmasna bal olarak PWM duty ratio'suna bal olarak deiken sinyal genilikli yada sabit sinyal genilikli olarak srlebilirler. Tek ulu (single ended) devrelerde gate dive transformatr AC coupled'dr ve manyetize ndktans deiken genlikli sinyaller grr. Half-bridge uygulamalar gibi ift sonlu (double ended) uygulamalarda gate drive transformatrn sabit genlikli sinyaller ile srmek gerekir. Tm durumlarda, gate drive transformatrleri B-H plane'inin (sre) hem 1. hemde 3. eyreklerinde kullanlmaktadrlar. Gate drive trasnformatr tasarm power transformate tasarmlarna ok benzerler. Sarg oran genellikle 1'dir ve scaklga bal g kayplar genellikle gz ard edilebilir lektedir. Byece, trasnformatr satarm core (ekirdek) tasarm ile balayabilir. Gate drive trasnformatrleri iin tipik ekirdek tasarm troidal, RM, P yada benzer ekirdeklerdir. ekirdek malzemezi yksek permeabilitiye sahip ferrit bir madde olmaldr ki manyetize indktans deeri maksimum dolaysyla manyetize akm da minimum (yada ok dk) olabilsin. Tecrbeli tasarmclar ekirdek byklklerini deneyimlerine gre seebilirler yada power trasformatrler tasrmlarnda doldugu gibi rn tahminleri dorultusunda seebilirler. ekirdek seildikden sonra pirimer sarg iin gerekli sarg says aadaki gibi hesaplanabilir:

where VTR is the voltage across the primary winding, t is the duration of the pulse, B is the peak-to-peak flux change during t, and Ae is the equivalent cross section of the selected core. The first task is to find the maximum volt-second product in the numerator. Figure 36 shows the normalized volt-second product for both single ended and double ended gate drive transformers as the function of the converter duty cycle. burada VTR birincil sarg zerindeki voltaj deeri, t sinyal sresi, B iki peak arasnda t sresinde flux deiimi, Ae trasformatr ekirdeinin denk-kesitidir. Yaplacak ilk i numaratrde maksimum volt-saniye arpmn bulmaktr. Figr36 da single-ended vd doubleended gate drive trasnformatrleri iin maksimum volt-saniye arpmlar konverter grev dngsnn bir fonksiyonu olarak gsterilmektedir.

Figr36 Gate drive transformer volt-second product vs. duty ratio For an AC coupled circuit, the worst case is at D=0.5 while direct coupling reaches the peak volt-second value at the maximum operating duty ratio. Interestingly, the AC coupling reduces the maximum steady state volt-second product by a factor of four because at large duty ratios the transformer voltage is proportionally reduced due to the voltage developing across the coupling capacitor.

It is much more difficult to figure out B in the Np equation. The reason is flux walking during transient operation. When the input voltage or the load are changing rapidly, the duty ratio is adjusted accordingly by the PWM controller. Deducing exact quantitative result for the flux walk is rather difficult. It depends on the control loop response and the time constant of the coupling network when it is present. Generally, slower loop response and a faster time constant have a tendency to reduce flux walking. A three to one margin between saturation flux density and peak flux value under worst case steady state operation is desirable for most designs to cover transient operation. AC coupled bir devre iin, maksimim grev dngsnde direct coupling peak voltaj-saniye deerine ularken en kt durum D=0.5 olmasdr. ngin olarak AC coupling steady state'de (sistemin olagan almas srasnda) maksimum volt-saniye arpmn orannda drmektedir. nk Geni grev dnglerinde trasformer voltaj coupling kapasitrndeki voltaj deerine oaranla dmektedir. B yi Np denkleminde bulmak olduka zordur sebebi ise gei operasyonlar srasndaki flux deiimidir (flux-walkin). nput voltaj yada load'u hzl bir ekide deiirken, grev dngs (duty ratio) PWM denetleyiciye gre ayarlanr. Tam nitelikli bir sonu karabilmek flux walking iin olduka zordur. Kontrol loop'unun tepkisine ve coupling networknn zaman sabitine baldr. Genel olarak yava loop tepkisi ve hzl zaman sabiti fulux walking'i drme eilimdedir. En kt durumda steady state'te 1 e 3 orannda satrasyon flux yogunlugu ve peak flux degeri pek ok tasarmda gei operayonlarn tamamlayabilmek iin zorunludur. The next step is to arrange the windings in the available window area of the core. As mentioned before, the leakage inductance should be minimized to avoid time delay across the transformer, and the AC wire resistance must be kept under control. On toroidal cores, the windings should be wound bifilar or trifilar depending on the number of windings in the gate drive transformer. With pot cores, each winding should be kept in a single layer. The primary should be the closest to the center post, followed by the low side winding, if used, and the high side winding should be the farthest from the center post. This arrangement in pot cores provides an acceptable leakage inductance and the lowest AC winding resistance. Furthermore, natural shielding of the control (primary) winding against capacitive currents flowing between the floating components and power ground is provided by the low side winding which is usually connected to the power ground directly. Sonraki adm ise ekirdein uygun pencere aralnda sarglar sarmaktr. Daha ncede hatrladld zere, trasformerdaki zaman gecikmesini en aza indirmek yada nlemek iin lackage indktans minimize edilmelidir ve AC kablo rezistans kontrol altnda tutulmaldr. Troidal ekirdeklerin kullanld durumlarda, trasformatrn sarg saysna bal olarak sarglar ft telli veya telli olarak sarlmaldr. Pot ekirdeklerde her bir sarg tek bir kademede (single layer) yaplmaldr. Pirimer merkez arkasna olabildiince yakn tutullmal ve dk kenra sarg ile devam edilmeli, ve yksek kenar sarg merkez arkasndan olabildiince uzakta olmaldr. Pot ekirdeklerde bu tarz bir tasarm lackage indktansn kabul edilebilir bir snr altnda tutarak dk AC sarg rezistansn salar. Ayrca floating bileenler arasnda akan kapasitif akmlara kar dk kenar sargnn power grounda dogrudan balanmas ile doal bir shilding salanr.

Dual duty transformer coupled circuits There are high side switching applications where the low output impedance and short propagation delays of a high speed gate drive IC are essential. Figure 37 and Figure 38 show two fundamentally different solutions to provide power as well as control to regular low voltage gate drive ICs in a floating application using only one transformer. Dual duty transformer coupled devreler Dk empedansn ve ksa propagation gecikmelerinin gerekli oldugu yksek hzl gate drive IC lerin kullanld yksek kenar switching uygulamalar bulunmaktadr. Figr37 ve figr38 de sadece 1 trasformatr kullanlarak devreye g salayan ve dk voltaj gate drive IC'sinikontrol eden temelde birbirinden ok farkl iki zm gsterilmektedir.

Figure 37. Power and control transmission with one transformer The circuit of Figure 37 uses the switching frequency to carry the control signal and the power for the driver. The operation is rather simple. During the on-time of the main switch, the positive voltage on the secondary side of the transformer is peak rectified to generate the supply voltage for the gate drive IC. Since the power is generated from the gate drive pulses, the first few drive pulses must charge the bias capacitor. Therefore, it is desirable that the driver IC chosen for this application has an under voltage lock out feature to avoid operation with insufficient gate voltage. As it is shown in the circuit diagram, the DC restoration circuit (CC2 and DC2) must be used to generate a bias voltage for the driver which is independent of the operating duty ratio. DC2 also protects the input of the driver against the negative reset voltage of the transformer secondary winding. The transformer design for this circuit is basically identical to any other gate drive transformer design. The power level is just slightly increased by the power consumption of the driver IC, which is relatively small compared to the power loss associated by the total gate charge of the MOSFET. The transformer carries a high peak current but this current charges the bypass capacitor, not the input capacitance of

theMOSFET. All gate current is contained locally between the main transistor, driver IC and bypass capacitor. ekil 37'de gsterilen devre kontrol sinyalini tamak ve g iin switching frekansn kullanmaktadr. Aslnda ileyi olduka basittir. Ana switchin on-time' boyunca transformatrn sekonder tarafndaki pozitif voltaj rektife edilerek gate drive IC'si iin voltaj salar. G gate drive pulse'larndan retildii iin ilk bir ka pulse bias kapasitrn arj eder. Bundan dolay, bu uygulama iin seilmi olan IC'nin dk voltaj korumasnn olmas elzemdir. Devre diyagramnda gsterildii zere, DC restorasyon devresi (CC2 ve DC2), operasyon duty ratio'sundan bamsz olan srcye bias voltaj yaratmak iin kullanlmaldr. DC2 ayn zamanda srcnn inputlarn,trasnformatrn ikincil sargsnn nagatif resel voltajndan korumak iin de kullanlr. Bu devre iin trasnformatr tasarm diger gate trasnformatrlerinin tasarmlaryla temelde ayndr. G seviyesi driver IC'sinin g tketimi nedeni ile hafife artmtr ki bu Mosfet toplam gate yknn g kayb ile karlatrldnda olduka dk kalr. Trasnformatr yksek peak akm tar ancak bu akm baypass kapasitrn arj eder, Mosfetin input kapasitrn deil. Tm gate akm ana stansistr, src IC'si, ve bypass kapasitr arasnda lokal olarak sahiplenilmekte (tanmakta, bulundurulmaktadr.

Figure 38. Bir transformatrl g ve kontrol transmisyonu. Another similar solution to transfer power and control signal with the same transformer is shown in Figure 38. The difference between the two circuits in Figures 37 and 38 is the operating frequency of the transformer. This implementation utilizes a dedicated chip pair. The high frequency carrier signal (fCARRIER>>fDRV) is used to power transfer, while amplitude modulation transmits the control command. The basic blocks of the gate drive schematic in Figure 38 can be integrated into two integrated circuits allowing efficient utilization of circuit board area. Because of the high frequency operation, the transformer size can be reduced compared to traditional gate drive transformers. Another benefit of this solution is that the bias voltage of the floating driver can be established independently of the gate drive commands, thus the driver can react without the start- p delay discussed in the previous solution.

Ayn transformatr ile g ve kontrol sinyalini trasnfer eden baka bir zm ekil 38 de gsterilmitir. ekil 37 de gsterilen ve 38 de gsterilen devreler arasndaki fark, trasformatrlerin alma frekanslardr. Bu uyarlama , dedike edilmi (adanm) ip iftleri kullanr . Yksek frekans tayc sinyal (fCARRIER>>fDRV) g transfer etmek iin kullanlrken genlik modlasyonu kontrol sinyallerini tamak iin kullanlr. Figr38 deki temel blok devre kartn verimli kullanmak iin iki entgre devre kullanlarak tasarlanabilir. Yksek frekans operayonlar nedeniyle, transformatr boyutu genel gate drive transformatrleri ile karlatrldnda daha kk olabilir. Bu zmn bir baka avantaj ise dalgalanan (floating) srcnn bias voltaj gate drive komutlarndan bamsz olarak salanabilir ve bylece src daha nceki blmlerde bahsedilen p-gecikmesi olmadan cevap verir. ///////////// Double ended transformer coupled gate drives In high power half-bridge and full-bridge converters, the need arises to drive two or more MOSFETs usually controlled by a push-pull or also called double-ended PWM controller. A simplified schematic of such gate drive circuit is illustrated in Figure 39. In these applications a dual polarity symmetrical gate drive voltage is readily available. In the first clock cycle, OUTA is on, forcing a positive voltage across the primary winding of the gate drive transformer. In the next clock cycle, OUTB is on for the same amount of time (steady state operation) providing an opposite polarity voltage across the magnetizing inductance. Averaging the voltage across the primary for any two consecutive switching period results zero volts. Double ended transformer coupled gate drives Yksek gc (high power) haf-bridge ve full-bridge eviricilerde (converters) double-ended PWM denetleyici olarak adlandrlan push-pull'lar ile kontrol edilen 2 yada daha fazla Mosfet'e ihtiya doar. Bu ekilde bir devrenin basit bir emetii ekil 39 da gsterilmitir. Bu eit uygulamalarda dula polarite simetrik gate drive voltaj kullanma hazrdr. lk saat dngsnde (clock cycle) OUTA on durumundadr, ve gate drive trasnformatrn birincil sargs zerinden pozitif bir voltaj zorlar. Sonraki saat dngsnde OUTB on durumndadr ve ayn sre zaman iin manyetize indktans zerinde ters polariteli voltaj salar. Bu nedenle pepee iki zaman dngs iin avaraj voltaj '0' dr.

Figure 39. Push-pull type half-bridge gate drive Therefore, AC coupling is not needed in pushpull type gate drive circuits. Designers are often worried about any small amount of asymmetry that could be caused by component tolerances and offsets in the controller. These small deviations are easily compensated by the output impedance of the driver or by a small resistor in series with the primary winding of the transformer. The uneven duty cycle will cause a small DC current in the transformer which generates a balancing voltage across the equivalent resistance of the drive circuit. Assuming two different duty ratios, DA and DB for the PWM outputs, the DC current level of the magnetizing inductance is defined as: Bu nedenle, push-pull tarz gate drive devrelerde AC coupling'e ihtiya yoktur. Tasarmclar genellikle genellikle denetleyicilerdeki offsetlerden ve kullanlan devre bileenlerinden kaynakl oluabileke kk miktardaki asimetri sorunlar hakknda fazlasyla endielenmektedirler. Bu kk sapmalar output empedans yada transformatrn primer sargsna seri balanacak kk bir diren ile kolayca kompanse edilebilir. E olmayan grev dngleri (uneven duty cycle) transformatrde kk bir DC akmna neden olarak src devresinin e-direnci zerinde denge voltaj oluturur. ki farkl duty ratio oldugunu kabul ederek, PWM outputlar iin DA ve DB, manyetize ndktansn akm seviyesi aadaki gibi tanmlanabilir.

To demonstrate the triviality of this problem, lets assume that DA=0.33, DB=0.31 (6% relative duty ratio difference!), VDRV=12V, and REQV=5 which is the sum of one low side and one high side driver output impedance. The resulting DC current is 24mA and the excess power dissipation is only 3mW. The design of the gate drive transformer follows the same rules and procedures as already described in this chapter. The maximum voltsecond product is defined by VDRV and the switching period, because push-pull circuits are usually not duty ratio limited. Appropriate margin (~3:1) between worst case peak flux density and saturation flux density must be provided. A unique application of the push-pull type gate drive circuits is given in Figure 40 to control four power transistors in a phase shift modulated full bridge converter. Bu sorunun basitligini sizlere anlatmak iin aadaki deerlere sahip olduumuzu fazr edelim: DA=0.33, DB=0.31 (dudty ratiolarda %6 'lk bir fark), VDRV=12V, REQV=5 ki bu deer bir dk kenar ve bir yksek kenar src output empedansnn toplamdr. Oluan DC akm 24 mA'dir ve power kayb (dissipation) sadece 3mW'dr. Gate drive transformatrnn tasarmnda bu blmde anhsedilmi olan ayn kural ve prosedrler geerlidir. Pull-push devreleri genellikle dudy-ratio ile limitli olmadklar iin maksimum volt-saniye arpm switching peryotu ve VDRV ile tanmlanr. En kt peak flux yogunlugu ve saturation (doygunluk) flux yogunlugu arasnda yeterli marjin (~3:1) salanmaldr. Push-pull tarsz gate drive uygulamas ekil 40 'da gsterilmektedir. Devre faz-kaymal (phase-shift) module full-bridge konvertrda drt adet power transistrn kontrol etmektedir

Figure 40. Push-pull type half-bridge gate drive

Due to the phase shift modulation technique, this power stage uses four approximately 50% duty cycle gate drive signals. The two MOSFETs in each leg requires a complementary drive waveform which can be generated by the two output windings of the same gate drive transformer. Although, steady state duty ratio are always 0.5, changing the phase relationship between the two complementary pulse trains necessitates to have an asymmetry in the duty cycles. Therefore, during transient operation the PWM outputs are not producing the normal 50% duty cycle signals for the gate drive transformers. Accordingly, a safety margin must be built in the transformer to cover uneven duty ratios during transients. Another interesting fact to point out is that local turn-off circuits can be easily incorporated and are very often needed on the secondary side of the transformer. The gate drive transformer, more precisely the leakage inductance of the transformer exhibits a relatively high impedance for fast changing signals. The turn-off speed and dv/dt immunity of the power circuit can be severely impacted if the drivers pull down capability is not optimized for high speed switching applications. Faz kaymas (phase shift) modulasyon teknigi nedeniyle power katman drt adet yaklak %50 duty-cycle gate drive sinyali kullanr. Her bacaktaki iki Mosfet birbirini tamamlayan src dalga formu (waveform) gerektirir ki bunlar ayn gate drive transformatrnn output sarglar ile salanabilir. Steady-state (olagan alma) duty-ratio'su 0.5 oldugu halde, birbirini tamamlayan iki pulse katar (treni) arasndaki faz ilikisini deitirmek grev dnglerinde (duty-cycle) asimetriye neden olur. Bu sebeple gate drive transformatr iin, operasyon geileri srasnda PWM outputlar normal %50'lik grev sinyallerini retmez. Bundan dolay, gvenlik marjinleri transformatre dahil edilerek geiler srasnda e olmayan (uneven) dutyratio'lar cover edilebilsin. Dier bir ili nokta ise, lokal turn-off devresi transformatrn sekonder ksm ile kolayca birlikte alabilir ve buna ihtiya duyulur. Gate drive transformatrnn leakage (sznt) indktans deien sinyaller iin yksek empedans gsterir. Eer srcnn pull-down yetenegi yksek hzl uygulamalar iin optimize edilmemi ise g devresinin turn-off hz ve dv/dt baklg (immunity) bundan iddetti-ciddi biimde etkilenir.

FINAL COMMENTS, SUMMARY

Like all books, this article should be read from the beginning to the end to get the whole story. Every consideration described earlier regarding switching speeds, dv/dt immunity, bypassing rules etc. are equally applicable for all circuits including transformer coupled gate drives. As the topics build upon each other, only the unique and new properties of the particular circuit have been highlighted. This paper demonstrated asystematic approach to design high performance gate drive circuits for high speed switching applications. The procedure can be summarized by the following step-by-step checklist:

SON YORUMLAR ve ZET

Hikayenin tmn anlamak iin, dier tm kitaplar gibi, bu kitap da okunmaya en bandan balanmal. Bundan nce tanmlanm, anlatlm bilgiler switching hz, dv/dt baklg, bypasslama kurallar, transformer coupled gate drivelar da dahil olmak zere hepsi uygulanabilir bilgilerdir. Sadece dierinin zerine eklenen tek ve yeni zellikler highlight edilmitir. Bu metin, yksek hzl switching uygulamalar yksek performansl gate drive

devrelerinin tasarmna asimetrik bir yaklam geritmek zere yazlmtr. Tm prosegr aadaki kontrol listesini adm-adm takip ederek zetlenebilir. The gate drive design process begins AFTER the power stage is designed and the power components are selected. Collect all relevant operating parameters. Specifically the voltage and current stresses of the power MOSFET based on the application requirements, operating junction temperature, dv/dt and di/dt limits related to external circuits around the power MOSFET which are often determined by the different snubber or resonant circuitry in the power stage. Estimate all device parameters which describe the parasitic component values of the power semiconductor in the actual application circuit. Data sheet values are often listed for unrealistic test conditions at room temperature and they must be corrected accordingly. These parameters include the device capacitance, total gate charge, RDS(on), threshold voltage, Miller plateau voltage, internal gate mesh resistance, etc. Gate drive, power katman tasarlandktan ve power bileenleri seildikten sonra tasarlanmaya balanr. lgili tm alma parametrelerini bul ve toparla. zellikle power Mosfetin voltaj ve akm stres parametrelerini uygulamann ihtiyalar, mosfet yaknlarndaki harici devrelerin alma junction scaklg, dv/dt snrlar gz nnde bulundurulmaldr. ki bunlar genelde power evresinde sndrc (snubber) resonantrr. Gerek uygylama devresinde, parazitik etkilere neden olabilecek tm bileenlerin parametrelerini incele. Datasheetlerde verilen degerler genellikle gerekci olmayan test koullannda geerlidir. Deerler buna gre normalize edilmelidir. Test parametreleri device kapasitansn, toplam gate ykn RDS(on), eik voltajn, Miller platosu voltajn, dahili gate mesh direnvi vb. parametreleri iermektedir.

Prioritize the requirements: performance, printed circuit board size, cost target, etc. Then choose the appropriate gate drive circuit to match the power stage topology. Establish the bias voltage level which will be used to power the gate drive circuit and check for sufficient voltage to minimize the RDS(on of the MOSFET. Select a driver IC, gate-to-source resistor value, and the series gate resistance RGATE according to the targeted power-up dv/dt, and desired turn-on and turn-off switching speeds. Design (or select) the gate drive transformer if needed. Calculate the coupling capacitor values in case of AC coupling. Check start-up and transient operating conditions, especially in AC coupled gate drive circuits. nceliklei srala, performans, baskdevre boyutu, hedeflenen maliyet, vs. Sonrasnda power evresine uygun gate drive devresini se. Gate drive devresine g verecek bias voltaj seviyesini belirle ve Mosfet'in RDS(on) deerini minimize edecek voltaj kontrol et. IC srcsn, gate-tosource direnci degerini, gate rezistans RGATE degerini hedeflenen power-up ve dv/dt ye gre se, ihtiya duyulan turn-on ve turn-off switching hzlarn belirle. Eer ihtiya duyuluyorsa gate drive transformatrn se yada tasarla. AC coupling durumunda coupling kapasitr deerini hesapla. Balan ve gei evreleri alma koullarn kontrol et. zellikle AC coupled gate

drive devrelerinde. Evaluate the dv/dt and di/dt capabilities of the driver and compare it to the values determined by the power stage. Add one of the turn-off circuits if needed, and calculate its component values to meet dv/dt and di/dt requirements. Check the power dissipation of all components in the driver circuitry. Calculate the bypass capacitor values. Optimize the printed circuit board LAYOUT to minimize parasitic inductance. Always check the gate drive waveform on the final printed circuit board for excessive ringing at the gate-source terminals and at the output of the driver IC. Add protection or tune the resonant circuits by changing the gate drive resistor as needed. In a reliable design, these steps should be evaluated for worst case conditions as elevated temperatures, transient voltage and current stresses can significantly change the operation of the driver, consequently the switching performance of the power MOSFET. Of course, there are many more gate drive implementations which are not discussed in this paper. Hopefully, the principles and methods presented here can help the readers understanding and analyzing of other solutions. For those who are looking for quick answers in the rather complex field of high speed gate drive design, Appendix A through E offer typical, numerical examples of the different calculations. Appendix F provides a complete, step-by-ste gate drive design example for an active clamp forward converter with a ground referenced and a floating gate drive circuits. Srcnn dv/dt ve di/dt deerlerini deerlendir power katman tarafndan belirlenen deerlerle karlatr. htiya duyuluyorsa birtane turn-off devresi ekle ve bileenlerini kontrol ederek ihtiya duyulan dv/dt ve di/dt deerlerini karlayp karlamadna bak. Src devresindeki tm bileenlerin g tketimini kontrol et. Bypass kapasitr deerini hesapla Pazitik indktans minimize etmek iin baskdevre tasarmn optimize et. Baslm baskdevredenin gate-to-source terminallerinde ve IC'nin output terminallerinde herzaman gate drive dalga formunu (wavefrom) ve limitlerin geilme durumunu kontrol et. htiya duyuluyorsa, gate drive direncini deitirerek resonant devreye koruma ekle yada tune (ince ayar) et. Uygun bir tasarmda bu admlar en kot alma artlar iin (scaklk, gei voltaj ve akm stresleri, vs vs) kontrol edilir. Elbette bu yadzda bahsedilmeyen daha pek ok gate-drive uyarlamalar bulunmaktadr. Umarmki bu yazda bahsedilen bilgiler, okuyucunun dier zmleri de anlamasna ve analiz edebeilmesine yardmc olacaktr. Yksek hzl gate drive tasarmlarnn kompleks alanlarnda basit ve hzl zmlere ulamak isteyen okuyucular Ek A dan Ek F ye kadarki blmlerde nmerik hesaplamalar ve farkl hesaplar bulabilirler. Ek F'de ground refaransl ve dalgalanan (floating) gate drive devreleriyli aktif kenetli forward konvertrlar iin komple adm-adm gate drive tasarm rnekleri bulunmaktadr. Laszlo Balogh