ASIC DESIGN CENTER University of Applied Sciences Offenburg Electronic Design Automation

Design of Digital System in VHDL Entwurf digitaler Systeme mit VHDL

VHDL Users Manual Plus Rolling Dice Application

Rolling Dice with Melody Sound

Version 3.0 / 2008

Institute for Applied Research (IAF) Prof. Dr. Dirk Jansen M.Sc. Nidal Fawaz Tel: +49781205267 Tel: +49781205128 email: d.jansen@fh-offenburg.de email: fawaz@fh-offenburg.de

Table of Contents
Design of Digital System in VHDL ............................................................................... i 1 Introduction............................................................................................................. 6 2 VHDL Concept and Development......................................................................... 7 3 VHDL Language and Syntax............................................................................... 10
3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 General................................................................................................................................. 10 VHDL Structural Elements.................................................................................................. 11 Objects and Data types......................................................................................................... 16 Standard Logic 1164 ............................................................................................................ 19 Operators.............................................................................................................................. 22 Attributes.............................................................................................................................. 23 Concurrent Statement Description ....................................................................................... 24 Sequential Statement Description ........................................................................................ 27 Functions and Procedures .................................................................................................... 33 Finite State Machines........................................................................................................... 34 Packages and Libraries......................................................................................................... 38 Standard Operations............................................................................................................. 41 Sequential circuits:............................................................................................................... 43 State Machine: ..................................................................................................................... 46 Tristate-Structure: ................................................................................................................ 47 Delay models: ...................................................................................................................... 50 Structural modelling............................................................................................................. 51 Generate: .............................................................................................................................. 55 Testbench: ............................................................................................................................ 57

Synthesisable Behaviour Modules....................................................................... 41

4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8

5 6 7

Introduction to VHDL Laboratory..................................................................... 60 Rolling Dice with Melody Sound ......................................................................... 61 Laboratory Assignments ...................................................................................... 63
7.1 7.2 7.3 7.4 7.5 7.6 7.7 Lab Assignment 1 (Introductory Example) ......................................................................... 63 Lab Assignment 2 (Clock Generator) .................................................................................. 68 Lab Assignment 3 (Dice Generator) .................................................................................... 74 Lab Assignment 4 (Sound Generator) ................................................................................. 82 Lab Assignment 5 (Top Sheet Dice).................................................................................... 83 Lab Assignment 6 (Synthesis) ............................................................................................. 88 Lab Assignment 7 (Place & Route) ..................................................................................... 93

Appendix A: The VHDL language ............................................................................ 98

Language Elements............................................................................................................................ 98 Object................................................................................................................................................. 98 Structure........................................................................................................................................... 100 Behavioural Modelling .................................................................................................................... 103

Appendix B: Packages .............................................................................................. 110

IEEE.numeric_bit ............................................................................................................................ 110 IEEE.numeric_std............................................................................................................................ 114 IEEE.std_logic_1164 ....................................................................................................................... 118 VHDL standard library STANDARD ............................................................................................. 121 VHDL standard library TEXTIO..................................................................................................... 122

References .................................................................................................................. 124

List of Figures
Figure 2-1 Figure 2-2 Figure 2-3 Figure 3-1 Figure 3-2 Figure 3-3 Figure 3-4 Figure 3-5 Figure 3-6 Figure 3-7 Figure 3-8 Figure 3-9 Figure 3-10 Figure 3-11 Figure 3-12 Figure 3-13 Figure 3-14 Figure 3-15 Figure 3-16 Figure 3-17 Figure 3-18 Figure 3-19 Figure 3-20 Figure 3-21 Figure 3-22 Figure 3-23 Figure 3-24 Figure 3-25 Figure 3-26 Figure 3-27 Figure 3-28 Figure 3-29 Figure 3-30 Figure 3-31 Figure 3-32 Figure 3-33 Figure 3-34 Figure 3-35 Figure 6-1 Figure 6-2 Figure 7-1 Figure 7-2 Figure 7-3 Figure 7-4 Figure 7-5 Figure 7-6 Figure 7-7 Figure 7-8 Figure 7-9 Figure 7-10 Figure 7-11 Figure 7-12 Figure 7-13 Figure 7-14 Figure 7-15 Figure 7-16 Figure 7-17 Figure 7-18 Figure 7-19 Abstraction Levels in Design .......................................................................................................... 7 Development Process ...................................................................................................................... 8 Four phases Process: a-Behaviour, b-Simulation, c-Synthesis and d-Layout ................................. 9 VHDL Code of 8 bit Comparator.................................................................................................. 10 Entity of Half Adder...................................................................................................................... 11 Entity and Architecture Description.............................................................................................. 12 Full Adder Structure in VHDL....................................................................................................... 13 Register Process ............................................................................................................................ 15 Process Communication and Execution ........................................................................................ 15 Four bits Counter........................................................................................................................... 16 Constant Declaration ..................................................................................................................... 17 Time Type Object Declaration ...................................................................................................... 17 Concatenation of Signals............................................................................................................... 19 Resolved and Unresolved Signal Declaration ............................................................................... 20 Resolution Function ...................................................................................................................... 21 Counter Source File....................................................................................................................... 22 Shift Operators .............................................................................................................................. 23 Clock Process with Attribute Declaration ..................................................................................... 24 Concurrent Area for Statement Assignment.................................................................................. 24 Concurrent, Conditional and Selected Signal Assignments .......................................................... 26 General Form of Process Statement .............................................................................................. 27 Process with Sensitivity List ......................................................................................................... 28 Process without Sensitivity List .................................................................................................... 28 Multiplexer 4-into-1 ...................................................................................................................... 29 Four-bit Shifter.............................................................................................................................. 30 Signal and Variable Assignment in Processes............................................................................... 31 If-Then-Else Statement Description .............................................................................................. 31 Case Statement Description........................................................................................................... 32 Case Statement Example ............................................................................................................... 32 For-Loop Example ........................................................................................................................ 33 Maximum Value Function............................................................................................................. 34 Medvedev State Machine .............................................................................................................. 35 Moore State Machine .................................................................................................................... 36 Mealey State Machine ................................................................................................................... 37 Package Example .......................................................................................................................... 38 Package Body Example................................................................................................................. 39 Use Package Body Example ....................................................................................................... 39 Use Example............................................................................................................................... 40 Complete Dice Hardware .............................................................................................................. 62 Main Sub-Blocks of the Dice ........................................................................................................ 62 Counter Source Code .................................................................................................................... 65 Counter Do-File ............................................................................................................................ 66 Simulation Result of Counter ........................................................................................................ 67 Circuit Diagram of Clock generator .............................................................................................. 68 Structure of Clock Generator ........................................................................................................ 68 Circuit of 2 bits divider and its timing diagram............................................................................. 69 Timing Circuit of 4 bits clock divider ........................................................................................... 69 Simulation Result of 2 bits Clock Divider .................................................................................... 70 Simulation Result of 8 bits Clock Divider .................................................................................... 71 Simulation Result of 5 bits Clock Divider .................................................................................... 72 Simulation Result of Clock Generator .......................................................................................... 73 Basic Circuit Diagram of Dice Generator ..................................................................................... 74 Structural Diagram of Basic Dice Circuit...................................................................................... 74 Entity, Outer Structure and Truth Table of the Dice Decoder....................................................... 75 Structure and Output of NCO........................................................................................................ 75 Simulation Result of Decoder (1).................................................................................................. 77 Simulation Result of Decoder (2).................................................................................................. 78 Simulation Result of the Counter .................................................................................................. 79 Simulation Result of the NCO....................................................................................................... 80 ii

Figure 7-20 Figure 7-21 Figure 7-22 Figure 7-23 Figure 7-24 Figure 7-25 Figure 7-26 Figure 7-27 Figure 7-28 Figure 7-29 Figure 7-30 Figure 7-31 Figure 7-32 Figure 7-33 Figure 7-34 Figure 7-35 Figure 7-36 Figure 7-37 Figure 7-38 Figure 7-39

Simulation Result of Dice Generator ............................................................................................ 81 Sound Generator Block Diagram .................................................................................................. 82 Structural Model of Complete Dice Circuit .................................................................................. 84 Simulation Result of Sound Generator.......................................................................................... 85 Simulation Result of Top Sheet Dice (1) ...................................................................................... 86 Simulation Result of Top Sheet Dice (2) ...................................................................................... 87 Precision Setting of the CPLD ...................................................................................................... 90 Generated Precision Output Files.................................................................................................. 90 Top component RTL diagram (Example!) .................................................................................... 91 Sub-components of the top sheet (Example!)............................................................................... 92 Area report generated by Precision tool (Example!) .................................................................... 92 EDIF generated file (Example!) .................................................................................................... 93 Project Definition .......................................................................................................................... 94 UCF Definition.............................................................................................................................. 94 Part Selector .................................................................................................................................. 94 I/Os Definition .............................................................................................................................. 95 Fitting Definition........................................................................................................................... 96 iMPACT User Interface ................................................................................................................ 96 Xilinx Programmer........................................................................................................................ 97 Schematic design of the emulator board ....................................................................................... 97

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Preface
This script is intended to be a practical tutorial on VHDL. In general, this script is not a reference manual of VHDL; there are enough books in the market that describe the VHDL syntax. On the other side, this script deals with important syntax that is needed in programming, then starting with simulation, going through synthesis and ending up with emulation. The script is divided into two parts. Part one deals with the VHDL programming language and describes all the commands and rules of this language starting from chapter one up to chapter four. The second part covers chapters five to seven and it is about the assignments that must be performed during the laboratory. Appendix A and B are attached at the end of the script Chapter one is an introduction to VHDL, chapter two speaks about its concept and development. Chapter three describes VHDL language and syntax going through the important commands, explaining data types, concurrent and sequential statements, libraries, packages and others. Chapter four deals with the most common synthesisable modules in VHDL. Part two is the laboratory assignments where a rolling dice with melody sound must be programmed, simulated, synthesised and at the end emulated on FPGA. Appendix A and B are attached at the end of the script. Appendix A list out VHDL language elements, structure and behaviour modelling while Appendix B list out the IEEE Libraries for Numeric bit package, Standard Logic 1164 package and other important packages.

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VHDL Syntax

1 Introduction
VHDL stands for VHSIC Hardware Description Language; VHSIC is an acronym for Very High Speed Integrated Circuit. Its development was sponsored by the U.S Department of Defence and became IEEE Standard. VHDL was developed to address a number of recurrent problems in the development, exchange and documentation of digital hardware, in another word, VHDL is a programming language designed and optimised for describing behaviour of a digital system. The most evident application is probably the development of a formal model of the behaviour of a system. With formality, misunderstandings and misinterpretations can be avoided. Because of the self documenting character of VHDL, a VHDL model can even serve as system documentation to a certain degree. The advantage of hardware description languages is the possibility to execute the code. In principle, they are nothing else than a specialized programming language. Coding errors of the formal model or conceptual errors of the system can be found by running simulations. There, the response of the model on stimulation with different input values can be observed and analysed. During the development cycle, the description has to become more and more precise until it is actually possible to manufacture the product. The (automatic) transformation of a less detailed description into a more elaborated one is called synthesis. Existing synthesis tools are capable of mapping specific constructs of hardware description languages directly to the standard components of integrated circuits. This way, a formal model of the hardware system can be used from the early design studies to the final netlist. Software support is available for the necessary refinement steps.

2 VHDL Concept and Development

In every design, level of abstractions must be declared. Figure 2-1 shows the abstraction levels of IC design. It consists of four levels starting with behaviour, going through RTL, Logic and ending up to the lowest abstraction level which is layout.

High Abstraction

Behaviour

Register Transfer Logic (RTL)

Logic

Low Abstraction Layout

Figure 2-1

Abstraction Levels in Design

The development of VHDL models starts with their specification which covers functional aspects and timing behaviour as shown in figure 2-2. After writing down the codes, they will be simulated and checked for the right functionality. If the model shows the required behaviour, the codes will be synthesized. A synthesis tool chooses the appropriate gates and flip-flops from the specified ASIC library in order to reproduce the functional description. Once the model is available as ASIC library elements, a simulation on gate level can be done. Now gate and propagation delays have to be taken into consideration. Delay values can be included in each VHDL model description, i.e. clues about maximum clock frequency and critical paths after synthesis will be estimated. Once again it must be checked, whether the circuit fulfils the specified timing constraints. After the system is checked out and all specifications were met, layout will be generated using specific software.

Specification Functionality and Parameters

VHDL Model Codes and Programs

Simulation ModelSim or others

Synthesis Leonardo, Synopsis or others

Gate Netlist EDIF format (Electronic Design Interchange Format)

Simulation ModelSim or others

Layout IC Station or others

Figure 2-2

Development Process

Figure 2.3 describes the four phases that it undergoes during development cycle of ExclusiveOR gate. Figure (a) shows the behaviour description of the gate using VHDL syntax language, it consists of a Library declaration, entity and behaviour description. Figure (b) shows the simulation result of the codes that have been programmed in the previous stage, a test bench must be provided to simulate all the possible cases in order to insure no errors under all conditions. While Figure (c) presents if the system can really be transferred to the gate level and that all the codes have equivalent implementation gate level, another simulation must be done here after referencing the component technology library into simulation in order to check the maximum delay in the system, the result must not exceed one cycle clock. Figure (d) shows the last stage which is the layout. In the layout, transistor level will be declared and the overall system will reach to the lowest physical or hierarchy layer building it up from transistors, flip flops and others components. An application field of VHDL is in ASIC (Application Specific Integrated circuit) where synthesis is the tool of transformation from VHDL code to the gate-level netlist.

FPGA (Field Programmable Gate Array) is also a targeted application where configurable logic blocks (CLB) are used to process the codes on the hardware, more details will be described later.

Fig a Behavioural structure

Fig b Simulation Result

Fig c Synthesis Result

Fig d Layout Result

Figure 2-3

Four phases Process: a-Behaviour, b-Simulation, c-Synthesis and d-Layout

3 VHDL Language and Syntax

To get into VHDL directly, a very simple example will be introduced. This example will include the very general commands and syntax of VHDL programming.

3.1 General
Suppose a comparator must be implemented with two inputs of one byte input data each. The output of the comparator will be one bit indicating 1 if the two bytes are equal and 0 if not. This circuit will be described in VHDL language as shown in figure 3-1. A single concurrent assignment has described the operation of the comparator.

Figure 3-1

VHDL Code of 8 bit Comparator

The following points must be taken in consideration when writing VHDL code: 1. VHDL is case insensitive. 2. Using --, a comment can be written excluded out from the code execution. 3. Statements are terminated by ;. 4. Signal assignments are declared by <=. 5. Letters, numbers, underscores and others can be defined and used. Simple identifiers may contain letters, numbers and underscores. They are case insensitive; entity is the same as ENTITY as same as ENTity. During compilation there is no effect on the case sensitivity. Additional comments can be written to declare some points, these comments are important to remind you later what was the program about and if there is any important idea must be known. Using this symbol -- all the right side line will be ignored. Moving from one command to another, a semicolon must be terminated at the end of each command declaring the end of the statement. Assigning an output can be done by using this symbol <=, this will assign the right side the left side of the symbol as shown in figure 3-1 line 9.

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The important notice is the difference between = and <=, to show only equality this symbol = returned a Boolean value of 1 if the left side is equal in quantity to the right side, and 0 if both sides are not equal. While this <= is forcing the left side to have the value amount to the right side.

3.2 VHDL Structural Elements

Every VHDL design consists of at least an Entity and Architecture pair. Entity describes the interface of the system from the perspective point of its input and output, while Architecture describes the behaviour or the functionality of the digital system itself. Figure 3-1 line 2 and 7 shows the declaration of the two elements. Other elements are the packages and libraries. A package is a common storage area where type declarations, constants and other global units are stored in it. A library in VHDL is the logical name of a collection of compiled VHDL units (object code).

Entity
The interface between a module and its environment is described within the entity declaration which is initiated by the keyword Entity. One should think about the system as a black box and the entity will just declare the ports of this box with the corresponding total system as in figure 3-2.

Entity Input/output

Architecture Function

Figure 3-2

Entity of Half Adder

The word PORT declares the blocks of the system. In this example, 2 inputs of 1 bit each are declared, the IN and OUT keywords declare the type of flow of the signal. IN strict the flow of the signal into the system while OUT is outward direction from the system. Other types can be also declared as INOUT and BUFFER, they are used to declare bidirectional movements of signals such as in bus interface. If the signal is made up of 1 bit then a BIT declaration is sufficient, while if the signal is made up of more than 1 bit then a BIT_VECTOR is needed with the number of bits as shown in figure 3-1 line 3. After declaring the input and the output of the system, END keyword terminates the entity declaration as shown in line 5.

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Architecture
The Architecture is made up of statements; these statements are concurrently executed sequential statements could also be executed but under process declaration, more details about will be given later. Declaration of Architecture is needed and must be referred to the entity where the ports are declared. Figure 3-3 line 7 shows the Architecture declaration, the name of the architecture could be any arbitrary name behaviour, structure illustrating the abstraction level, it is followed by OF keyword and the entity name of the system. It is important to give the right entity name in order to refer all the signals to it. A BEGIN and END signals must terminate the beginning and the ending of the statements. Figure 3-3 shows the structure of Architecture. It is made up of statements that are executed in a parallel mode Concurrent at the same time independent of its location.

Entity Input/output

Architecture Function

BEGIN Concurrent 1 Concurrent 2 Process: 1. Sequential 1 2. Sequential 2 3. Sequential 3 4. Sequential 4 : : Concurrent 4 : END

Figure 3-3

Entity and Architecture Description

Component Declaration and Instantiation

Breaking the design into subdesigns will decrease the complexity of the work.

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Components are modules that can be gathered under a higher hierarchy, they are subprograms that will be mapped together to form a complete design. Component instantiations are statements that refer lower-level components creating unique copies or instances of those components.
x_in x y y_in x_in sum_out sum

Half Adder

y_in

Half Adder
carry_out

carry_out carry in

OR

carry

Figure 3-4

Full Adder Structure in VHDL

Suppose a full adder must be designed. This adder can be build up from 2 half adders with OR gate as shown in figure 3-4.

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These half adders will be added to the system as components, then mapped to the overall system. In the architecture, component half_adder is declared and its entity is mentioned in line 12. This component is similar to a socket that can be used several times to perform the same function in different positions. To communicate between different components, internal signals must be declared. These signals will connect the output of a component to another input component or opposite. In line 9, three signals are declared which are internal connections between different modules. After declaring the components, port mapping is required to show the instantiation of each of them. Lines 24, 30 and 33 show the instantiation port mapping of different components in the system. Each component will be given an instantiation name that differentiates between them. This naming helps to identify the ports of this component with respect to the other similar or non similar components. To connect the ports of the components, this symbol will be used => connecting the port signal of the component of the left side to the internal signals or outer signals on the right side as shown in lines 25,26,27 and 28. Also a comma , is needed to terminate between each mapping statement which is different from semicolon ; that terminates command or entity statements. Important point is that the left side must match the right side in type and quantity. If the left side is a bit vector of 3 bits then the right side must be also a signal defined as bit vector of 3 bits. An easier way is to list directly the connected signals in the right order as listed in the component entity, this is shown in lines 31 and 34. The full adder in this case will be a top sheet of structural netlist combining different components of specific goal each on a hierarchy to get full adder functionality.

Process
A process is used to describe the behaviour of a circuit over time. In general, the statements in architecture are executed concurrently; the need of a sequential behaviour has introduced a process. Figure 3-5 shows a typical clocked process that is used for 1-bit Register. The process has a name regproc as seen in line 9; it must start with BEGIN keyword and end with END PROCESS. An important thing is the sensitivity list. Sensitivity list is a list of signals that triggered the process giving it the command to start executing the statements. In line 9, the two signals reset and clk are in the sensitivity list. Any change in one of these two signals will activate the process function. The execution will be in a sequential form, this means if one of the signals changes then the first condition will check whether the reset is 0 or 1 even if clk signal changed. This is because the first statement has the highest priority of order. This condition will be checked every time the process is activated. In case if there was no change in reset then the process will step into the second statement and check if there is a trigger on the clock signal. If the condition met then the signal y will take the value of x. Processes are allowed to be used in architecture area, multiple of processes can be written in one architecture. All the processes will be concurrently executed if they have same trigger signal, the internal statements of each process is independent from other processes.
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x clk reset

y Register

Figure 3-5

Register Process

Architecture Process ----------------------

Architecture Process ----------------------

Architecture Process ----------------------

Figure 3-6

Process Communication and Execution

Another way to write a process is by using wait statements instead of sensitivity list. wait statements suspend the execution of the process until some condition has been met. The best example of such a process is a test bench, test benches will be described later. Figure 3-6 shows the relation between different processes in different architectures; all processes run in parallel mode but their internal statements run in sequential mode.

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3.3 Objects and Data types

Objects are language elements used to present and store data. Three basic types of objects are found: 1. Signals 2. Variables 3. Constants Each object has a specific data type and a unique set of possible values. For example, an object of type bit has only two possible values 0 or 1.

Signals
Signals are similar to wires on a schematic, and can be used to interconnect concurrent elements of the design. To declare a signal, a signal keyword must be written before the name of the signal, figure 3-4 line 9 shows the declaration of 3 signals, a signal type must be declared (bit, std_logic or others) without mentioning the direction of flow as in entity declaration. Signals can also be initialized to a specific value at the beginning of the declaration. They are useful for simulation, but in synthesis these values will be ignored due that the hardware may not power it up to a known state when the system is switched on.

Variables
Variables are objects used to store intermediate values between sequential VHDL statements. They are allowed only in processes, procedures and functions. They are local to those functions and they cannot be seen by other functions. Suppose a process has declared a variable as shown in figure 3-7 line 2, the variable has no specific direction of flow, only the type of the variable will be declared. To assign a value for a variable this symbol will be used := and not <=, this differentiate between signals and variables. Since the variables are internally recognised within its process, a signal of similar type object must be assigned to take the value of the variable, line 9 shows the assignment of the variable count_int to the signal count. In this case, the value of count_int can be seen outside the process. More details about variables and signals will be given later.

Figure 3-7

Four bits Counter

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Constants
Constants are objects that are assigned a value once at the beginning; the value doesnt change during execution and simulation. These constants are useful when there is a repetition need of constants in different places. These constants can be located in any declaration area in your design description. There are two types of declaration, global and local declaration. Global constants will be declared in packages while local constants can be declared within architecture, block, process or subprogram as shown in figure 3-8.

Figure 3-8

Constant Declaration

Time
Time is a special type as it consists of a numerical value and a physical unit. Normally it is used to delay the execution of statements for a certain amount of time especially in test benches and propagation delays as show in figure 3-9. In line 2, period was declared as a constant of value 100 ns, this was used in line 8 to refer to this amount of time. The constant period can be multiplied with an integer as in line 10 to show a delay of 300 ns. The resolution of time in VHDL simulators reaches to femto-seconds (fs): fs, ps, ns, us, ms, s, min and hr.

Figure 3-9

Time Type Object Declaration

Scalar Types
Scalar types represent single values where relational operations can be applied to them. They include numeric types (integer and real) and enumerated types (Boolean and Character). Table 3-1 shows these different types. The bit data type is the most fundamental representation of a wire in VHDL. The bit has only two possible values, either 1 or 0 which represent logical 1 or 0 in a digital system.

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The Boolean type has only two possible values, either True or False. It is simply the result of a logical test such as comparison statement or If statement.
Table 3-1 Data Types Declaration

Data Type Bit Boolean Integer Character Real Severity_level Time

Typical Values 1 or 0 True or False 0,1,2,-32,129 etc a, b, 0, 1, , @, etc. Floating point number NOTE, ERROR 100 ns

Comment Defined as enumerated type The result of comparison result Min. and Max. ranges: 2147483647 ISO 8859-1 Character set Min. and Max. ranges: 1.0E38 Enumerated type used in report A physical type

Integer type includes integer type values in a specified range. The minimum and maximum default ranges are 2147483647. This range can also be restricted with a range constraint or a new integer subtype:
(SUBTPYE byte_int integer RANGE 0 TO 255) or ( SIGNAL byte_int : integer RANGE 0 TO 255)

During synthesis, integer will be mapped to a number of wires. These wires could be modelled via bit vectors as bit_vector declaration. Real types are floating point types used to approximate real numbers. Mainly used for simulation purposes and are not accepted in synthesis tools. Character types are used to represent string data to display messages during simulation or to represent actual data values in design description.

Array Types
An array is a collection of one or more values of the same type. They are indexed by a number that falls into the declared range of the array using to or downto syntax. The direction of an arrange array has an impact on the index values for each element. The values are assigned according to their position within the array, not according to their index. Therefore it is highly recommended to use only one direction (usually 'downto' in hardware applications) throughout your designs: SIGNAL x : bit_vector (3 downto 0) SIGNAL y : bit_vector (3 downto 0) y(0) <= x(3); y(1) <= x(2); y(2) <= x(1); y(3) <= x(0). This command will assign x to y but the positions are reversed. For example if x=1010 then y=0101. A small different is there between assigning a bit and a bit_vector. Suppose x is one bit signal and y is 3 bits signal, the values will be assigned in this way:
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x <= 1; y <= 110 Also a signal can be assigned with Hex Format as shown in figure 3-10 line 7. The letter x precedes the data to identify the Hex format. Another method of declaration is called concatenation. Concatenation is a function with operator & that groups together the elements on its sides which have to be of the same data type. Line 10 is an example of this operation, signal B_BUS is declared as A_BUS plus other 4 bits to form all together 8 bits. There is a difference between typing & and AND, the first is for concatenation process while the second is used as an AND operator between signals.

Figure 3-10

Concatenation of Signals

Enumeration Types
New types can be declared from the programmer, these new scalar types are called enumerated types which facilitate the readability of the system. These types enhanced the readability of state machines and they are dependable on the two signals current state and next state. For example, if a state machine contains the following states RESET, START, EXECUTE_1, EXECUTE_2, and END, these names will make the readability of the system easier and during simulation the programmer will know on which state the system is running. These names can be mapped to bit patters by synthesis tools. More details about state types will be covered later in state machine chapter.

3.4 Standard Logic 1164

IEEE Standard Logic 1164 was released in the late 1980s. It helps to overcome the limitation of VHDL and its various commercial implementations. The limitations of the logic values 1 and 0 led to create multiple values that shows different behaviour of a wire as (highimpedance, unknown,). For that, IEEE standard logic data type was found with its nine values as shown in table 3-2. These nine values model the behaviour of a digital circuit during simulation and represent the possible states of a signal. The most important reason to use standard logic data types is portability. It gives you a standard and a portable style simulation or changing simulation environment in interface with other components.

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To use the IEEE 1164 standard logic types, at least two statements must be added in the source file. These statements are: LIBRARY IEEE and USE ieee.std_logic_1164.ALL
Table 3-2 Standard Logic Values

Value U X 0 1 Z W L H -

Description Uninitialised Unknown Logic 0 (driven) Logic 1 (driven) High Impedance Weak 1 Logic 0 (read) Logic 1 (read) Dont care

This declaration is shown in figure 3-13 at lines 1 and 2. In every design unit, these two statements must be added at the beginning in order to make the contents of the standard library visible to each design unit.

Resolved and Unresolved Types

A signal requires resolution whenever it is simultaneously driven with more than one value. By default, data types are unresolved, resulting in errors being generated when there are multiple values being driven onto signals of those types. Oppositely, if the signal is declared as a resolved one then multiple values are allowed to be driven onto it simultaneously with a known result. Figure 3-11 shows the declaration of these two types for different signals. As there is bit_vector declaration there is also std_logic_vector which is found in IEEE 1164 package for array declaration.

Figure 3-11

Resolved and Unresolved Signal Declaration

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Z <= x;

&
y

Z <= x and y;

x
?

y
Resolution Function is needed ! Figure 3-12

Z <= x; Z <= y;

Resolution Function

Figure 3-12 shows three different statements, the first signal is a direct assignment of the input x to the output z, the second is an assignment of the AND operation between x and y to the output. The third assignment is a declaration for an output driven by two inputs separately; such declaration will lead to a conflict if the output signal is not declared as a resolved one. In case the output is declared as a resolved signal then the value of the output will be evaluated according to table 3-3. If the output depends on more than 2 inputs then the driving values are collected in an array and handed to the resolution function which will evaluate the final output value. The advantage of resolved signals is detection of errors of multiple drivers during simulation, while unresolved signals are commonly used in industry standard as a gate level netlist and it is always required in tri-state busses declaration.
Table 3-3 Output Resolved Signals

U U X 0 1 Z W L H U U U U U U U U U

X U X X X X X X X X

0 U X 0 X 0 0 0 0 X

1 U X X 1 1 1 1 1 X
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Z U X 0 1 Z W L H X

W U X 0 1 W W W W X

L U X 0 1 L W L W X

H U X 0 1 H W W H X

U X X X X X X X X

Numeric Standard Package

The numeric standard package defines the numeric types signed and unsigned, also their corresponding arithmetic operations and functions based on std_logic resolved data type. The need to describe operations such as counters that are not directly supported to the standard logic data types led to the formation of type conversions, these conversion functions facilitate to work in different format as unsigned signals and then convert them back to standard logics.

Figure 3-13

Counter Source File

Figure 3-13 lines 2, 3 and 4 show the declaration of IEEE library and the usage of std_logic_1164 and numeric_std packages. These two packages are found in IEEE library. Line 7 declares signal counter as a standard logic vector of 8 bits in the entity structure. In line 18, the operation + is needed to perform the counting process, this operation is declared in numeric package. In line 20, a conversion type is needed to convert from unsigned type to standard logic type. The conversion operation is done by the command std_logic_vector(). A complete list of type conversions is provided in the appendix.

3.5 Operators
VHDL is a rich language that includes many different operators. These different types include logical operators, relational operators, shift operators and other arithmetic operators.

Logical Operators
The logical operators are and, or, nand, nor, xor and xnor. These operators are used to describe Boolean logic operations or perform bit-wise operations. The highest priority among the logical operations is not operator, the rest have equal priorities. Brackets must be used to define the order of evaluation. For example:

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z <= not (a and (b or c)) xnor d; In this case, b and c will be processed first, then with a, then negated and at last xnor with d.

Relational Operators
Relational operators are used to test the relative values of two scalar types. The result of a relational operation is always a Boolean true or false value. These operators are =, /=, <, <=, > and >=.

Shift Operators
Shift operators provide bit-wise shift and rotate operations for arrays of type bit or Boolean. There are three types of shifting: 1. Shift Left/Right Logical (sll or srl) 2. Shift Left/Right Arithmetic (sla or sra) 3. Rotate Left/Right Logical (rll or rrl)
srl sll

sra

sla

rrl
Figure 3-14 Shift Operators

rll

The difference between these 3 types is shown in figure 3-14.

Arithmetic Operators
These include addition, subtraction, multiplication, division and other arithmetic operators, such as +, -, , /, mod and other operators, the length of the operands must always be adjusted to the same size, if not then concatenation process can be applied to readjust the length of the operands. These operators can be applied on integer, real and physical types. More details are found in appendix.

3.6 Attributes
Attributes are elements that allow extracting additional information about an object such as a signal, variable or type. They also allow assigning additional information to objects in design description. There are two types of attributes: predefined and custom attributes.

Predefined Attributes
Predefined attributes are always applied to a prefix such as a signal, variable name or a type name.
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In figure 3-15 line 4, clock signal has 2 attributes: LAST_VALUE and EVENT. The first attribute reflects the last value of the clock before its current value while the second attribute triggers the process at the moment when jump occurs.

Figure 3-15

Clock Process with Attribute Declaration

Others attributes are: Left, Right, High, Low, Length and etc

Custom Attributes
Custom attributes are those which are not defined in IEEE specifications, they are defined by synthesis or simulation tool vendor for the own usage. For example, the attribute enum_encoding is declared by synthesis tool vendors (Synopsis, LeonardoSpectrum) to allow binary coding to be attached to objects of enumerated types. It can be declared as follows: ATTRIBUTE enum_encoding: string; It could be directly written in VHDL code, the synthesis tool will automatically search in the vendor package if this attribute is found, if not then the synthesis tool will automatically ignore it.

3.7 Concurrent Statement Description

ENTITY PORT ( ); END; ARCHITECTURE BEGIN Concurrent 1 Concurrent 2 Concurrent 3: Process Sequential 1 Sequential 2 Sequential 3 Sequential 4 : : Concurrent 4 : END; END architecture

Concurrent Area

Figure 3-16

Concurrent Area for Statement Assignment

VHDL is a concurrent language, means that all statements are parallel executed. These statements are declared in the architecture of the system, detailed between the BEGIN and
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END statements. Figure 3-16 shows the concurrent area where statements can be declared. All these statements are parallel executed with same priority, means that if statement 2 was exchanged by statement 4 then the result is the same as the previous one. The process statements will also be in parallel executed independent of its internal sequential mode. This is to show that the behaviour of execution in VHDL is concurrent, but under special statements, as processes, the execution of these statements internally will have a time sequential performance.

Concurrent Signal Assignments

Concurrent signal assignments are the most concurrent statements written in VHDL, they specify the logical relationship between different signals in a digital system. Concurrent assignments are normally used for two purposes: 1. Describe combinational logic. 2. Describe connections between lower-level components. Figure 3-17 line 14 shows a concurrent assignment, the output signal x is assigned in a combinational logic form of a, b, c and d signals. Important thing here is to take care when assigning input signals to output signals, the port direction or mode must be taken in consideration, only IN signals can be assigned to OUT signals from the entity list. Local signals declared in architecture can be used in both situation as well as bidirectional mode signals INOUT can be used too.

Conditional Signal Assignments

Conditional signal assignments allow describing a sequence of related conditions and corresponding signal assignments. Figure 3-17 line 17 shows a conditional assignment for signal y. This is an example of a multiplexer with sel signal as a selector between the four input signals. In such declaration, a priority is preserved. During execution, the system will check the first condition if it is satisfied, if yes then a will be assigned to y, if not then the second condition will be checked, and so on till it reaches to the last condition and it is a direct assignment without any condition. This means that if sel signal was not 00, 01, or 10 then it will directly assign d to y. Logically, the last condition must be with sel condition of 11, but the point is that sel signal is not just made up of 4 options 00, 01, 10 or 11, there are also the other values of the nine terms which could be 0X, 1U, 1- or ZZ that are declared in std_logic_1164 package. These values must be taken in consideration, for that we use a direct assignment at line 20 to describe the other possible combination values. When writing conditional statements, no semicolon ; symbol is terminated at the end of the line after ELSE word. This is to show that all the four lines (17 to 20) are used to declare at the end one value for the output signal y depending on the value of sel.

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Figure 3-17

Concurrent, Conditional and Selected Signal Assignments

Selected Signal Assignment

The selected signal assignment is almost the same as the conditional signal; the only thing differs is that it has no priority conditions. The execution will not follow a sequential order of priority to check if the condition is satisfied, the system will fall directly to the satisfied condition as shown in figure 3-17 line 23, z signal will have directly the value of the input which satisfies the condition of sel value. In case the value didnt match then the assignment will fall directly to d. It is always important to end selected signal assignment with WHEN OTHERS clause as in line 26 to be sure that the system will not fall in unknown state due to the lack that not all the values are listed in the selected conditional assignment. The same with conditional signal, it ends up with unconditional assignment ELSE as in line 19 in case all the conditional values didnt meet the requested value of sel. Uncompleted list of conditions will generate latches by synthesis in the system. An important notice distinguishes between conditional and selected signal is that conditional signal assignments can result in unwanted additional logic being generated from synthesis while selected signal assignment will never result in additional priority logic being generated. This is due to that conditional assignments are dependable on priority list of execution while selected assignments are undependable and lead to less amount of logic gates.

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3.8 Sequential Statement Description

Sequential Statements allow describing circuits as a sequence of related events, this is the main difference between concurrent and sequential description. It allows you to specify at a high level what the system is supposed to do over the time. Sequential statements are commonly found in processes, functions and procedures.

The Process Statement

A process statement is the primary way to enter sequential statements. It includes a sensitivity list, local declarations, and one or more sequential statements. It describes the sequential execution of statements that are dependent on one or more events having occurred. Figure 3-18 shows the general form of a process statement.
process_ name: PROCESS (sensitivity_list) declarations BEGIN Sequential 1 Sequential 2 Sequential 3 Sequential 4 : : END PROCESS;

Figure 3-18

General Form of Process Statement

The process name (process_name) appearing before the process word keyword is not obligatory, but it is useful to be named in order to be distinguished from other processes during execution. After the process name, the word PROCESS must be written to declare the type of the following statements. After the process word, a sensitivity list will be declared, more details in the second parts. In the second line, variables can be declared for local use, these variables will not be seen outside the process by other process or other statements. It is just limited for internal use of the process. If this variable is the target to be evaluated then it must be assigned to a signal holding its value to become apparent outside the process area. Before writing down the sequential statements, BEGIN keyword is declared as well as at the end of the statements END PROCESS is also declared showing the end of the process statements. Two types of processes exist, process with sensitivity list and process without sensitivity list.

Process with Sensitivity List

The sensitivity list (sensitivity_list) that comes after process word is important to trigger the process execution. The system will run after a change occurred in the sensitivity list signals, these signals are the ones found in the process statements as an input signals. It is important to list all the input signals in the sensitivity list that are read in the process statements to trigger the execution.

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Figure 3-19

Process with Sensitivity List

Figure 3-19 shows the two signals listed in the sensitivity list, clk and reset. These two signals are used to trigger the process and lead to execute the sequential statements. If any one of the signal changes then execution is done. In lines 3 and 5, the two signals are read and according to their values the system will behave. Regarding to which signal has changed, the system will always start executing from the first statement till the end, even if one or both signals have changed.

Process without Sensitivity List

A process without a sensitivity list execute continuously, suspending only when a WAIT statement is encountered. The system will execute first time from the BEGIN then suspend when it arrives to WAIT statement and then waits till the conditions is satisfied. Once the condition is satisfied then the system will continue execution till it falls once again on a WAIT statement. If all wait statements are satisfied (it could be also only one WAIT statement in process) then the system will restart once again directly from BEGIN and suspend on the WAIT statements.

Figure 3-20

Process without Sensitivity List

Figure 3-20 lines 3 and 5 show the declaration of two wait statements, the process starts directly after BEGIN word to execute and suspends on the WAIT statement, once the condition is satisfied then it completes execution and suspends on the second WAIT statement. The overall process will deliver half the frequency of the clock. Such process is used to produce lower frequencies or sub-frequencies from the original clock.

Processes for Combinational Logic

Processes can also be used to describe combinational logic circuits when all inputs are listed in the sensitivity list and there are no undefined input conditions. The following example shows a simple combinational logic function for a multiplexer using a process statement.

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Figure 3-21

Multiplexer 4-into-1

In line 9, the five input signals are declared (sel, a, b, c and d), this means that if any signal from the input is changed then it will have directly an effect and the system will execute and evaluate the new data. The point is that there is no memory needed, i.e. neither flip flops nor latches are found in such a description. If there is a change in one of the input signals and the process execute then this change must influence one of the statements in the process. If not then it will be a register logic behaviour which will be declared in the next section. So to dictate whether the signal assignment logic is been generated or not these two rules must be confirmed: 1. The sensitivity list of the process includes all the signals that are being read within the process, for this example are (sel, a, b, c and d). 2. Assignment statements written for the process outputs (y in this example) cover all the possible combinations of the process inputs (sel, a, b, c and d in this example).

Processes for Registered Logic

The most common use of VHDL processes is to describe the behaviour of the circuits that have memory and must save their state over time. To obtain such behaviour, the following rules must be taken in consideration. 1. The sensitivity list of the process doesnt include all the signals that are being read with the process. 2. Incompletely use of IF-THEN-ELSE statements lead to hold values some signals under certain conditions. The following example in figure 3-22 will illustrate more the registered logic process. A four bit shifter is shown in the above figure, the incomplete IF-THEN statement leads signal q_reg to hold its value when the two conditions are false, means reset is low and clk is not on event. The output signal in this case will keep its previous value till one of the conditions is satisfied.
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Figure 3-22

Four-bit Shifter

Processes for State Machines

State machines are a common form of a sequential logic circuits that are used for generating or detecting sequences of events. More details about state machines will be covered later.

Signal and Variable Assignments

One important aspect of VHDL is the relationship between sequential statements and the scheduling of signal and variable assignments. Variables are assigned new values immediately while signal assignment are scheduled and do not occur until the current process has been suspended. Deciding whether to use signals or variables requires careful consideration; the following two examples will illustrate the difference between using each type. In figure (a) lines 7 and 8, the output q_1 is used in the second statement as an input signal, since it is declared as a signal then the evaluated value from the first statement in line 7 will not appear directly in the second statement. To make it easier, suppose the value of q_1 was high 1 due to the last execution, a new trigger from clk signal occurred which will lead to run the process, on line 7, suppose the new value of q_1 is low 0, now the second statement has to evaluate the value q_2 which is dependable on value of q_1, the important point is that the value here of q_1 which will be evaluated is 1 and not 0 because q_1 is defined as signal and the signal will not have its new value unless the process is suspended. In the next execution, the value of q_1 will be 0 although the execution at that moment could lead a value different than this value. Such behaviour will describe a chain of registers. In figure (b), two variables are declared within the process, these variables will have immediate evaluation. In this case the value of temp_2 will be evaluated with respect to the
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immediate value of temp_1 and not as in the previous example. This is clear in the difference of connections of both circuits. In reality, both types are used to describe complex synchronous circuits.

clk clk a a b q_1 b

temp_1

q_1

temp_2

q_2

q_2 c Fig a

Fig b Signal and Variable Assignment in Processes

Figure 3-23

If-Then-Else Statements
The If-Then-Else statement is the most common form of control statement in VHDL. It has the following structure as shown in figure 3-24.
IF first_condition THEN Statement(s) ELSIF second _condition THEN Statement(s) ELSE Statements(s) END If;

Figure 3-24

If-Then-Else Statement Description

The evaluations of the conditions are Boolean type. The first If condition has the top priority, if this condition is fulfilled then the corresponding statements will be carried out and the rest of the If statements will be skipped. And Else statement is an optional path when all the conditions failed to be satisfied.

Case Statements
Case statements are a type of control statement that can be used as alternatives to If-ThenElse statements. The following figure 3-25 shows the case statement description.
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CASE control_expression IS WHEN test_expression_1 => Statements WHEN test_expression_1 => Statements WHEN OTHERS => Statements END CASE

Figure 3-25

Case Statement Description

The control signal must be declared between CASE and IS, according to the value of this signal, the system will jump directly to the value listed after WHEN clause. This is the main difference between If-Then-Else statement and Case statement.

Figure 3-26

Case Statement Example

Another important thing is that all the cases must be covered, to insure the rest cases, OTHER clause can be used to cover them. If multiple values have same condition then or operation can be used. Figure 3-26 shows an example of a case statement. The input integers are limited by a RANGE clause to avoid declaring by default all the range of integer (2147483647), using this option, it will decrease in synthesis the number of gates and memory of this declaration. Using x as the control expression, the cases must cover all the range from 0 to 15. Lines 11, 13 and 15 cover some of the ranges and the rest is declared in line 17. | OR operation is been used when similar values have same conditions. Line 15 used TO clause to cover a sub range sequence from one to five.

Loops Assignment
The for loop is a sequential statement that allows specifying a fixed number of iterations in a behavioural design description. It includes an automatic declaration for the index i. For the for loop to be synthesized, the range of the loop variable must not depend on signal or variable values.
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The following example shows how a for-loop statement can be implemented.

Figure 3-27

For-Loop Example

Line 12 declares the for-loop statement, every time x changes then it will execute the process, then the for-loop will be performed, if the condition is satisfied in line 13 then the assignment will be performed.

3.9 Functions and Procedures

Functions and procedures are collectively known as subprograms, they are directly analogous to functions and procedures in a high level software programming language such as C or Pascal. 1. A procedure is a subprogram that has an argument consisting of inputs and outputs with no return value. 2. A function is a subprogram that has only inputs in its argument list with a return value. Both types can be either defined locally within architecture or they can be placed in a package and used globally throughout the design description or project.

Functions
A function is a subprogram that accepts zero or more input arguments and returns a single output value. The returned value will have the same type associated to it. The arguments to a function are all inputs to the function as seen in figure 3-28 line 1, the two integers value_1 and value_2 are used as an input to the function and return back the integer result to the system.

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Figure 3-28

Maximum Value Function

Procedures
Procedures differ from functions in that they do not have a return value, and their arguments may include both inputs and outputs to the subprogram. They are used as independent statements, either within the concurrent area of an architecture or within the sequential statement area of a process or subprogram.

3.10 Finite State Machines

State machines are common form of sequential logic circuits that are used for generating or detecting sequences of events. Different types of finite state machines exist, their graphical representation and ways to model them with VHDL will be shown. In general, every finite state machine can be described either by one or two different processes. The actual states of a state machine should generally be described by descriptive names. This can be achieved by use of an enumeration type whose values are these names. Later in the synthesis process, these names have to be mapped to a binary representation. This step is known as state encoding. Different versions exist for state machines to be described; three types can be distinguished in this area: 1. Medvedev 2. Moore 3. Mealy

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Medvedev
The difference between the three types of state machines (Medevedev, Moore and Mealy machines) is the way the output is generated. In the Medvedev machine the value of the output is identical with the state vector of the finite state machine. That means, the logic for the output consists only of wires; namely the connection from the state vector registers to the output ports. In Medvedev type, the output vector y resembles the state vector s. Figure 3-29 shows a typical state machine of Medvedev type, it can be programmed by two processes, registered process and combinational process.

Y X

Next State
Next State Logic

State Register

State

The output vector resembles the state vector Y=S

ARCHITECTURE rtl OF medvedev IS BEGIN reg_process : PROCESS (clk,reset) BEGIN --- State Registers Inference END PROCESS reg_process; combinational_process : PROCESS (x,state) BEGIN --- Next State Logic END PROCESS combinational_process; --- Assigning Output by concurrent statements Y <= S ; END rtl;

Figure 3-29

Medvedev State Machine

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Moore
In Moore type, the value of the output vector is a function of the current state. For that, additional logic block is needed and it is located after the storing element. This block holds the hardware which is needed to calculate the output values out of the current state. To get this output, a third process is needed to implement that and the only signal on the sensitivity list will be state. Figure 3-30 shows the description of this type state machine.

Next State
Next State Logic

State Register

State
Output Logic Y

The output vector is a function of the state vector Y=f (S)

ARCHITECTURE rtl OF moore IS BEGIN reg_process : PROCESS (clk,reset) BEGIN --- State Registers Inference END PROCESS reg_process; combinational_process : PROCESS (x,state) BEGIN --- Next State Logic END PROCESS combinational_process; --- Assigning Output by concurrent statements output_process : PROCESS (state) BEGIN --- Output Logic END PROCESS output ; END rtl;

Figure 3-30

Moore State Machine

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Mealy
In Mealy type, the value of the ouput vector is a function of the current values of the state vector and of the input vector. This is shown in figure 3-31 by the line drawn in the block diagram from the input vector to the logic block calculating the output vector. In this case the input vector is listed in the senisitivity list of the corresponding process with the state signal.

Next State
Next State Logic

State Register

State
Output Logic

The output vector is a function of the state vector and the input vector Y=f (X,S)

ARCHITECTURE rtl OF mealey IS BEGIN reg_process : PROCESS (clk,reset) BEGIN --- State Registers Inference END PROCESS reg_process; combinational_process : PROCESS (x,state) BEGIN --- Next State Logic END PROCESS combinational_process; --- Assigning Output by concurrent statements output_process : PROCESS (state,X) BEGIN --- Output Logic END PROCESS output ; END rtl;

Figure 3-31

Mealey State Machine

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3.11 Packages and Libraries

Packages
Data types, constants and subprograms can be declared inside entity declarations and inside architecture bodies. To make a set of type, constant and subprogram declarations visible to a number of design entities (entity declarations and their associated architecture bodies), it must be declared before the entities. The general form of a package declaration is given as:
PACKAGE identifier IS Declarations END identifier;

Both the declaration and the closing identifier are optional; however, an empty package declaration does not serve any apparent design purpose. The following declarations may occur in the declarations portion of a package declarations: 1. Basic declaration 2. Signal declaration 3. Attributes declaration 4. Attributes specification 5. Disconnection specification 6. Components declaration The following example illustrates a package declaration.
PACKAGE logic is TYPE three_level_logic IS ( '0', '1', 'Z'); CONSTANT Unknown_value : Three_level_logic := '0'; FUNCTION Invert(Input :Three_level_logic) RETURN Three_level_logic; END logic; Figure 3-32 Package Example

The general form of a package body is:

PACKAGE BODY indentifier IS Declarations END identifier;

The package body always has the same name as its corresponding package declaration preceded by the reserved words package body. Declaration that may occur in a package body includes: 1. Basic declaration 2. Subprogram body As with the package declaration, the package body may be empty, and its closing identifier is optional. Note that a package body contains the subprogram bodies whose corresponding

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subprogram declarations occur in the package declaration. Figure 3-33 is an example of a body for package logic Package bodies contains subprogram bodies and declarations that are not intended to be used by other VHDL units. Thus, package declarations contain the public, visible declarations while package bodies contain the private, invisible declarations.

PACKAGE BODY logic IS FUNCTION Invert (input : Three_level_logic) RETURN Three_level_logic IS BEGIN CASE Input IS WHEN 0 => RETURN 1; WHEN 1 => RETURN 0; WHEN Z => RETURN Z; END CASE; END Invert; END logic; Figure 3-33 Package Body Example

Items declared inside a package declaration are not automatically visible to another VHDL units. A use clause proceedings a units will make items declared in a package declarations visible in the unit.
USE Logic.Three_level_logic, Logic.Invert; ENTITY Inverter IS PORT ( x : IN Three_level_logic ; Y : OUT Three_level_logic); END Inverter; ARCHITECTURE Invert _body OF Inverter IS BEGIN PROCESS BEGIN y <= Invert (x) AFTER 10 ns; WAIT ON x; END PROCESS; END Inverter_body; Figure 3-34 Use Package Body Example

A use clause may, as in the immediately preceding example, name specific items declared in a package. However, an alternate form of the use clause, constructed with the reserved word all, makes all i terms declared in a package declarations visible. The following use clause makes all declarations in package Logic visible to the entity declarations.

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USE Logic.ALL; ENTITY Invert IS PORT ( x : IN Three_level_logic; y : OUT Three_level_logic); END Inverter; --The architecture body inherits the visibility of its entity declaration ARCHITECTURE Inverter_body OF Inverter IS BEGIN PROCESS BEGIN y<=Invert(x) AFTER 10 ns; WAIT ON x; END PROCESS; END Inverter_body; Figure 3-35 Use Example

Libraries
Packages may be thought of as libraries of subprograms. Libraries may in general contain design entities . We might have separate libraries for TTL, CMOS, ECL and other technologies. We could then simulate the same device, implemented in different technologies, simply by changing the references in the library statement to the appropriate library. (This assumes, of course, that component names, port names, etc., are the same, although the architectures, generic values, etc., will differ.) VHDL supports the reuse of code through the use of libraries. There are two declarative statements associated with libraries: the library and use statements. LIBRARY STD, work; USE STD.STANDARD.ALL; This context clause contains two kinds of statements, which is typical. The library statement names the library we wish to use. The use statement selects the elements within that library that we wish to make visible to the design unit under compilation. It may be useful to use multiple libraries with identically named components, so VHDL insists that, by defaults, we specify precisely which elements in each library we wish to use, each and every time we use them, unless the default is specified. The default all is often used to reduce the tedium of specifying precisely which elements from the library are to be used. Without the use statement, statements of the form: SIGNAL sig: STD.STANDARD.BIT; Would have to be used whenever type BIT, from package STANDARD of library name STD was used. The use statement can therefore save a tremendous amount of typing, along with improving readability. In VHDL terminology, BIT would be the suffix and STD. STANDARD the prefix in the name of the type. It is the suffix that becomes directly visible. It is of course, possible to use a number of libraries at a time. Such library are called resource libraries in the VHDL LRM. Library STD contains the packages STANDARD and TEXTIO. Library work denotes the current working library, that is, the VHDL code currently being compiled. Although the LRM 11.2 recommends that STD contain only those library units defined in the LRM, compiler vendors appear to ignore that admonition.
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4 Synthesisable Behaviour Modules

The target of writing a VHDL program is to be implemented at the end on a hardware circuit. The important thing is that the program must be synthesisable. Unfortunately not all the programs and behaviours are synthesisable, this is depending on the synthesis tools from the vendor company. A general operations have being selected that are synthesisable and can be implemented on a hardware.

4.1 Standard Operations

LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; ENTITY nand2 IS PORT(a,b: IN std_ulogic_vector (0 to 7); y: OUT std_ulogic_vector(0 to 7)); END ENTITY;

All Vector operation

ARCHITECTURE one OF nand2 IS BEGIN Y<= a NAND b; END one;

Individual bits treating separately in loop:

ARCHITECTURE two OF nand2 IS BEGIN PROCESS(a,b) BEGIN FOR i IN a ' RANGE LOOP y( i ) <= a( i ) NAND b( i ); END LOOP; END PROCESS; END two;

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As condition:
ARCHITECTURE three OF nand2 IS BEGIN y(0) <= '0' WHEN a(0) = '1' AND b(0) ='1' ELSE ' 1'; ... y(7) <= '0' WHEN a(7) = '1' AND b(7) ='1' ELSE ' 1'; END three;

As Truth table:
ARCHITECTURE four OF nand2 IS BEGIN PROCESS(a,b) BEGIN FOR i IN a ' RANGE LOOP CASE a( i ) & b( i ) IS WHEN 11 => y( i ) <= ' 0'; WHEN OTHERS => y( i ) <= '1'; END CASE; END LOOP; END PROCESS; END four;

Branches (multiplexer structures):

ENTITY if_and _case IS PORT ( i: IN integer RANGE 0 TO 9; a,b,c: IN std_ulogic_vector (7 DOWNTO 0); z: OUT std_ulogic_vector (7 DOWNTO 0) ); END if_and _case;

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With IF:
ARCHITECTURE if_behave OF if_and_case IS BEGIN p1: PROCESS IF( i = 3 ) THEN z <= a; ELSIF ( i < 3 ) THEN z <= b; ELSE z <= c; END IF; END PROCESS p1; END if_behave;

With CASE:
ARCHITECTURE case_behave OF if_and_case IS BEGIN p1: PROCESS ( i , a , b , c ) BEGIN CASE i IS WHEN 3 => z <= a; WHEN 0 TO 2 => z <= b; WHEN OTHERS => z <= c; END CASE; END PROCESS p1; END case_behave;

4.2 Sequential circuits:

Latch

ENTITY latch IS PORT ( a,b: c: END latch;

IN bit; OUT bit );

ARCHITECTURE behave OF latch IS BEGIN PROCESS (a,b) BEGIN IF ( a = '0' ) THEN c <= b; END IF; END PROCESS; END behave;

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D-Flip-Flop

ENTITY d_ff IS PORT(clk,d: IN std_ulogic; q: OUT std_ulogic); END d_ff;

ARCHITECTURE behave1 OF d_ff IS BEGIN PROCESS BEGIN WAIT UNTIL clk ' EVENT AND clk = '1' THEN q <= d; END PROCESS; END behave1;

ARCHITECTURE behave2 OF d_ff IS BEGIN PROCESS(clk) BEGIN IF clk ' EVENT AND clk = '1' THEN q <= d; END IF; END PROCESS; END behave2;

ARCHITECTURE behave3 OF d_ff IS BEGIN PROCESS BEGIN WAIT UNTIL clk ' EVENT AND clk = '1' AND clk ' LAST_VALUE = '0'; q <= d; END PROCESS; END behave3;

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ARCHITECTURE behave4 OF d_ff IS BEGIN PROCESS (clk) BEGIN IF clk ' EVENT AND clk = '1' AND clk ' LAST_VALUE = '0'; q <= d; END IF; END PROCESS; END behave4;

T-Flip-Flop:

ENTITY t_ff IS PORT(clk, enable: IN std_ulogic; q: OUT std_ulogic); END t_ff;

ARCHITECTURE behave OF t_ff IS BEGIN PROCESS BEGIN WAIT UNTIL clk ' EVENT AND clk = '1' AND clk ' LAST_VALUE = '0'; IF enable = '1' THEN q <= NOT q; END IF; END PROCESS; END behave;

Flip-flop with asynchronous signals (RESETS):

ENTITY d_ff IS PORT(clk,d, reset: q: END d_ff;

IN std_ulogic; OUT std_ulogic);

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ARCHITECTURE asyn_behave OF d_ff IS BEGIN PROCESS(clk,reset) BEGIN IF reset = '1' THEN --active high reset Q <= '0'; ELSIF clk ' EVENT AND clk = '1' AND clk ' LAST_VALUE = '0' THEN Q <= d; END IF; END PROCESS; END asyn_behave;

4.3 State Machine:

Medvedev

Logic Input

FlipFlop

Output

Moore

Logic Input

FlipFlop

Logic

Output

Mealy

Logic Input

FlipFlop

Q Logic Output

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Memorystate: PROCESS (clk, reset) BEGIN IF( reset = 1) THEN State <= reset_state; ELSIF (clkevent AND clk = 1 AND clkLAST_VALUE = 0 ) THEN state <= next_state; END IF; END PROCESS Memorystate;

Transitionlogic: PROCESS (state, in1, in2,. . .) BEGIN CASE state IS WHEN state1 => IF (in1= . . . AND in2 = . . . AND . . .) THEN next_state <= . . . ; ELSIF . . . WHEN state2 => ... END CASE; END PROCESS Tansitionlogic;

outputlogic: PROCESS (state, in1, in2, . . . ) BEGIN CASE state IS WHEN state1 => IF (in1= . . . AND in2 = . . . AND . . .) THEN out1 <= . . . ; out2 <= . . . ; . . . ELSIF . . . WHEN state2 => ... END CASE; END PROCESS outputlogic;

4.4 Tristate-Structure:

y <= a WHEN en=1 ELSE Z; y <= a WHEN en=1 ELSE L; y <= a WHEN en=1 ELSE H;
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Pulldown Pullup

Resolve function:

The Resolve function assigns a unique value to a bus at the same time, on which several drivers (outputs) can write.
Example: Driver 1 1 1 1 Driver 2 1 0 H Driver 3 Z Z L Line condition 1 X 1

All lines, which are driven by several outputs, must be by one resolved type (std_logic/std_logic_vector). Then with each allocation the Resolve function is called automatically.
Signal type std_logic std_logic_vector std_ulogic std_ulogic_vector Number of attached outputs More than one output More than one output Max. one output Max. one output

resolved resolved unresolved unresolved

Controlled signal allocation:

Controlled signal allocation (on normally defined signal) Block_label: BLOCK (Condition) BEGIN signal_name <= GUARDED value; END BLOCK; equivalent IF instruction IF Condition THEN signal_name <= value; END IF;

Controlled signals:
Controlled signals characterized by the addition REGISTER or BUS then the signal from the function of a trichloroethylene acts tristate-Treibers.
Declaration of a controlling signal SIGNAL signal_name [, signalname2, ...] : std_logic[vector] REGISTER | BUS [:= defaultvalue];

SIGNAL y:std_logic BUS; SIGNAL y:std_logic REGISTER;

48

Controlled signal allocation (on in as " controlling signal " defined signal) Block_label: BLOCK (condition) BEGIN signal_name <= GUARDED value; END BLOCK;

equivalent IF instruction IF condition THEN Signal_name <= value; ELSE Signal_name <= NULL; END IF;

Checked signal allocation for such a signal:

Active drivers 0 0 0 Declaration of the controlling signal Arbitrary BUS REGISTER Signal status Resolve-Function Default value of the Resolve function (ith a. ' Z ') last assigned value

Switch off from controlling signals (signal drivers) DISCONNECT signal_name [,signal_name2, ...]: DISCONNECT y:std_logic AFTER 10 ns; std_logic[vector] AFTER time; DISCONNECT ALL:std_logic AFTER 20 ns; DISCONNECT OTHERS: std_logic[vector] AFTER time; DISCONNECT ALL: std_logic[vector] AFTER time; Example. Tristate-Driver with Timing

ENTITY tristate IS GENERIC( ton: toff: PORT( a en y END tristate;

TIME:=20 ns; TIME:=10 ns); :IN std_ulogic; :IN std_ulogic; :OUT std_logic BUS);

ARCHITECTURE tristate_behave OF tristate IS DISCONNECT y:std_logic AFTER toff; BEGIN treiben: BLOCK(en='1') BEGIN y<=GUARDED a AFTER ton; END BLOCK treiben; END tristate_behave;

49

4.5 Delay models:

Sig_a <= 1 AFTER 2 ns, 0 AFTER 5 ns, 1 AFTER 12 ns, 0 AFTER 15 ns, 1 AFTER 10 ns, 1 AFETR 17 ns;

Sig_a<=TRANSPORT 1 AFTER 11 ns

renewed allocation at the point in time t=2 ns

Sig_a<=1 AFTER 11 ns

renewed allocation at the point in time t=2 ns

Sig_s <= TRANSPORT 1 AFTER 1 ns, 1 AFTER 10 ns, 1 AFTER 18 ns, 1 AFTER 25 ns, sig_t <= TRANSPORT sig_i <= sig_r <= REJECT 2 ns INTERNAL

0 AFTER 5 ns, 0 AFTER 13 ns, 0 AFTER 20 ns, 0 AFTER 26 ns,

sig_s AFTER 3 ns; sig_s AFTER 3 ns; sig_s AFTER 3 ns; -- ! VHDL 93

50

4.6 Structural modelling

The structural Modelling corresponds to wiring components in form of a network list. This occurs in three steps: Declaration: Announce the component (prototype declaration) Instantiation: Definition of the wiring and characteristic values. Configuration: Announce the Models, in the behavior is described.

Component declaration.:
COMPONENT COMPONENT component_name [IS] [GENERIC (param_1[,..., param_n]: type_name[:=default_value] [; ...]);] [PORT (port_1[,...,port_n]: mode type_name[:=default_value] [; ...]);] END COMPONENT [component_name];

Component instantiation:
GENERIC MAP/PORT MAP Instant_name: [COMPONENT] component_name [GENERIC MAP (param_value_1, ..., param_value_n)] [PORT MAP (signal_name_1,...,signal_name_n)];

Also possible for the allocation of the parameter values or port and signals: port_1 => signal_name_1, port2 => signal_name_2, ... OPEN as signal_name:Not attached pin (possible default_value assumed) Components Configuration
CONFIGURATION CONFIGURATION configuration_name OF entity_name IS Configuration statements END [CONFIGURATION] [configuration_name];

Here ite determines, which ENTITY and which ARCHITECTURE from which LIBRARY for the component are used.

51

3 to 8

3 to 8

ENTITY cs_decoder IS PORT( a0, a1, a2, a3, a4, a5: cs: END cs_decoder;

IN OUT

std_ulogic; std_ulogic);

ARCHITECTURE structural OF cs_decoder IS SIGNAL intern_a, intern_b:std_ulogic; COMPONENT 3to8 GENERIC(td:TIME:=2 ns); PORT(i0,i1,i2:IN std_ulogic; o0,o1,o2,o3,o4,o5,o6,o7:OUT std_ulogic); END COMPONENT; COMPONENT and_2 GENERIC( tdlh: TIME:=1.5 ns; tdhl: TIME:=2 ns); PORT(a,b:IN std_ulogic; y:OUT std_ulogic); END COMPONENT; BEGIN decoder1: 3to8 decoder2: 3to8 and_gate: and_2 GENERIC MAP (3 ns) PORT MAP( a0, a1, a2, OPEN, OPEN, OPEN, OPEN, OPEN, OPEN, OPEN, intern_a); PORT MAP( i0=>a3, i2=>a5, i1=>a4, o5=>intern_b, OTHERS=>OPEN); GENERIC MAP (1 ns, 1.5 ns) PORT MAP( intern_a, intern_b, cs);

END structural; CONFIGURATION decoder_config OF decoder IS FOR structural FOR decoder1: 3to8 USE ENTITY decoder_lib.3_zu_8_decoder (behavioral_architecture); END FOR; FOR decoder2: 3to8 USE ENTITY decoder_lib.3_zu_8_decoder (synthese_architecture); END FOR; FOR ALL: and_2 USE ENTITY gate_lib.and2 (architecture_name); 52

END FOR; END FOR; END decoder_config;

Modelling of configuration:
3 to 8

3 to 8

LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; LIBRARY work; USE work.ALL; ENTITY cs_decoder IS PORT( a0, a1, a2, a3, a4, a5: cs: END cs_decoder; IN OUT std_ulogic; std_ulogic);

ARCHITECTURE structural OF cs_decoder IS SIGNAL intern_a, intern_b:std_ulogic; COMPONENT 3to8 GENERIC(td:TIME:=2 ns); PORT(i0,i1,i2:IN std_ulogic; o0,o1,o2,o3,o4,o5,o6,o7:OUT std_ulogic); END COMPONENT; COMPONENT and_2 GENERIC( tdlh: TIME:=1.5 ns; tdhl: TIME:=2 ns); PORT(a,b:IN std_ulogic; y:OUT std_ulogic); END COMPONENT; FOR ALL: 3to8 USE ENTITY work.3to8 (behavioral_architecture); FOR ALL: and_2 USE ENTITY work.and_2 (architecture_name); BEGIN Decoder1: 3to8 Decoder2: 3to8 and_gate: and_2 END structural; GENERIC MAP (3 ns) PORT MAP( a0, a1, a2, OPEN, OPEN, OPEN, OPEN, OPEN, OPEN, OPEN, intern_a); PORT MAP( i0=>a3, i2=>a5, i1=>a4, o5=>intern_b, OTHERS=>OPEN); GENERIC MAP (1 ns, 1.5 ns) PORT MAP( intern_a, intern_b, cs);

53

Direct Instantiation (only with VHDL ' 93 possible)

Does not need a component declaration and no configuration. This is particularly favourable, if the component occurs only once.

Reference to configuration Instanz_name: CONFIGURATION library_name.configuration_name [GENERIC MAP (param_value_1, ..., param_value_n)] [PORT MAP (signal_name_1,...,signal_name_n)];

Reference to Entity Instant_name: ENTITY library_name.entity_name (architecture_name) [GENERIC MAP (param_value_1, ..., param_value_n)] [PORT MAP (signal_name_1,...,signal_name_n)]; Above ex. with direct Instantiation:: ENTITY cs_decoder IS PORT( a0, a1, a2, a3, a4, a5: cs: END cs_decoder;

IN std_ulogic; OUT std_ulogic);

ARCHITECTURE structural OF cs_decoder IS SIGNAL intern_a, intern_b:std_ulogic; BEGIN decoder1: OPEN, decoder2: 3to8 and_gate: and_2 END structural; ENTITY decoder_lib.3_zu_8_decoder (behavioral_architecture) GENERIC MAP (3 ns) PORT MAP( a0, a1, a2, OPEN, OPEN, OPEN, OPEN, OPEN, OPEN, intern_a); ENTITY decoder_lib.3_zu_8_decoder (synthese_architecture) PORT MAP(i0=>a3, i2=>a5, i1=>a4, o5=>intern_b, OTHERS=>OPEN); CONFIGURATION gate_lib.and2_config GENERIC MAP (1 ns, 1.5 ns) PORT MAP(intern_a, intern_b, cs);

BLOCK:
With the BLOCK statement several components can be combined into a block, so that one receives within the Architecture one additionally to hierarchic level.
BLOCK Block_name: BLOCK [IS] Declaration BEGIN concurrent statements END BLOCK [configuration_name];

54

ARCHITECTURE structural OF cs_decoder IS SIGNAL intern_a, intern_b:std_ulogic; COMPONENT and_2 GENERIC( tdlh: TIME:=1.5 ns; tdhl: TIME:=2 ns); PORT(a,b:IN std_ulogic; y:OUT std_ulogic); END COMPONENT; BEGIN decoder: BLOCK PORT(in0, in1, in2, in3, in4, in5: IN std_ulogic; out1, out2: std_ulogic); PORT MAP ( in0=>a0, in1=>a1, in2=>a2, in3=>a3, in4=>a4, in5=>a5, out1=>intern_a, out2=>intern_b); COMPONENT 3to8 GENERIC(td:TIME:=2 ns); PORT(i0,i1,i2:IN std_ulogic; o0,o1,o2,o3,o4,o5,o6,o7:OUT std_ulogic); END COMPONENT; GENERIC MAP (3 ns) PORT MAP( in0, in1, in2, OPEN, OPEN, OPEN, OPEN, OPEN, OPEN, OPEN, out1); decoder2: 3to8 PORT MAP(i0=>in3, i2=>in5, i1=>in4, o5=>intern_b, OTHERS=>OPEN); END BLOCK decoder and_gate: and_2 GENERIC MAP (1 ns, 1.5 ns) PORT MAP(intern_a, intern_b, cs); BEGIN decoder1: 3to8

END structural;

4.7 Generate:
To the simple structural description of regular structures.
GENERATE with condition Generate_name: IF condition GENERATE [ Declaration BEGIN] Concurent sratement END GENERATE [generate_name];

GENERATE as loop Generate_name: FOR variable IN length GENERATE [ Declaration BEGIN] Concurent sratement END GENERATE [generate_name];

Example: n-Bit Register

55

ENTITY n_bit_register IS GENERIC ( n : IN positive := 4); PORT (clk : IN bit ; reg_in : IN bit_vector ( n-1 DOWNTO 0) ; reg_out : OUT bit_vector(n-1 DOWNTO 0) ); END n_bit_register;

ARCHITECTURE structural OF n_bit_register IS COMPONENT d_ff_socket PORT (d, clk : IN bit ; q : OUT bit ); END COMPONENT ; BEGIN reg : FOR i IN n-1 DOWNTO 0 GENERATE d_ff_instance : d_ff_socket PORT MAP ( reg_in( i ), clk, reg_out ( i ) ) ; END GENERATE ; END structural;

Example: n-Bit Shift registers:

ENTITY shift_register IS GENERIC ( n : IN positive RANGE 2 TO 64 := 4); PORT (clk , ser_in : IN bit ; ser_out : OUT bit ; END shift_register;

56

ARCHITECTURE structural OF shift_register IS SIGNAL intern : bit_vector (1 TO n-1 ) ; COMPONENT d_ff_socket PORT (d, clk : IN bit ; q : OUT bit ) ; END COMPONENT ; BEGIN reg : FOR i IN n DOWNTO 1 GENERATE --first D-FF : with input wires-------------------------------------------------------------------------------reg_begin : IF i = 1 GENERTATE d_ff_begin : d_ff_socket PORT MAP ( ser_in, clk, intern ( i ) ) ; END GENERATE ; --middle D-FFs ----------------------------------------------------------------------------------------------------reg_middle : IF i > 1 AND i < n GENETATE d_ff_middle : d_ff_socket PORT MAP ( intern( i 1 ), clk, intern ( i ) ) ; END GENERATE ; --last D-FF: with out put wires----------------------------------------------------------------------------------reg_last : IF i = n GENERTATE d_ff_last : d_ff_socket PORT MAP ( intern( i 1 ) , clk , ser_out ) ; END GENERATE ; END GENERATE ; END structural ;

4.8 Testbench:
Testbench models serve for the check of a VHDL model. The inputs module which can be tested according to the desired function are headed and the outputs are queried with the debit result compared. If deviations occur, errors, warnings or Notes are given as a output. That has the advantage, which the user does not have to decide on the basis of the output in the Wave Window in relation to the simulation with Force files whether a malfunctioning is present.

Example: Testbench for NAND2

57

ARCHITECTURE strategy_1 OF nand2_tb IS COMPONENT nand2_socket PORT ( in1, in2 : IN bit ; out1 : OUT bit) ; END COMPONENT ; SIGNAL a, b, c : bit ; SUBTYPE t2 IS bit_vector ( 1 TO 2 ) ; BEGIN --------Instanation of model under test ( mut )--------------------------------------------------mut : nand2_socket PORT MAP (a, b, c ) ; -------- description of the input signals (stimuli)-----------------------------------------------stimuli_generation : PROCESS BEGIN ------ an allocation of the point in time o ns ( a, b ) <= t2 ( 01 ) AFTER 10 ns , ---qualifier t2 ( 10 ) AFTER 20 ns , ---printout t2(. . .) t2 ( 11 ) AFTER 30 ns , t2 ( 00 ) AFTER 40 ns , WAIT; END PROCESS; ----- examination of the model-output ( response ) --------------------------------------------response_control : PROCESS BEGIN WAIT FOR 12 ns; ASSERT c = 1 REPORT wrong result SERVERITY note; WAIT FOR 10 ns; ASSERT c = 1 REPORT wrong result SERVERITY note; WAIT FOR 10 ns; ASSERT c = 0 REPORT wrong result SERVERITY note; WAIT FOR 10 ns; ASSERT c = 1 REPORT wrong result SERVERITY note; WAIT; END PROCESS; END strategy_1

58

Laboratory Tasks

59

5 Introduction to VHDL Laboratory

Practising VHDL programming is one of the important things to sharp your skills and become familiar in it, a direct application on VHDL will increase your knowledge and deep your experience in handling electronic design applications. Just reading and understanding VHDL literature is not sufficient to succeed in it, however working on simulation and implementation with less knowledge about VHDL language and syntax will not achieve the optimum solution. This means both directions must be integrated together and each part will be a complementary to the other. A Rolling Dice with Melody Sound project has been introduced for this purpose. An electronic dice will be simulated, synthesised and emulated on FPGA. The target is to write source files that simulate the behaviour of a dice with melody sound.

60

6 Rolling Dice with Melody Sound

From the title name, it is clear that the project will be about an electronic rolling dice with melody sound. The following features of this dice must be met: 1. The dice must scroll from 1 to 6 with LEDs blinking; ticking-sound is generated while it is scrolling from one number to another. 2. Deceleration of rolling speed depends on the push-button duration on the dice; if the time-push was longer then the initial velocity of the scrolling will be high and vice versa. 3. A melody is generated after the velocity reaches to zero and the dice stands on one number, according to this number the melody will be generated. Number 6 will have long-time melody, number 1 will have middle-time melody while the rest numbers from 2 to 5 will have short-time melody. 4. Three options must be controlled from outside by three switches: A switch to enable or disable melody-sound and tick-sound of the dice. A switch to enable or disable the tick-sound only. A switch to select the melody sound either to have 3 melodies as described before or to have a unique melody for all the cases, in other word, either numbers 6, 1 and 2 to 5 will have three distinguished melodies or numbers 1 to 6 will have the same melody which will be the short-time melody. 5. Power off mode, after around 5 seconds from melody off, the LEDs will be switched off automatically for battery saves. These specifications must be taken in consideration while writing down the source files of the dice. The question raised here, how to describe the behaviour of a dice? Figure 6-1 shows the complete dice hardware product, it consists mainly from the chip board itself, LEDs, push-button, speaker and battery. What we are concerned about is to write down the source file of its behaviour. Figure 6-2 shows the main parts of the internal dice. The three main parts are: 1. Clock generator 2. Dice generator 3. Sound generator Completion of these three parts will bring the dice into function; each part must be developed and checked to meet the requirment. More information is in the next section.

61

Push Button Battery

LEDs

Speaker

Chip Board

Figure 6-1

Complete Dice Hardware

Dice

Clock Generator

Dice Generator

Sound Generator

Ton Signal

Decoder

Melody

Pulse Signal

Counter

Tick

NCO Figure 6-2 Main Sub-Blocks of the Dice

62

7 Laboratory Assignments
The lab is divided into seven sections, they are as followed: 1. First section will be an introductory example to become more familiar in using VHDL programming. 2. Second section is about simulating the clock generator. 3. Third section is about simulating the dice generator. 4. Fourth section is also about simulating sound generator. 5. Fifth section is simulating the overall parts together forming the top sheet of the dice. 6. Sixth section is about synthesising the overall system. 7. Seventh section is to emulate the overall system on an FPGA to ensure correctness behaviour of the dice.

7.1 Lab Assignment 1 (Introductory Example)

Starting directly to write VHDL code for the first time is not that simple, to have an easy starting, an incomplete source file of a counter will be given. After launching HDL designer program from Mentor Graphics, start a new project titled counter_project, in this project open a new vhdl source file and save it counter.vhd

Launching HDL Designer Software

A counter has to count upward and downward, the input and the output signals are declared in the entity part.
63

Counter Source Code

Here is the source code of the counter
------------------------------------------------------- EXAMPLE OF TWO BIT COUNTER -------------------------------------------------------- Library Declaration -LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; --------------------------------------------ENTITY --------------------------------------------ENTITY counter IS PORT( reset :IN std_logic; clk :IN std_logic; up :IN std_logic; down :IN std_logic; q_0 :OUT std_logic; q_1 :OUT std_logic; b :OUT std_logic; --borrow c :OUT std_logic --carry ); END counter; --------------------------------------------ARCHITECTURE --------------------------------------------ARCHITECTURE behave OF counter IS TYPE state IS (st_0,st_1,st_2,st_3); SIGNAL mode, nxt_mode : state; BEGIN -- Registered Process -clk_proc : PROCESS (clk,reset) BEGIN IF (reset='0') THEN -- Active Low Reset -mode <= st_0; ELSIF (clk'EVENT AND clk='1' AND clk'LAST_VALUE='0') THEN mode <= nxt_mode; END IF; END PROCESS clk_proc; -- Combinational Process -counter_proc : PROCESS (mode,up,down) BEGIN CASE mode IS WHEN st_0 => IF up='1' AND down='0' THEN nxt_mode <= st_1; ELSIF up='0' AND down='1' THEN nxt_mode <= st_3; END IF; WHEN st_1 => . --- Complete the statements !! --. . .

64

-- Output Process -output_proc : PROCESS (mode,up,down) BEGIN IF mode=st_0 AND up='0' AND down='1' THEN b<='1'; ELSE b<= . --- Complete the statement !! --END IF; IF mode=st_3 AND up='1' AND down='0' THEN c<= . .. .. IF mode=st_0 OR mode=st_1 THEN q_1<= . . IF mode=st_0 OR mode=st_2 THEN q_0<<= END .. .

Figure 7-1

Counter Source Code

After completing the source code, it must be compiled to check if errors are found. If not then a testbench or a force file must be written to simulate the source file.

65

Counter Do File
A force file do file will be given for the previous example. Open a new empty do file source and save it as counter_dofile.do
----------------------------------- Couter 2_bit Do File ------------------------------------ Reset Simulation -restart -force -nolist -nowave -nobreak -nolog onerror {resume}

-- Add the waves needed to be displayed --- Two ways can be written, either each --- signal by its name or use '/*' for all -add wave /* -- Force all the input signals, clk, reset... --- Clock period 10 ns --- the signal name must be given after force clause -- 2 vlaues must be give, the bit value and the time value -- for example 0 bit at 0 ns, 1 at 5 ns and so on -force clk 0 0,1 5 -r 10 -- -r is used for repetition -force reset 0 0 force reset 1 10 force up 1 0, 0 500 force down 0 0,1 500 run 1000 Figure 7-2 Counter Do-File

In a force file, input signals are forced to different values to ensure all possible cases that could the system falls on.

66

Simulation Result of 2 bits Counter

Figure 7-3

Simulation Result of Counter

67

7.2 Lab Assignment 2 (Clock Generator)

After having some practice with counter project, now start a completely new project dice_project, avoid saving the new files in the old project!. In this section, the clock generator will be designed. The clock is the main trigger of the system, a crystal oscillator of frequency 32 KHz is used to trigger the overall system. There are many sub-frequencies needed in this design which have less frequency of 32 KHz. To generate the rest lower frequencies, clock dividers are used for this purpose.

pulse_1000 reset_n clock enable pulse_500

Clock Generator

pulse_32 pulse_8 time_out tone_6400 tone_5333 tone_4000

Figure 7-4 reset_n

Circuit Diagram of Clock generator

time_out clk_32KHz 1:16 1:2 1:2 1:16 1:4 1:64

pulse_2000

pulse_1000

pulse_500

pulse_32

pulse_8

1:5

tone_6400

tone_ 1:3 1:2 tone_5333 pulse_ 1:8 tone_4000

Figure 7-5

Structure of Clock Generator

Two types of signals are needed: 1. Tone signals which are used to generate the melody and tick sound frequencies, these signals will be referred as tone_xxxx (for example xxxx = 4000 Hz => tone_4000).

68

2. Pulse signals which are used to trigger the states, registers and flip-flops, these signals will be referred as pulse_xxxx (for example xxxx = 1000 Hz => pulse_1000). Figure 7-4 shows the block diagram of the clock generator. To get more in details about the internal structure of the clock generator, figure 7-5 illustrates the structure of this part. To generate the different tones and pulses of the circuit, a clock divider is needed to generate sub-frequencies from the main clock of the system.

Two Bits Clock Divider

A two bits clock divider is a circuit that generates the following output as shown in figure 7-6.

clock reset_n clock enable q

Two Bits Divider

carry

enable

carry

Figure 7-6

Circuit of 2 bits divider and its timing diagram

To increase the number of division, cascaded blocks can be used for this purpose. For example, the output of four bits division is shown in figure 7-7.

clock

enable

carry Figure 7-7 Timing Circuit of 4 bits clock divider

The carry signals will be assigned to the pulse signals and the q signals will be assigned to the tone signals. To generate 3 bits and 5 bits dividers for ton signals, Mark and Space ratios of 2:1 and 3:2 must be used. Since 3 and 5 are not even numbers, division with equal ratios of ones and zeros is not reachable, in this case 2:1 and 3:2 ratios between ones and zeros are used to generate the desired frequency signals. - Use case statement to build up your 2-bits clock divider and other dividers! Dont use if else statement avoiding priority races. - Use always std_logic and arithmetic packages but not numeric package!
69

Simulation Result of 2 bits Clock Divider

Figure 7-8

Simulation Result of 2 bits Clock Divider

70

Simulation Result of 8 bits Clock Divider

Figure 7-9

Simulation Result of 8 bits Clock Divider

71

Simulation Result of 5 bits Clock Divider

Figure 7-10

Simulation Result of 5 bits Clock Divider

72

Simulation Result of Clock Generator

Figure 7-11

Simulation Result of Clock Generator

73

7.3 Lab Assignment 3 (Dice Generator)

In this section, the dice generator will be designed and simulated. Figure 7-12 shows the entity of the dice generator.

reset_n clk pulse_500 pulse_32

Dice Generator
Decoder Counter NCO

a_f b_e c_d g one six start_tick start_melody

push_button

Figure 7-12

Basic Circuit Diagram of Dice Generator

The dice generator consists of a decoder, counter and numerically controlled oscillator (NCO), these three parts form the heart of the dice, figure 7-13 shows the internal blocks of the dice generator.

reset_n clk enable reset_n clk reset_n clk up down

Decoder

a_f b_e c_d g one six

a_f b_e c_d

g q carry zero

pulse_500 pulse_32

Counter

one six

push_button

reset_n clk enable a

start_tick

NCO
6

carry

start_melody

Figure 7-13

Structural Diagram of Basic Dice Circuit

74

The decoder is responsible to deliver the signals to the LEDs and decode the scrolling number and displays it, figure 7-13 shows the entity block of the decoder, the outputs are used to control the display and the sound generator.

reset_n clk enable

Decoder

a_f b_e c_d g one six

b g

d c_d 1 1 g 0 1

a_f 1 2 3 4 5 6 Figure 7-14 0 0

b_e 0 0

Entity, Outer Structure and Truth Table of the Dice Decoder

The counter performs the counting function of 6 bits resolution. The output signals of the counter are used to control the NCO, the counter itself and the sound generator. Beside the 6 bits output (q) of the counter, there is a carry and zero signal. Once the counter reaches the maximum then a carry signal is generated. The same for the zero, once the counting reaches to zero then a zero signal is generated. Numerically controlled oscillator (NCO) is used to control the acceleration and deceleration of the rolling speed. Figure 7-14 shows the structure of the NCO. The speed of rolling is determined by the carry signal of the adder.

carry 8 a 6 Slow 8 Bits 8

clk enable

reset_n

Fast

8 Bits Register

Figure 7-15

Structure and Output of NCO

To build up the complete dice generator structure, individual internal parts must be programmed and simulated.

75

The counter will contain (up/down) counting mode depending on the input signal, the counter must generate 6 bits output (q) which stands for the counted value, a carry and zero signals will be generated. The decoder must generate the output signals for displaying, two additional signals (one and six) are used later in sound generator section. The NCO must generate a carry signal once counting reach saturation, according to the amount of signal (a) the carry will be generated either fast or slow depending on (a) signal value. The three internal blocks in figure 7-13 must be combined and connected to each other, the following specification must be taken in consideration while connecting the input and the output of the outer entity with the internal entity blocks: 1. Decoder scrolls continuously if push_button is high or carry signal of the NCO is high! 2. The counter counts up with a frequency of 32 Hz while push_button is high and its maximum final value of its counting does not exceed 63 i.e. it counts from 0 to maximum value of 63 so that there is no overflow occurs. Think of its carry! 3. The counter counts down when push_button is low and the carry of NCO is high! 4. The NCO will perform addition every 2 ms! 5. start_tick is activated when push_button is low and another signal is (find out!) 6. start_melody is activated when the counting value of the counter reaches to zero! These conditions must be satisfied to insure the correct behaviour of the dice generator block. The simulation results of each part and the overall dice generator part is shown in the following pages.

76

Simulation Result of the Decoder

Figure 7-16

Simulation Result of Decoder (1)

77

Figure 7-17

Simulation Result of Decoder (2)

78

Simulation Result of the Counter

Figure 7-18

Simulation Result of the Counter

Note: To get an analog presentation, go to the signal on the left side, right click, and then change format to analog and radix to unsigned signal.
79

Simulation Result of the NCO

Figure 7-19

Simulation Result of the NCO

80

Simulation Result of Dice Generator

Figure 7-20

Simulation Result of Dice Generator

81

7.4 Lab Assignment 4 (Sound Generator)

In this section the sound generator will be developed, it is responsible to generate the ticking and melody sounds of the dice. Figure 7-21 shows the block diagram of the sound generator.

push_button reset_n clk tone_6400 tone_5333 tone_4000 pulse_1000 pulse_8 one six start _melody start_tick melody_enable tick_enable melody_select

Sound Generator
speaker

Tick Melody

Figure 7-21

Sound Generator Block Diagram

Description of Sound Generator: 1. The three input tones of frequencies (6400, 5333 and 4000) are used to deliver the different sound waves. 2. Pulses (1000 and 8) are used to control the jump states. 3. One and six signals to enable special melody for them. 4. Start melody and tick signals to declare the beginning of each. 5. Melody enable signal to enable the speaker of melody sound only. 6. Tick enable signal to enable the speaker of ticking sound only. 7. Melody selection to select either one melody for all options or three different melodies for numbers 6, 1 and 2 to 5. The following truth table presents the operation of the Sound Generator.
Table 7-1 Truth Table of Sound Generator

start_tick 1 0 0 0

start_melody 0 1 1 1

one X 1 0 0

Six X 0 1 0

1 f1 f3 f1 f1

2 f1 f2 f2 f2

3 f1 f1 f3 -

4 f1 -

5 f2 -

6 f3 -

7 f1 -

Where f1=tone_4000, f2=tone_5333 and f3=tone_6400.

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The last three enable signals (melody, tick and melody select) are externally controlled by the user himself depending on his desired mode. Input signal pulse_1000 is the condition to go from one state to another state when the counter of the dice is in the counting mode that is during scrolling mode. Inputs signal pulse_8 is the condition to go from one state to another state to generate melody when it is in the melody mode. To simulate the sound generator part, the overall system must be running in order to generate the necessary input signals. For that, to be sure of the simulation behaviour, this section will be simulated with the next section.

7.5 Lab Assignment 5 (Top Sheet Dice)

In this section, the overall system will be combined to form the top sheet of the dice with its all sub-blocks. That is the clock generator, dice generator and the sound generator. Figure 7-22 shows the top sheet structure of the complete dice. The final entity must have exactly the same names of ports as shown in the top sheet of the dice as well as the entity name must be top_sheet! these assignments are important for synthesis. The three blocks are exactly the same but the only difference is in the clock generator block. Still the power off mode is not being yet implemented. In order to fulfil it, the time_out signal that is generated from the clock generator will be used for this purpose, the point is that the time out is not being yet synchronized with the push_button input signal to ensure that time out will not occur unless the dice is run and the melody is off. To apply that, a slight change must be done in the clock generator in the last block divider which is 1:64to ensure that the time out will run after the push button is released and a time of 8 seconds is passed then a time_out signal will be generated.

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reset_n clk push_button enable tick_enable melody_enable melody_select

Dice Top Sheet

g c_d b_e a_f time_out speaker

reset_n clock enable push_button

Clock Generator

pulse_1000 pulse_500 pulse_32 pulse_8 time_out tone_6400 tone_5333 tone_4000

reset_n clk pulse_500 pulse_32 push_button

Dice Generator

a_f b_e c_d g one six start_tick start_melody

push_button reset_n clk tone_6400 tone_5333 tone_4000 pulse_1000 pulse_8 one six start _melody start_tick melody_enable tick_enable melody_select

Sound Generator

speaker

Figure 7-22

Structural Model of Complete Dice Circuit

84

Simulation Result of Sound Generator

Figure 7-23

Simulation Result of Sound Generator

85

Simulation Result of the Top Sheet Dice

Figure 7-24

Simulation Result of Top Sheet Dice (1)

86

Figure 7-25

Simulation Result of Top Sheet Dice (2)

87

7.6 Lab Assignment 6 (Synthesis)

While simulation is the process of using a model to describe the behaviour of a physical system, synthesis is the complementary process of constructing a physical system from a model. The physical design is automatically generated from an abstract description using a pre-defined set of basic building blocks such as logic gates. Synthesis is a design process that operates in three types of information: 1. The first is the model of the circuit which is the VHDL model. 2. Second is the set of conditions on the resulting circuit such as speed and area. 3. Third is the set of input components that are to be used to construct the circuit. Knowing these three types, synthesis operation can be performed. The final output of this process will be a netlist file called EDIF file which stands for Electronic Design Interchange Format. Using this edif file, a further operation can be done which is emulation and layout generation. In this lab, we are going to use Precision Synthese software to perform our target. The following file has to be added as the top sheet to your project, be sure that the instantiated component has the same port names to avoid conflict during synthesis process:
LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; ENTITY top_sheet_xilinx IS PORT( melody_enable : IN std_logic; melody_select : IN std_logic; push_button : IN std_logic; reset_n : IN std_logic; schmitt_in : IN std_logic; tick_enable : IN std_logic; a_f : OUT std_logic; b_e : OUT std_logic; c_d : OUT std_logic; g : OUT std_logic; schmitt_out : OUT std_logic; speaker : OUT std_logic; speaker_not : OUT std_logic; time_out : OUT std_logic ); END ENTITY top_sheet_xilinx; ARCHITECTURE behave OF top_sheet_xilinx IS -- Declaration der internen signale SIGNAL a_f_sig, b_e_sig, c_d_sig, g_sig, time_out_sig, clk, enable_sig -- Component Declarations COMPONENT top_sheet PORT ( clk : IN std_ulogic; enable : IN std_ulogic; melody_enable : IN std_ulogic; melody_select : IN std_ulogic; push_button : IN std_ulogic; reset_n : IN std_ulogic; 88

: std_ulogic;

tick_enable : IN std_ulogic; a_f : OUT std_ulogic; b_e : OUT std_ulogic; c_d : OUT std_ulogic; g : OUT std_ulogic; speaker : OUT std_ulogic; time_out : OUT std_ulogic ); END COMPONENT; BEGIN clk <= not schmitt_in; --Def. der OUTPUT's schmitt_out <= clk; a_f <= not a_f_sig; b_e <= not b_e_sig; c_d <= not c_d_sig; g <= not g_sig; speaker_not <= '0'; enable_sig <= '1'; --Sleepmodus D_FF:PROCESS (clk, reset_n, push_button, time_out_sig) BEGIN IF (reset_n ='0' OR push_button = '1') THEN time_out <= '1'; ELSIF(RISING_EDGE(clk)) THEN IF (time_out_sig = '1') THEN time_out <= '0'; END IF; END IF; END PROCESS; -- Portmapping U_0 : top_sheet PORT MAP ( reset_n => reset_n, clk => clk, push_button => push_button, enable => enable_sig, tick_enable => tick_enable, melody_enable => melody_enable, melody_select => melody_select, g => g_sig, c_d => c_d_sig, b_e => b_e_sig, a_f => a_f_sig, time_out => time_out_sig, speaker => speaker ); END;

After adding this file as a top sheet, the next step is to compile all the files together by clicking ModelSim Compile after selecting the highest top sheet which is the top_sheet_xilix, the compiler will compile all the sub sheets and components beyond the top component. Later click on Precision Synthese from Task-Menu window as shown in figure 7-26, the Precision Synthesis Settings will be started.

89

Figure 7-26

Precision Setting of the CPLD

The following settings have to be selected: Technology: XILINX Coolrunner 2 Device: 2c128vq100 Speed: -7

Figure 7-27

Generated Precision Output Files

90

While synthesizing, if any error occurred then double click on the error message and you will be linked directly to the error place. After syntheses, save the project directly to check out the generated files. Figures 7-28 and 7-29 show the RTL schematic view of the dice (only for demonstration!).

Figure 7-28

Top component RTL diagram (Example!)

91

Figure 7-29

Sub-components of the top sheet (Example!)

Figure 7-30

Area report generated by Precision tool (Example!)

92

Figure 7-31

EDIF generated file (Example!)

Figure 7-30 is the generated area report file. The percentage of used logic cells and flip-flops are mentioned in the file (only for demonstration!). Figure 7-31 is the generated EDIF file, it maps the project to the selected technology device (only for demonstration!).

7.7 Lab Assignment 7 (Place & Route)

The last step is to check the system on hardware; this process is called emulation on hardware device. In this case, CPLD device from XILINX will be used to emulate the overall system. The software that will be used to Place and Route for this purpose is ISE. The ISE software can either minimize area or increase frequency. Each model has its advantages and disadvantages depending on the demand. After running the software, start new project and add the project name and link it to your main file location. In the next window, select as a top level source the EDIF format (Electronic Design Interchange Format), figure 7-31. After that select the UCF file (User Constrain File) where the pins are defined, figure 7-33. <Path of the HDL- Project> / <Name of the HDL Library>/ / PS / Top_Sheet_Xilinx_Behave / Top_Sheet_Xilinx_Behave_imp1 /

93

Figure 7-32

Project Definition

Figure 7-33

UCF Definition

In Process Window where the User Constrain, the Assign Package Pins must be selected.

Figure 7-34

Part Selector

In this window, all the relevant settings of the programmed CPLD must be done so that the ISE software has all the needed settings to start place and route process. In the Design Object window, every input and output can be programmed and definite pin numbers can be named.

94

Figure 7-35

I/Os Definition

The main important settings for the pins are as follows: I/O Name: name of the input and output as declared in the entity Loc: Number of the pin I/O Std: Voltage amplitude Termination; End of the input pin Schmitt: if the input signal needs a Schmitt trigger or not.

The following table shows the complete pin definition of the dice project.
I / O Name push_button melody_select melody_enable tick_enable reset_n schmitt_in schmitt_out speaker speaker_not time_out a_f b_e c_d G I / O Direction Input Input Input Input Input Input Output Output Output Output Output Output Output Output Loc P66 P60 P59 P61 P99 P22 P15 P13 P9 P65 P93 P91 P90 P92 I / O Std. LVCMOS18 LVCMOS18 LVCMOS18 LVCMOS18 LVCMOS18 LVCMOS18 LVCMOS18 LVCMOS18 LVCMOS18 LVCMOS18 LVCMOS18 LVCMOS18 LVCMOS18 LVCMOS18 Termination FLOAT PULLUP PULLUP PULLUP PULLUP FLOAT Schmitt

ON

After assigning all these parameters, the UCF (User Constrain File) will be updated with all these parameters after saving the file. In Assign Package Pins Manager. The next step to define the parameters of place and route weather optimize for place and have smaller area or optimize for time and get higher clock frequency performance.

95

Figure 7-36

Fitting Definition

The Fitting parameters must also be defined, these parameters are found under the name Properties of Implement Design as shown in figure 7-36

Property Name Implementation Template Use Global Clock Use Global Output Enable Use Global Reset Unused I / O Pad Termination Mode Input and tristate I / O Termination Mode I / O Voltage Standard

Value Optimize Speed Disable Disable Disable PULLUP FLOAT LVCMOS18

By double clicking on Implement design, the Route process starts and the generate output file has an extension .JED which will be loaded later via JTAG interface on the CPLD. Next, the software iMPACT is used to program the CPLD. After launching it, a new project must be defined. To program the CPLD, the switch S6 on the emulator board must be enabled, this switch must be enabled only during programming, after that it must be disabled.

Figure 7-37

iMPACT User Interface

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The final step is to connect the programming device to the CPLD found on the board. Using the command Automatically connect to a cable and identify Boundary scan chain, a connection will be established via JTAG interface to the CPLD. After detection and connection, the name and the path of the .JED file must be provided (Xilinx_top_sheet.jed).

Figure 7-38

Xilinx Programmer

Finally right click on Xilinx icon and click on program, after few seconds test the dice program on the emulator board if it is running!

Figure 7-39

Schematic design of the emulator board

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Appendix A: The VHDL language

Language Elements
Example -- Comment at the end of line ENTITY inv IS Inverter abc, ABC, abc_1 8_bit_decoder 2, 00123, 250_000, 2E3 (Integer) 2.001, 16.34E3, 3_12.4E-12 (real) basis#int.int#exp, 2#101001,2#10.01#101 20 fs, 5.3e4 ms, 4 hr 'x', '2', ' ', '?' " text ", " hello " & " you ", " also " " quotes " " in the text " "11001100", b"11001100", x"CC", o"314" 3, 3.4E-2 (explicit operands) a, b (operand) b'HIGH, a'LOW (Attribute) a(1 TO 8) (Aggregate) integer'(worth) (Qualified printouts) functionsname(a) (Functions call) does not permit

Comment Operand Numeric values

a_, a__b, _a, reserved Words 2.0E3, 2E-3 2E3 17#123#, 2#12#

Characters Character strings Bit string (bit_vector) Operand

Object
Definition of own data types:
Type of enumerating TYPE enum_type_name IS (worth_1[,...wert_n]); TYPE bit IS ('0','1'); TYPE state IS (wait, st1, further);

Integral types TYPE int_type_name IS RANGE start TO end;

TYPE displayofdice IS RANGE 1 TO 6; TYPE displayofdice IS RANGE 6 DOWNTO 1; TYPE displayofdice IS RANGE notes'RANGE;

Floating point types TYPE real_type_name IS RANGE start TO end; Physical types TYPE phys_type_name IS RANGE start TO end UNITS fundamental unit; [height = value fundamental unit; ...] END UNITS; Sub types SUBTYPE subtype_name IS basetype_name 98

TYPE temperature IS RANGE -273.15 TO 1.0E6;

TYPE time IS RANGE 1 TO 1E12 UNITS fs; ps=1000 fs; ns=1000 ps; END UNITS;

SUBTYPE winner number IS dice number

[RANGE start TO end];

RANGE 4 TO 6;

Type transformations:
real -> integer INTEGER(real_value) Integer -> real REAL(integer_value) i:=integer(r);

r:=real(i);

Field types:
Linear fields (vectors) TYPE array_name IS ARRAY (index_type RANGE <>) TYPE data IS ARRAY (0 TO 255) OF integer; OF basetype_name; TYPE gewuerfelt IS ARRAY (NATURAL RANGE <>) OF dicedisplay; Multidimensional fields TYPE array_name IS ARRAY (index_type RANGE <> [,index_type2 ...]) OF basetype_name; Derived fields SUBTYPE subtype_name IS basetype_name (start to end [, index2...]);

TYPE matrix IS ARRAY (0 TO 7, 0 TO 7) OF integer;

SUBTYPE firstname IS string (1 TO 20); SUBTYPE word IS bit_vector (1 TO 16);

Access to fields:
Reading i:=matrix(1,2); i:=matrix(1)(2); i_vector:=matrix(1)(2 TO 5); adrhighbus:=adrbus(8 TO 15); Writing matrix(1,2):=1; matrix(1):=(1,2,3,4,5,6,7,8); matrix(1)(1 TO 5):= (1 | 5 => 3, OTHERS => 0); (3,0,0,0,3)

Records:
Record TYPE record_name IS RECORD name1:typ1; [name2:typ2;...] END RECORD [record_name]; TYPE date IS RECORD Day:integer; Month:integer; Year:integer; Weekdays:string; END RECORD;

Access to record entry:

Reading i:=today.day; today2:=today; Writing today:=(27,04,01,Friday); today.day:=27; today :=(day => 27, month => 04, year => 01, weekday => MO);

99

Object declaration:
Constant one (only once allocable) CONSTANT name[,name2...]:type_name:=value; CONSTANT day: INTEGER :=31;

Variable (several times allocatable, only current value readably) VARIABLE name[,name2]:type_name [:=default_value]; VARIABLE a:INTEGER; (only within PROCESS and FUNCTION/PROCEDURE VARIABLE b,c: REAL:=2.22; definable) Signal (several times allocatable, it is possible to access previous values) SIGNAL name[,name2]:type_name[:=default_worth]; SIGNAL input: BIT:=1; (within ENTITY, ARCHITECTURE, PACKAGE and SIGNAL ab: bit_vector (0 TO 15); BLOCK definable) Alias (object with other names, ev. others type possible) ALIAS name: alias_type IS alias_object; ALIAS abhigh : bit_vector (0 TO 7) IS ab (8 TO 15); ALIAS adr: bit_vector(15 TO 0) IS ab; Attribute Name'attr_name['attr_name2...]

i:=displayofdice'HIGH;

Variable ones of FOR loops do not have to be defined. In order to define a variable as global, SHARED can be placed in front. Ex.: SHARED VARIABLE i:INTEGER;

Structure
Library
The designators of Package, Entity and Configuration must be unique. The designators for the Architectures must be unique within the Entity. Merge a LIBRARY LIBRARY lib_name1[,libname2 ...]; Use from components of a LIBRARY USE libname.package_name.element_name[, ...];

LIBRARY IEEE;

USE libname.package_name.ALL;

The instruction can be before Entity, Architecture, Configuration, Package or Package Body. According to standard the LIBRARY are work and std merged. Its all items of the Package " hr. standard " are well-known.

Entity
An Entity consists of four basic blocks: GENERIC block statement Defining the parameters, which are transferred to the model and influence on the behaviour. These parameters are visible from the outside. PORT block statement: Defining the link pins (name, data type and signal direction). Declaration section: Here new types, constant, signals, subroutines etc. can be declared or defined. These are valid for the Entity and thus for all with their connected Architectures. Statement part:

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In this section after BEGIN " passive " operations can be located. It means that the output variables cannot be influenced. This section can be used e.g. in order to check the input variables on irregular combinations.

ENTITY ENTITY entity_name IS [GENERIC (param_1[,..., param_n]: type_name[:=default_value] [; ...]);] [PORT (port_1[,...,port_n]: mode type_name[:=default_value] [; ...]);] [Declaration] [BEGIN Statements (passive)] END [ENTITY] [entity_name]; Param_x: port_x: Mode: Parameter name, which is accessible from the outside and influence on the Architecture. Port name: Designation of a link pin Mode of the port: IN: Input: only read OUT: Output: only write INOUT: Bi-directional Port: read and write BUFFER: Bi-directional Port: read and write (Writing from a source) Signaltype (variabletype) Worth, which is assumed for the parameter or port, if this is not defined or not attached keep it openly.

type_name: default_value:

Possible signal types for the parameters or port after IEEE

Boolean Bit Integer Real Character Time std_ulogic std_ulogic_vector std_logic std_logic_vector true, false 0, 1 -2147483648...+2147483647 -1E308...+1E308 ASCII- Characters worth fs,ns,ms,... Logical type, the 0,1,Z,U,X,W,L,H, - to assume (unresolved) Vector of std_ulogic (busstructure) Logical type, which 0,1,Z,U,X,W,L,H, - can be assumed Vector of std_logic (Busstructure)

Example
ENTITY rs_flip_flop IS PORT ( r,s: IN std_ulogic; q,q_n: OUT std_ulogic); BEGIN ASSERT ((r /='1') OR (s /='1')) REPORT " Bad input combination " SEVERITY warning; END ENTITY rs_flip_flop; ENTITY rom_8kb IS GENERIC ( data_delay: PORT ( adr: data: rd: cs: TYPE tristate IS ('0', '1', 'Z'); END ENTITY rs_flip_flop; ENTITY ram IS 101 TIME:= 10 ns); IN std_ulogic_vector(12 DOWNTO 0); OUT std_logic_vector(7 DOWNTO 0); IN std_ulogic; IN std_ulogic := 1);

GENERIC ( read_delay: write_delay: bitbreite: PORT ( adr: data: rd: wr: cs: END ENTITY rs_flip_flop;

TIME:= 10 ns; TIME:= 10 ns; INTEGER); IN std_ulogic_vector(bitbreite-1 DOWNTO 0); INOUT std_ulogic_vector(7 DOWNTO 0); IN std_ulogic; IN std_ulogic; IN std_ulogic := 1);

Architecure
A Architecture consists of two basic blocks: Declaration section: Here types, constant, signals, subroutines etc. can be declared or defined. in the statement part after BEGIN are the instruction or process, which describe the behavior or the structure of the component. ARCHITECTURE ARCHITECTURE architecture_name OF entity_name IS [Definitions] BEGIN Instruction (processes) to the modelling END [ARCHITECTURE] [architecture_name]; Basically one differentiates between concurrent statements and sequential statements. Sequential statements can be specified only with in the processes. Concurrent statements (quasi parallel finished) <= (as signal allocation) ASSERT BLOCK GENERATE PROCESS Prozeduraufruf component instantion Sequential statements (successively finished) <= (as signal allocation) := ASSERT CASE EXIT IF LOOP NEXT NULL REPORT RETURN WAIT Prozeduraufruf

Configuration
Configuration data of a VHDL model: to use Architecture to use library for a Sub module (during structural description) application (wiring) of the Sub module (during structural description) parameter (generics) of the Sub module (during structural description) CONFIGURATION CONFIGURATION configuration_name OF entity_name IS USE/ Attribute allocations Configuration statements END [CONFIGURATION] [configuration_name];

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Packages
Packages are libraries, which are completed over the LIBRARY statement for the VHDL SOURCE code. In the Package it can be defined: Data types, components, objects etc.. Package contains only the declarations. In the Package Body it has the definitions and functionality. If only Package Body is modified, component, which uses the LIBRARY, must not again be compiled. The package body always has the same name as its corresponding package declaration.

PACKAGE PACKAGE package_name IS Declaration of Type, Subtype, Aliases, constant, ... Subroutines, components, Attribute,... END [PACKAGE] [package_name]; PACKAGE BODY PACKAGE BODY package_name IS [local Declaration of Type, Subtype, Aliases, constant, ...] Definition of Subroutines,... END [PACKAGE BODY] [package_name];

Behavioural Modelling
Operation
Logical operations: NOT AND OR XOR NAND NOR XNOR Comparison operations: = /= < <= > >= Arithmetic operations: + & * / MOD REM ** ABS Shift and Rotate: SLL SRL SLA a:=NOT(b); a:=b AND c AND d; a:=b OR c OR d; a:=b XOR c XOR d; a:=b NAND c; a:=b NOR c; a:=b XNOR c;

(only 2 operands admissible!) (only 2 operands admissible!) (only 2 operands admissible!) Type of result is boolean! Equal Unequal Smaller Smaller equal Greater Greater equal

IF a=b THEN

a:=b+c; a:=b-c; a:=b & c; a:= b * c; a:= b / c; a:= b MOD c; a:= b REM c; a:= b ** 2; a:=ABS(b);

Addition Subtraction Tie together Multiplication Division Modulo (Remainder, sign of c) Remainder (Remainder, sign of b) High, Potenzieren Amount

in the examples around c bit is shifted a:=b SLL c; Shift logic left a:=b SLL c; Shift logic right a:=b SLL c; Shift arithmetic left 103

SRA ROL ROR

a:=b SLL c; a:=b SLL c; a:=b SLL c;

Shift arithmetic right Rotate left Rotate right

Attribute:
Attributes (type-referred): are behind type BASE LEFT RIGHT HIGH LOW POS() VAL() SUCC() PRED() LEFTOF() RIGHTOF() ASCENDING IMAGE() VALUE() Attributes (field-related): are behind type, constant or variable LEFT [()] RIGHT [()] LOW [()] HIGH [()] LENGTH [()] RANGE [()] REVERSE_RANGE [()] ASCENDING [()] TYPE t1 IS ARRAY (1 TO 8) OF INTEGER; TYPE t2 IS ARRAY (8 TO 1) OF INTEGER; TYPE t3 IS (red, blue, green); t1BASE--INTEGER supplies type of base t1LEFT -- 1 Left boundary t2LEFT -- 8 t1RIGHT -- 8 Right boundary t2RIGHT -- 1 t1HIGH -- 8 Upper boundary t2HIGH -- 8 t1LOW -- 1 Under boundary t2LOW -- 1 t3POS(rot) -- 0 Position (index) of the item t3POS(gelb) -- 2 t3VAL(1) -- blue Worth the item on index t1SUCC(4) -- 5 Following index t2SUCC(4) -- 5 t1PRED(4) -- 3 previous index t2PRED(4) -- 3 t1LEFTOF(4) -- 3 Index around 1 to the left t2LEFTOF(4) -- 5 t1RIGHTOF(4) -- 5 Index around 1 to the right t2RIGHTOF(4) -- 3 t1ASCENDING --true TRUE, with rising edge t2ASCENDING -- false t3IMAGE(0) -- rot Converts value of the item in string t3VALUE(rot) -- rot Converts string in value type t IS ARRAY 1 TO 8,7 DOWNTO 0 OF INTEGER; VARIABLE a:t; aLEFT (1) --1 aRIGHT (2) --0 aLOW (1) --1 aHIGH (2) --7 aLENGTH (2) --8 aRANGE (1) --1 TO 8 aREVERSE_RANGE (2) --0 TO 7 aASCENDING (1)--true aASCENDING (2)-- false Left boundary Right boundary Under boundary Upper boundary Length size Length length in reverse order TRUE, during rising edges

Attributes (signal-referred): DELAYED [(time)] STABLE [(time)] QUIET [(zeit)] TRANSACTION EVENT ACTIVE 104

at time delays TRUE, if signal was in the time without event FALSE, if it was in the time of active changes each time, if signal is active (of the type BIT) TRUE, if the signal occurs at the event TRUE, if signal is active

LAST_EVENT LAST_ACTIVE LAST_VALUE DRIVING DRIVING_VALUE Attributes (block-referred): BEHAVIOR STRUCTURE

Time up to the last event of the signal Time when the signal was active last the last value of the event (last change) TRUE, if driver of the signal is switched on the driver for the signal

TRUE, if block or Architecture is a pure description of behaviour TRUE, if block or Architecture is a pure structure description

Attribute (allgemein): SIMPLE_NAME PATH_NAME INSTANCE_NAME

Name of the unit Path of the unit within the model like PATH_NAME with info. over configuration

A4.3 Concurrent statements

Signal
Signal allocation [label:] signal_name <= [TRANSPORT] signal_wert1 [AFTER time1] [, signal_wert2 AFTER time2, ...]; Caused signal allocation with WHEN ELSE [label:] signal_name <= [TRANSPORT] signal_wert1 [AFTER time1] [, signal_wert2 AFTER timet2, ...] WHEN condition [ELSE signal_wert3 [AFTER time3] [, signal_wert4 AFTER time4, ...]] [ELSE ...];

a <= 1; a <= 1, 0 AFTER 2 ns;

a <= TRANSPORT 1 WHEN input=0 ELSE 0 AFTER 2 ns WHEN input=1 ELSE X;

Condition signal allocation with WHEN Caused signal allocation with WHEN [label:] WITH printout SELECT WITH input SELECT signal_name <= [TRANSPORT] signal_wert1 [AFTER a <= TRANSPORT 1 WHEN 0, time1] [, signal_wert2 AFTER time2, ...] WHEN wert1 [, 0 AFTER 2 ns WHEN 1, signal_wert3 [AFTER time3] [, signal_wert4 AFTER X WHEN OTHERS; time4, ...]] WHEN wert2, [signal_wert5 [AFTER time5] [, signal_wert6 AFTER time6, ...] WHEN OTHERS]; UNAFFECTED signal allocation (signal remains in its past status) [label:] signal_name <= UNAFFECTED; Advantage: no unnecessary activation of the signal a <= UNAFFECTED;

Assertions:
ASSERT [label:] ASSERT condition [REPORT Message] [SEVERITY severity_level];

ASSERT error-variable /=TRUE REPORT Error occurred SEVERITY error;

Checks a condition and outputs a warning or an error message, if the condition is not fulfilled. As severity_level is possible: note, warning, error, failure. Default-moderately, i.e. if SEVERITY is not indicated, error is assumed.
105

Process:
Process serves as environment for sequential instruction. The instruction PROCESS is considered however it is concurrent. PROCESS with sensitive signals in the heading [label:] PROCESS (signal_1 [,signal_2, ...]) [IS] Declaration BEGIN Sequential Statements (except WAIT) END PROCESS [label]; PROCESS with WAIT statement [label:] PROCESS [IS] Declaration BEGIN Sequential statement WAIT instruction with condition for continuation of sequential statements END PROCESS [label];

output: PROCESS(d, clk) BEGIN IF clk=1 THEN q<=d; END IF; END PROCESS output;

output: PROCESS BEGIN IF clk=1 THEN q<=d; END IF; WAIT ON d, clk; END PROCESS output;

Sequential statements:
Signal:
Signal allocation [label:] signal_name <= [TRANSPORT] signal_wert1 [AFTER time1] [, signal_wert2 AFTER time2, ...];

a <= 1; a <= 1, 0 AFTER 2 ns;

Conditioned signal allocation is not permitted during sequential signal allocation. This must be generated over IF and CASE statements accordingly. Variable:
Variable allocation [label:] var_name:=value;

a := 1;

Assertions:
Checks a condition and outputs a warning or an error message, if the condition is not fulfilled.

ASSERT [label:] ASSERT condition [REPORT message] [SEVERITY severity_level]; REPORT [label] REPORT message [SEVERITY severity_level];

ASSERT error-variable/=TRUE REPORT error message SEVERITY error;

REPORT Abort SEVERITY failure;

As severity_level is possible: note, warning, error, failure. Default-moderately, i.e. if SEVERITY is not indicated, with ASSERT error is assumed, with REPORT note.

Wait:
The WAIT statement ensures for the fact that one waits elapsed until an event at a signal occurs (ON), until a condition is fulfilled (UNTIL) or to the time (FOR). If ON and UNTIL are indicated, then an event

106

must have occurred and the condition to be fulfilled. If FOR is indicated, max. one waits until the time ran.

WAIT [label] WAIT [ON signal_1 [, signal_2, ...]] [UNTIL condition] [FOR time];

WAIT ON clk, input; WAIT UNTIL a=0 FOR 100 ns;

IF-THEN:
IF-THEN [label] IF condition_1 THEN sequential statement ELSIF condition_2 THEN Sequential statement [ELSIF ...]] [ELSE sequential statement] END IF [label];

IF a=0 THEN b:=1; ELSIF a=1 THEN b:=2; ELSE b:=0; END IF;

CASE:
IF-THEN [label] CASE printout IS WHEN wert_1 => sequential statement [WHEN wert_2 => ...] [WHEN OTHERS => ...] END CASE [label];

CASE a IS WHEN 0 => b:=1; WHEN 1 => b:=2; WHEN OTHERS => b:=0; END CASE;

NULL:
No internal message executes. Serves for the explicit indication in IF and CASE STATEMENTS. CASE a IS WHEN 0 => b:=1; WHEN 1 => NULL; WHEN OTHERS => b:=0; END CASE;

LOOP:
FOR-LOOP [label] FOR count-variable IN length LOOP sequential statement END LOOP [label]; The counting variable does not need to be defined. FOR i IN 1 TO 6 LOOP a(i):=b(i); END LOOP;

WHILE-LOOP Executes the statements, as long as the condition is fulfilled [label] WHILE condition LOOP WHILE a<b LOOP sequential statement a:=a+1; END LOOP [label]; END LOOP; LOOP Continuous loop [label] LOOP 107

LOOP

sequential statement END LOOP [label];

a <= b; END LOOP;

NEXT Branch prematurely at the beginning of the next cycle run (if the condition is fulfilled). NEXT [label] [WHEN condition]; EXIT Leave the loop prematurely (if the condition is fulfilled). EXIT [label] [WHEN condition]; FOR i IN 1 TO 6 LOOP NEXT WHEN b(i)=Z; EXIT WHEN b(i)=X; a(i):=b(i); END LOOP;

Subroutines:
Argument modes Argument class Return values Function IN CONSTANT, SIGNAL always one Procedure IN, OUT, INOUT CONSTANT, SIGNAL, VARIABLE arbitrary

Function: Default for the argument class is CONSTANT, for the argument mode IN. The declaration of the function is optional. If the function is to be contained in a Package, then the declaration should in the Package and the definition in the Package Body to be placed. If for the call the argument value is not indicated, then the default value from the function definition is used. According to standard a function is determined as PURE ONES. PURE ONE is called, which only local of objects can be accessed. IMPURE functions can access against it global variable.

Declaration FUNCTION functionsname [([Argumentclass] Argumentname1 [,Argumentname2] [IN] Argumenttype [:=defaultvalue] [; ...] )] RETURN type of result; Definition FUNCTION functionsname [([Argumentclass] Argumentname1 [,Argumentname2] [IN] Argumenttype [:=defaultvalue] [; ...] )] RETURN type of result IS BEGIN Sequential statement (without WAIT) RETURN result-value; END [FUNCTION] [functionsname]; Call Functionsname [(Argumentwert1 [,Argumentwert2 ,...])]; Functionsname [(Argumentname1 => Argumentwert1 [,Argumentname2 => Argumentwert2 ,...] )];

FUNCTION bit_to_integer (bit_a: BIT) RETURN integer;

FUNCTION bit_to_integer (bit_a: BIT) RETURN integer IS BEGIN IF bit_a=1 THEN RETURN 1; ELSE RETURN 0; END IF; END bit_to_integer;

i:=bit_to_integer(0); i:=bit_to_integer(bit_a => 0);

impure functions function, which can access global variables. [PURE] FUNCTION functionsname ... IS IMPURE FUNCTION functionsname ... IS

Procedures:

108

Default for the argument mode is IN. For the argument class the default value is CONSTANT with the mode IN, or VARIABLE with the mode OUT or INOUT. A concurrent procedure is called if at least one of the arguments of the mode changes to INOUT IN or (corresponds to sensitivity cunning of processes).

Declaration PROCEDURE procedurename [([Argumentclass] Argumentname1 [,Argumentname2] [Argumentmodus] Argumenttype [:=defaultvalue] [; ...] )]; Definition PROCEDURE procedurename [([Argumentclass] Argumentname1 [,Argumentname2] [Argumentmodus] Argumenttype [:=defaultvalue] [; ...] )] IS BEGIN Sequential statement [RETURN;] END [PROCEDURE] [procedurename]; Call Procedurename [(Argumentvalue1 [,Argumentvalue2 ,...])]; Procedurename [(Argumentname1 => Argumentvalue1 [,Argumentname2 => Argumentvalue2 ,...] )];

PROCEDURE bit_to_integer (bit_a: IN BIT; i: OUT integer);

PROCEDURE bit_to_integer (bit_a: IN BIT; i: OUT integer) IS BEGIN IF bit_a=1 THEN i:=1; ELSE i:=0; END IF; END bit_to_integer;

bit_to_integer(0, j); bit_to_integer(bit_a => 0, i => j);

109

Appendix B: Packages

IEEE.numeric_bit
(see /Vhdl_src/ieee/numbit.vhd)

B1.1 Type: UNSIGNED SIGNED B1.2 Arithmatic: ABS -

type UNSIGNED is array (NATURAL range <> ) of BIT; type SIGNED is array (NATURAL range <> ) of BIT;

Bit vector without signs Bit vector with signs

function "abs" (ARG: SIGNED) return SIGNED; function "-" (ARG: SIGNED) return SIGNED; function "-" (L, R: UNSIGNED) return UNSIGNED; function "-" (L, R: SIGNED) return SIGNED; function "-" (L: UNSIGNED; R: NATURAL) return UNSIGNED; function "-" (L: NATURAL; R: UNSIGNED) return UNSIGNED; function "-" (L: SIGNED; R: INTEGER) return SIGNED; function "-" (L: INTEGER; R: SIGNED) return SIGNED; function "+" (L, R: UNSIGNED) return UNSIGNED; function "+" (L, R: SIGNED) return SIGNED; function "+" (L: UNSIGNED; R: NATURAL) return UNSIGNED; function "+" (L: NATURAL; R: UNSIGNED) return UNSIGNED; function "+" (L: INTEGER; R: SIGNED) return SIGNED; function "+" (L: SIGNED; R: INTEGER) return SIGNED;

Amount Subtraction

Addition

110

Rem

Mod

function "*" (L, R: UNSIGNED) return UNSIGNED; function "*" (L, R: SIGNED) return SIGNED; function "*" (L: UNSIGNED; R: NATURAL) return UNSIGNED; function "*" (L: NATURAL; R: UNSIGNED) return UNSIGNED; function "*" (L: SIGNED; R: INTEGER) return SIGNED; function "*" (L: INTEGER; R: SIGNED) return SIGNED; function "/" (L, R: UNSIGNED) return UNSIGNED; function "/" (L, R: SIGNED) return SIGNED; function "/" (L: UNSIGNED; R: NATURAL) return UNSIGNED; function "/" (L: NATURAL; R: UNSIGNED) return UNSIGNED; function "/" (L: SIGNED; R: INTEGER) return SIGNED; function "/" (L: INTEGER; R: SIGNED) return SIGNED; function "rem" (L, R: UNSIGNED) return UNSIGNED; function "rem" (L, R: SIGNED) return SIGNED; function "rem" (L: UNSIGNED; R: NATURAL) return UNSIGNED; function "rem" (L: NATURAL; R: UNSIGNED) return UNSIGNED; function "rem" (L: SIGNED; R: INTEGER) return SIGNED; function "rem" (L: INTEGER; R: SIGNED) return SIGNED; function "mod" (L, R: UNSIGNED) return UNSIGNED; function "mod" (L, R: SIGNED) return SIGNED; function "mod" (L: UNSIGNED; R: NATURAL) return UNSIGNED; function "mod" (L: NATURAL; R: UNSIGNED) return UNSIGNED; function "mod" (L: SIGNED; R: INTEGER) return SIGNED; function "mod" (L: INTEGER; R: SIGNED) return SIGNED;

Multiplication

Divide (Error, if 2. divide by 0)

Rest (Error, if 2. Divide by 0)

Modulo (Error, if 2. Divide by 0)

B1.3 Comparision: >

<

function ">" (L, R: UNSIGNED) return BOOLEAN; function ">" (L, R: SIGNED) return BOOLEAN; function ">" (L: NATURAL; R: UNSIGNED) return BOOLEAN; function ">" (L: INTEGER; R: SIGNED) return BOOLEAN; function ">" (L: UNSIGNED; R: NATURAL) return BOOLEAN; function ">" (L: SIGNED; R: INTEGER) return BOOLEAN; function "<" (L, R: UNSIGNED) return BOOLEAN; function "<" (L, R: SIGNED) return BOOLEAN; function "<" (L: NATURAL; R: UNSIGNED) return BOOLEAN; function "<" (L: INTEGER; R: SIGNED) return BOOLEAN; function "<" (L: UNSIGNED; R: NATURAL) return BOOLEAN; function "<" (L: SIGNED; R: INTEGER) return BOOLEAN;

Greater

Smaller

111

<=

>=

/=

function "<=" (L, R: UNSIGNED) return BOOLEAN; function "<=" (L, R: SIGNED) return BOOLEAN; function "<=" (L: NATURAL; R: UNSIGNED) return BOOLEAN; function "<=" (L: INTEGER; R: SIGNED) return BOOLEAN; function "<=" (L: UNSIGNED; R: NATURAL) return BOOLEAN; function ">=" (L, R: UNSIGNED) return BOOLEAN; function ">=" (L, R: SIGNED) return BOOLEAN; function ">=" (L: NATURAL; R: UNSIGNED) return BOOLEAN; function ">=" (L: SIGNED; R: INTEGER) return BOOLEAN; function "=" (L, R: UNSIGNED) return BOOLEAN; function "=" (L, R: SIGNED) return BOOLEAN; function "=" (L: NATURAL; R: UNSIGNED) return BOOLEAN; function "=" (L: INTEGER; R: SIGNED) return BOOLEAN; function "=" (L: UNSIGNED; R: NATURAL) return BOOLEAN; function "=" (L: SIGNED; R: INTEGER) return BOOLEAN; function "/=" (L, R: UNSIGNED) return BOOLEAN; function "/=" (L, R: SIGNED) return BOOLEAN; function "/=" (L: NATURAL; R: UNSIGNED) return BOOLEAN; function "/=" (L: INTEGER; R: SIGNED) return BOOLEAN; function "/=" (L: UNSIGNED; R: NATURAL) return BOOLEAN; function "/=" (L: SIGNED; R: INTEGER) return BOOLEAN;

smaller or equal

Greater or equal

Equal

Unequal

B1.4 Shifting and rotating: SHIFT_LEFT SHIFT_RIGHT ROTATE_LEFT ROTATE_RIGHT Sll Srl Rol

function SHIFT_LEFT (ARG: UNSIGNED; COUNT: NATURAL) return UNSIGNED; function SHIFT_LEFT (ARG: SIGNED; COUNT: NATURAL) return SIGNED; function SHIFT_RIGHT (ARG: UNSIGNED; COUNT: NATURAL) return UNSIGNED; function SHIFT_RIGHT (ARG: SIGNED; COUNT: NATURAL) return SIGNED; function ROTATE_LEFT (ARG: UNSIGNED; COUNT: NATURAL) return UNSIGNED; function ROTATE_LEFT (ARG: SIGNED; COUNT: NATURAL) return SIGNED; function ROTATE_RIGHT (ARG: UNSIGNED; COUNT: NATURAL) return UNSIGNED; function ROTATE_RIGHT (ARG: SIGNED; COUNT: NATURAL) return SIGNED; function "sll" (ARG: UNSIGNED; COUNT: INTEGER) return UNSIGNED; function "sll" (ARG: SIGNED; COUNT: INTEGER) return SIGNED; function "srl" (ARG: UNSIGNED; COUNT: INTEGER) return UNSIGNED; function "srl" (ARG: SIGNED; COUNT: INTEGER) return SIGNED; function "rol" (ARG: UNSIGNED; COUNT: INTEGER) return UNSIGNED; function "rol" (ARG: SIGNED; COUNT: INTEGER) return SIGNED;

Shift left Shift right Rotate left Rotate right Shift left (Not VHDL 1076-1987 compatibly) Shift right (Not VHDL 1076-1987 compatibly) Rotate left (Not VHDL 1076-1987 compatibly)

112

Ror

function "ror" (ARG: UNSIGNED; COUNT: INTEGER) return UNSIGNED; function "ror" (ARG: SIGNED; COUNT: INTEGER) return SIGNED;

Rotate right (Not VHDL 1076-1987 compatibly)

B1.5 Size modify: RESIZE

function RESIZE (ARG: SIGNED; NEW_SIZE: NATURAL) return SIGNED; function RESIZE (ARG: UNSIGNED; NEW_SIZE: NATURAL) return UNSIGNED;

Those modifies width of the bit vector

B1.6 Conversion: TO_INTEGER TO_UNSIGNED TO_SIGNED B1.7 Logic: Not And Or Nand Nor Xor Xnor

function TO_INTEGER (ARG: UNSIGNED) return NATURAL; function TO_INTEGER (ARG: SIGNED) return INTEGER; function TO_UNSIGNED (ARG, SIZE: NATURAL) return UNSIGNED; function TO_SIGNED (ARG: INTEGER; SIZE: NATURAL) return SIGNED;

Converts the bit vector in a Integer Converts number into a bit vector (without signs) Converts number into a bit vector (with signs)

function "not" (L: UNSIGNED) return UNSIGNED; function "not" (L: SIGNED) return SIGNED; function "and" (L, R: UNSIGNED) return UNSIGNED; function "and" (L, R: SIGNED) return SIGNED; function "or" (L, R: UNSIGNED) return UNSIGNED; function "or" (L, R: SIGNED) return SIGNED; function "nand" (L, R: UNSIGNED) return UNSIGNED; function "nand" (L, R: SIGNED) return SIGNED; function "nor" (L, R: UNSIGNED) return UNSIGNED; function "nor" (L, R: SIGNED) return SIGNED; function "xor" (L, R: UNSIGNED) return UNSIGNED; function "xor" (L, R: SIGNED) return SIGNED; function "xnor" (L, R: UNSIGNED) return UNSIGNED; function "xnor" (L, R: SIGNED) return SIGNED;

NOT AND OR NAND NOR XOR (Exclusives OR) XNOR (Not VHDL 1076-1987 compatibly)

B1.8 Edge identification: RISING_EDGE function RISING_EDGE (signal S: BIT) return BOOLEAN; FALLING_EDGE function FALLING_EDGE (signal S: BIT) return BOOLEAN;

TRUE, if signal change from 0 to 1 occurred TRUE, if signal change from 1 to 0 occurred

113

IEEE.numeric_std
(see /Vhdl_src/ieee/numstd.vhd)

B2.1 Type: UNSIGNED SIGNED B2.2 Arithmetic: ABS -

type UNSIGNED is array (NATURAL range <>) of STD_LOGIC; type SIGNED is array (NATURAL range <>) of STD_LOGIC;

Bit vector without signs Bit vector with signs

function "abs" (ARG: SIGNED) return SIGNED; function "-" (ARG: SIGNED) return SIGNED; function "-" (L, R: UNSIGNED) return UNSIGNED; function "-" (L, R: SIGNED) return SIGNED; function "-" (L: UNSIGNED;R: NATURAL) return UNSIGNED; function "-" (L: NATURAL; R: UNSIGNED) return UNSIGNED; function "-" (L: SIGNED; R: INTEGER) return SIGNED; function "-" (L: INTEGER; R: SIGNED) return SIGNED; function "+" (L, R: UNSIGNED) return UNSIGNED; function "+" (L, R: SIGNED) return SIGNED; function "+" (L: UNSIGNED; R: NATURAL) return UNSIGNED; function "+" (L: NATURAL; R: UNSIGNED) return UNSIGNED; function "+" (L: INTEGER; R: SIGNED) return SIGNED; function "+" (L: SIGNED; R: INTEGER) return SIGNED; function "*" (L, R: UNSIGNED) return UNSIGNED; function "*" (L, R: SIGNED) return SIGNED; function "*" (L: UNSIGNED; R: NATURAL) return UNSIGNED; function "*" (L: NATURAL; R: UNSIGNED) return UNSIGNED; function "*" (L: SIGNED; R: INTEGER) return SIGNED; function "*" (L: INTEGER; R: SIGNED) return SIGNED; function "/" (L, R: UNSIGNED) return UNSIGNED; function "/" (L, R: SIGNED) return SIGNED; function "/" (L: UNSIGNED; R: NATURAL) return UNSIGNED; function "/" (L: NATURAL; R: UNSIGNED) return UNSIGNED; function "/" (L: SIGNED; R: INTEGER) return SIGNED; function "/" (L: INTEGER; R: SIGNED) return SIGNED;

Amount Subtraction

Addition

Multiplication

Dividie (Error, if 2. Divide by 0)

114

Rem

Mod

function "rem" (L, R: UNSIGNED) return UNSIGNED; function "rem" (L, R: SIGNED) return SIGNED; function "rem" (L: UNSIGNED; R: NATURAL) return UNSIGNED; function "rem" (L: NATURAL; R: UNSIGNED) return UNSIGNED; function "rem" (L: SIGNED; R: INTEGER) return SIGNED; function "rem" (L: INTEGER; R: SIGNED) return SIGNED; function "mod" (L, R: UNSIGNED) return UNSIGNED; function "mod" (L, R: SIGNED) return SIGNED; function "mod" (L: UNSIGNED; R: NATURAL) return UNSIGNED; function "mod" (L: NATURAL; R: UNSIGNED) return UNSIGNED; function "mod" (L: SIGNED; R: INTEGER) return SIGNED; function "mod" (L: INTEGER; R: SIGNED) return SIGNED;

Rest? (Error, if 2. Divide by 0)

Modulo (Error, if 2. Divide by 0)

B2.3 Comparison: >

<

<=

>=

function ">" (L, R: UNSIGNED) return BOOLEAN; function ">" (L, R: SIGNED) return BOOLEAN; function ">" (L: NATURAL; R: UNSIGNED) return BOOLEAN; function ">" (L: INTEGER; R: SIGNED) return BOOLEAN; function ">" (L: UNSIGNED; R: NATURAL) return BOOLEAN; function ">" (L: SIGNED; R: INTEGER) return BOOLEAN; function "<" (L, R: UNSIGNED) return BOOLEAN; function "<" (L, R: SIGNED) return BOOLEAN; function "<" (L: NATURAL; R: UNSIGNED) return BOOLEAN; function "<" (L: INTEGER; R: SIGNED) return BOOLEAN; function "<" (L: UNSIGNED; R: NATURAL) return BOOLEAN; function "<" (L: SIGNED; R: INTEGER) return BOOLEAN; function "<=" (L, R: UNSIGNED) return BOOLEAN; function "<=" (L, R: SIGNED) return BOOLEAN; function "<=" (L: NATURAL; R: UNSIGNED) return BOOLEAN; function "<=" (L: INTEGER; R: SIGNED) return BOOLEAN; function "<=" (L: UNSIGNED; R: NATURAL) return BOOLEAN; function "<=" (L: SIGNED; R: INTEGER) return BOOLEAN; function ">=" (L, R: UNSIGNED) return BOOLEAN; function ">=" (L, R: SIGNED) return BOOLEAN; function ">=" (L: NATURAL; R: UNSIGNED) return BOOLEAN; function ">=" (L: INTEGER; R: SIGNED) return BOOLEAN; function ">=" (L: UNSIGNED; R: NATURAL) return BOOLEAN; function ">=" (L: SIGNED; R: INTEGER) return BOOLEAN;

Greater

Smaller

Smaller or equal

Greater or equal

115

/=

function "=" (L, R: UNSIGNED) return BOOLEAN; function "=" (L, R: SIGNED) return BOOLEAN; function "=" (L: NATURAL; R: UNSIGNED) return BOOLEAN; function "=" (L: INTEGER; R: SIGNED) return BOOLEAN; function "=" (L: UNSIGNED; R: NATURAL) return BOOLEAN; function "=" (L: SIGNED; R: INTEGER) return BOOLEAN; function "/=" (L, R: UNSIGNED) return BOOLEAN; function "/=" (L, R: SIGNED) return BOOLEAN; function "/=" (L: NATURAL; R: UNSIGNED) return BOOLEAN; function "/=" (L: INTEGER; R: SIGNED) return BOOLEAN; function "/=" (L: UNSIGNED; R: NATURAL) return BOOLEAN; function "/=" (L: SIGNED; R: INTEGER) return BOOLEAN;

Equal

Unequal

B2.4 Shifting and rotating: SHIFT_LEFT SHIFT_RIGHT ROTATE_LEFT ROTATE_RIGHT Sll Srl Rol Ror

function SHIFT_LEFT (ARG: UNSIGNED; COUNT: NATURAL) return UNSIGNED; function SHIFT_LEFT (ARG: SIGNED; COUNT: NATURAL) return SIGNED; function SHIFT_RIGHT (ARG: UNSIGNED; COUNT: NATURAL) return UNSIGNED; function SHIFT_RIGHT (ARG: SIGNED; COUNT: NATURAL) return SIGNED; function ROTATE_LEFT (ARG: UNSIGNED; COUNT: NATURAL) return UNSIGNED; function ROTATE_LEFT (ARG: SIGNED; COUNT: NATURAL) return SIGNED; function ROTATE_RIGHT (ARG: UNSIGNED; COUNT: NATURAL) return UNSIGNED; function ROTATE_RIGHT (ARG: SIGNED; COUNT: NATURAL) return SIGNED; function "sll" (ARG: UNSIGNED; COUNT: INTEGER) return UNSIGNED; function "sll" (ARG: SIGNED; COUNT: INTEGER) return SIGNED; function "srl" (ARG: UNSIGNED; COUNT: INTEGER) return UNSIGNED; function "srl" (ARG: SIGNED; COUNT: INTEGER) return SIGNED; function "rol" (ARG: UNSIGNED; COUNT: INTEGER) return UNSIGNED; function "rol" (ARG: SIGNED; COUNT: INTEGER) return SIGNED; function "ror" (ARG: UNSIGNED; COUNT: INTEGER) return UNSIGNED; function "ror" (ARG: SIGNED; COUNT: INTEGER) return SIGNED;

Shift left Shift right Rotate left Rotate right Shift left (Not VHDL 1076-1987 compatibly) Shift right (Not VHDL 1076-1987 compatibly) Rotate left (Not VHDL 1076-1987 compatibly) Rotate right (Not VHDL 1076-1987 compatibly)

B2.5 Size modify: RESIZE

function RESIZE (ARG: SIGNED; NEW_SIZE: NATURAL) return SIGNED; function RESIZE (ARG: UNSIGNED; NEW_SIZE: NATURAL) return UNSIGNED;

Those modifies width of the bit vector

B2.6 Conversion: TO_INTEGER

function TO_INTEGER (ARG: UNSIGNED) return NATURAL; function TO_INTEGER (ARG: SIGNED) return INTEGER; 116

Converts the bit vector in a Integer

TO_UNSIGNED TO_SIGNED B2.7 Logic: Not And Or Nand Nor Xor Xnor

function TO_UNSIGNED (ARG, SIZE: NATURAL) return UNSIGNED; function TO_SIGNED (ARG: INTEGER; SIZE: NATURAL) return SIGNED;

Converts number into a bit vector (without signs) Converts number into a bit vector (with signs)

function "not" (L: UNSIGNED) return UNSIGNED; function "not" (L: SIGNED) return SIGNED; function "and" (L, R: UNSIGNED) return UNSIGNED; function "and" (L, R: SIGNED) return SIGNED; function "or" (L, R: UNSIGNED) return UNSIGNED; function "or" (L, R: SIGNED) return SIGNED; function "nand" (L, R: UNSIGNED) return UNSIGNED; function "nand" (L, R: SIGNED) return SIGNED; function "nor" (L, R: UNSIGNED) return UNSIGNED; function "nor" (L, R: SIGNED) return SIGNED; function "xor" (L, R: UNSIGNED) return UNSIGNED; function "xor" (L, R: SIGNED) return SIGNED; function "xnor" (L, R: UNSIGNED) return UNSIGNED; function "xnor" (L, R: SIGNED) return SIGNED;

NOT AND OR NAND NOR XOR (Exclusives OR) XNOR (Not VHDL 1076-1987 compatibly)

B2.8 Match functions: STD_MATCH

function STD_MATCH (L, R: STD_ULOGIC) return BOOLEAN; function STD_MATCH (L, R: UNSIGNED) return BOOLEAN; function STD_MATCH (L, R: SIGNED) return BOOLEAN; function STD_MATCH (L, R: STD_LOGIC_VECTOR) return BOOLEAN; function STD_MATCH (L, R: STD_ULOGIC_VECTOR) return BOOLEAN;

TRUE, if bit vectors are alike after level (e.g. L means with 1)

B2.9 TranslationFunction: TO_01

function TO_01 (S: UNSIGNED; XMAP: STD_LOGIC := '0') return UNSIGNED; function TO_01 (S: SIGNED; XMAP: STD_LOGIC := '0') return SIGNED;

Transforms the " Std_logic" Bit vector into a unique bit vector (only with zeros and ones)

117

IEEE.std_logic_1164
(see /Vhdl_src/ieee/stdlogic.vhd)
B3.1 Type: std_ulogic

TYPE std_ulogic IS ('U','X','0','1','Z','W','L','H','-');

std_ulogic_vector std_logic std_logic_vector X01 X01Z UX01 UX01Z

TYPE std_ulogic_vector IS ARRAY ( NATURAL RANGE <> ) OF std_ulogic; SUBTYPE std_logic IS resolved std_ulogic; TYPE std_logic_vector IS ARRAY ( NATURAL RANGE <>) OF std_logic; SUBTYPE X01 IS resolved std_ulogic RANGE 'X' TO '1'; SUBTYPE X01Z IS resolved std_ulogic RANGE 'X' TO 'Z'; SUBTYPE UX01 IS resolved std_ulogic RANGE 'U' TO '1'; SUBTYPE UX01Z IS resolved std_ulogic RANGE 'U' TO 'Z';

More particularly " BIT " back-up type with additional statuses: U Uninitialized X Forced " indefinitely " 0 Forced 0 1 Forced 1 Z High impedance W Weak " indefinitely " L Weak 0 H Weak 1 indifferently Vector of the std_ulogic Bit type

Std_logic type with the values ' X ', ' 0 ' and ' 1' td_logic type with the values ' X ', ' 0 ', ' 1 ' and ' Z ' td_logic type with the values ' U ', ' X ', ' 0 ' and ' 1 ' Std_logic type with the values ' U ', ' X ', ' 0 ', ' 1 ' and ' Z '

B3.2 Logic: Not

And

FUNCTION "not" ( l : std_ulogic) RETURN UX01; FUNCTION "not" ( l : std_logic_vector ) RETURN std_logic_vector; FUNCTION "not" ( l : std_ulogic_vector ) RETURN std_ulogic_vector; FUNCTION "and" ( l : std_ulogic; r : std_ulogic ) RETURN UX01; FUNCTION "and" ( l, r : std_logic_vector ) RETURN std_logic_vector; FUNCTION "and" ( l, r : std_ulogic_vector ) RETURN std_ulogic_vector;

NOT

AND

118

Or

Nand

Nor

Xor

Xnor

FUNCTION "or" ( l : std_ulogic; r : std_ulogic ) RETURN UX01; FUNCTION "or" ( l, r : std_logic_vector ) RETURN std_logic_vector; FUNCTION "or" ( l, r : std_ulogic_vector ) RETURN std_ulogic_vector; FUNCTION "nand" ( l : std_ulogic; r : std_ulogic ) RETURN UX01; FUNCTION "nand" ( l, r : std_logic_vector ) RETURN std_logic_vector; FUNCTION "nand" ( l, r : std_ulogic_vector ) RETURN std_ulogic_vector; FUNCTION "nor" ( l : std_ulogic; r : std_ulogic ) RETURN UX01; FUNCTION "nor" ( l, r : std_logic_vector ) RETURN std_logic_vector; FUNCTION "nor" ( l, r : std_ulogic_vector ) RETURN std_ulogic_vector; FUNCTION "xor" ( l : std_ulogic; r : std_ulogic ) RETURN UX01; FUNCTION "xor" ( l, r : std_logic_vector ) RETURN std_logic_vector; FUNCTION "xor" ( l, r : std_ulogic_vector ) RETURN std_ulogic_vector; FUNCTION "xnor" ( l : std_ulogic; r : std_ulogic ) RETURN UX01; FUNCTION "xnor" ( l, r : std_logic_vector ) return std_logic_vector; FUNCTION "xnor" ( l, r : std_ulogic_vector ) return std_ulogic_vector;

OR

NAND

NOR

XOR (Exclusives OR)

XNOR (Not VHDL 1076-1987 compatibly)

B3.3 Conversion: To_bit

FUNCTION To_bit ( s : std_ulogic; xmap : BIT := '0') RETURN BIT;

To_bitvector

To_StdULogic To_StdLogicVector

FUNCTION To_bitvector ( s : std_logic_vector ; xmap : BIT := '0') RETURN BIT_VECTOR; FUNCTION To_bitvector ( s : std_ulogic_vector; xmap : BIT := '0') RETURN BIT_VECTOR; FUNCTION To_StdULogic ( b : BIT ) RETURN std_ulogic; FUNCTION To_StdLogicVector ( b : BIT_VECTOR ) RETURN std_logic_vector; FUNCTION To_StdLogicVector ( s : std_ulogic_vector ) RETURN std_logic_vector; FUNCTION To_StdULogicVector ( b : BIT_VECTOR ) RETURN std_ulogic_vector; FUNCTION To_StdULogicVector ( s : std_logic_vector ) RETURN std_ulogic_vector; FUNCTION To_X01 ( s : std_logic_vector ) RETURN std_logic_vector; FUNCTION To_X01 ( s : std_ulogic_vector ) RETURN std_ulogic_vector; FUNCTION To_X01 ( s : std_ulogic ) RETURN X01; FUNCTION To_X01 ( b : BIT_VECTOR ) RETURN std_logic_vector; FUNCTION To_X01 ( b : BIT_VECTOR ) RETURN std_ulogic_vector; FUNCTION To_X01 ( b : BIT ) RETURN X01;

To_StdULogicVector

Converted " std_ulogic" Bit type in BIT (statuses not equal 0 or 1 replaced through xmap) Converted " std_logic_vector" /"std_ulogic_vector" Bit vector type in BIT (statuses not equal 0 or 1 replaced through xmap) Converts BIT in " std_ulogic" Bit type Converted BIT_VECTOR - / "std_ulogic_vector" Bit vector type in " std_logic_vector" Bit vector type Converted BIT_VECTOR - / "std_logic_vector" Bit vector type in " std_ulogic_vector" Bit vector type

To_X01

119

To_X01Z

To_UX01

FUNCTION To_X01Z ( s : std_logic_vector ) RETURN std_logic_vector; FUNCTION To_X01Z ( s : std_ulogic_vector ) RETURN std_ulogic_vector; FUNCTION To_X01Z ( s : std_ulogic ) RETURN X01Z; FUNCTION To_X01Z ( b : BIT_VECTOR ) RETURN std_logic_vector; FUNCTION To_X01Z ( b : BIT_VECTOR ) RETURN std_ulogic_vector; FUNCTION To_X01Z ( b : BIT ) RETURN X01Z; FUNCTION To_UX01 ( s : std_logic_vector ) RETURN std_logic_vector; FUNCTION To_UX01 ( s : std_ulogic_vector ) RETURN std_ulogic_vector; FUNCTION To_UX01 ( s : std_ulogic ) RETURN UX01; FUNCTION To_UX01 ( b : BIT_VECTOR ) RETURN std_logic_vector; FUNCTION To_UX01 ( b : BIT_VECTOR ) RETURN std_ulogic_vector; FUNCTION To_UX01 ( b : BIT ) RETURN UX01; FUNCTION rising_edge (SIGNAL s : std_ulogic) RETURN BOOLEAN; FUNCTION falling_edge (SIGNAL s : std_ulogic) RETURN BOOLEAN; TRUE, if signal change from 0 to 1 TRUE, if signal change from 1 to 0

B3.4 Edge identification: RISING_EDGE FALLING_EDGE

B3.5 Signal identification: Is_X

FUNCTION Is_X ( s : std_ulogic_vector ) RETURN BOOLEAN; FUNCTION Is_X ( s : std_logic_vector ) RETURN BOOLEAN; FUNCTION Is_X ( s : std_ulogic ) RETURN BOOLEAN;

TRUE, if signal contains ' X ', ' U ', ' W ' or ' Z '

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VHDL standard library STANDARD

(see / Vhdl_src/std/standard.vhd)
B4.1 Type: BOOLEAN BIT BIT_VECTOR CHARACTER

INTEGER NATURAL POSITIVE REAL STRING TIME DELAY_LENGTH SEVERITY_LEVEL FILE_OPEN_KIND FILE_OPEN_STATUS B4.2 Function:

type boolean is (false,true); type bit is ('0', '1'); type bit_vector is array (natural range <>) of bit; type character is ( nul, soh, stx, etx, eot, enq, ack, bel, bs, ht, lf, vt, ff, cr, so, si, dle, dc1, dc2, dc3, dc4, nak, syn, etb, can, em, sub, esc, fsp, gsp, rsp, usp, ' ', '!', '"', '#', '$', '%', '&', ''', '(', ')', '*', '+', ',', '-', '.', '/', '0', '1', '2', '3', '4', '5', '6', '7', '8', '9', ':', ';', '<', '=', '>', '?', '@', 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 'I', 'J', 'K', 'L', usw.); type integer is range -2147483648 to 2147483647; subtype natural is integer range 0 to integer'high; subtype positive is integer range 1 to integer'high; type real is range -1.0E308 to 1.0E308; type string is array (positive range <>) of character; type time is range -2147483647 to 2147483647 units fs; ps = 1000 fs; ns = 1000 ps; us = 1000 ns; ms = 1000 us; sec = 1000 ms; min = 60 sec; hr = 60 min; end units; subtype delay_length is time range 0 fs to time'high; type severity_level is (note, warning, error, failure); type file_open_kind is (read_mode, write_mode, append_mode); type file_open_status is (open_ok, status_error, name_error, mode_error);

impure function now return delay_length; B4.3 Attribute: FOREIGN

attribute foreign : string;

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VHDL standard library TEXTIO

(see / Vhdl_src/std/standard.vhd)

B5.1 Type: LINE TEXT SIDE WIDTH

type LINE is access string; type TEXT is file of string; type SIDE is (right, left); subtype WIDTH is natural; file input : TEXT open read_mode is "STD_INPUT"; file output : TEXT open write_mode is "STD_OUTPUT";

Data file? Text file Adjustment? Bit width? ? ?

B5.2 Function: READLINE READ

WRITELINE

procedure READLINE(file f: TEXT; L: out LINE); procedure READ(L:inout LINE; VALUE: out bit; GOOD : out BOOLEAN); procedure READ(L:inout LINE; VALUE: out bit); procedure READ(L:inout LINE; VALUE: out bit_vector; GOOD : out BOOLEAN); procedure READ(L:inout LINE; VALUE: out bit_vector); procedure READ(L:inout LINE; VALUE: out BOOLEAN; GOOD : out BOOLEAN); procedure READ(L:inout LINE; VALUE: out BOOLEAN); procedure READ(L:inout LINE; VALUE: out character; GOOD : out BOOLEAN); procedure READ(L:inout LINE; VALUE: out character); procedure READ(L:inout LINE; VALUE: out integer; GOOD : out BOOLEAN); procedure READ(L:inout LINE; VALUE: out integer); procedure READ(L:inout LINE; VALUE: out real; GOOD : out BOOLEAN); procedure READ(L:inout LINE; VALUE: out real); procedure READ(L:inout LINE; VALUE: out string; GOOD : out BOOLEAN); procedure READ(L:inout LINE; VALUE: out string); procedure READ(L:inout LINE; VALUE: out time; GOOD : out BOOLEAN); procedure READ(L:inout LINE; VALUE: out time); procedure WRITELINE(file f : TEXT; L : inout LINE);

Line reads from text file Reads data from data file

Line writes in text file

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WRITE

ENDFILE

procedure WRITE(L : inout LINE; VALUE : in bit; JUSTIFIED: in SIDE := right; FIELD: in WIDTH := 0); procedure WRITE(L : inout LINE; VALUE : in bit_vector; JUSTIFIED: in SIDE := right; FIELD: in WIDTH := 0); procedure WRITE(L : inout LINE; VALUE : in BOOLEAN; JUSTIFIED: in SIDE := right; FIELD: in WIDTH := 0); procedure WRITE(L : inout LINE; VALUE : in character; JUSTIFIED: in SIDE := right; FIELD: in WIDTH := 0); procedure WRITE(L : inout LINE; VALUE : in integer; JUSTIFIED: in SIDE := right; FIELD: in WIDTH := 0); procedure WRITE(L : inout LINE; VALUE : in real; JUSTIFIED: in SIDE := right; FIELD: in WIDTH := 0; DIGITS: in NATURAL := 0); procedure WRITE(L : inout LINE; VALUE : in string; JUSTIFIED: in SIDE := right; FIELD: in WIDTH := 0); procedure WRITE(L : inout LINE; VALUE : in time; JUSTIFIED: in SIDE := right; FIELD: in WIDTH := 0; UNIT: in TIME := ns); function ENDFILE(file F : TEXT) return boolean;

Writes data in data file

TRUE, if achieves end

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References
1. VHDL Users Manual, Prof. Dirk Jansen, Version 1.0 2. VHDL Made Easy, Pellerin and Tylor, 1997 Prentice Hall 3. http://www.vhdl-online.de, Prof. Wolfram H. Glauert 4. Schaltungsdesign mit VHDL, Lehmann, Wunder und Franzis 5. Abstrakte Modellierung digitaler Schaltungen, Klaus Hagen

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