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3.5 MOSFET Scaling and Small-Geometry Effects
3.5 MOSFET Scaling and Small-Geometry Effects
constant field and constant voltage scaling and their effects. 2. Understand small geometry effects for MOS transistors and their implications for modeling and scaling 3. Understand and model the capacitances of the MOSFET as:
1) Lumped, voltage-dependent capacitances 2) Lumped, fixed-value capacitances
Goals
4. Be
3
MOS Scaling
Quantity Length Width Gate Oxide Thickness Supply Voltage Threshold Voltage Doping Density Area (A) Sensitivity L W tox Vdd VT0 NA, ND Device Characteristics WL W/Ltox 1/S2 S 1/S 1/S 1 1/S f 1/S2 1 1/S2 S S 1/S 1/S 1/S2 f S S3 Constant Field 1/S 1/S 1/S 1/S 1/S S Constant Voltage 1/S 1/S 1/S 1 1 S2 Scaling Parameters
D-S Current (IDS) Gate Capacitance (Cg) Transistor On-Resistance (Rtr) Intrinsic Gate Delay () Clock Frequency Power Dissipation (P) Power Dissipation Density (P/A)
5
(Vdd - vT)2
WL/tox Vdd/IDS RtrCg f IDSVdd P/A
2 i
1 NA
1 1 1 1 x j _ scale = x j V = 2 V S S NA S NA
Thus, for constant voltage scaling, NA_scale => S2NA, and ND_scale => S2ND On the other hand, for full scaling, VA => V/S giving:
x j _ scale = 1 1 xj S S 1 NA V = 1 S NA
2
V =
V SNA S
Thus, for full scaling, NA_scale => SNA, and ND_scale => SND
7
Voltage Scaling IDS_scale => SIDS. Wscale => W/S and xj_scale => xj/S for the source and drain (same for metal width and thickness). So JD_scale => S3JD, increasing current density by S3. Causes metal migration and self-heating in interconnects. Since Vdd_scale => Vdd and IDS_scale => SIDS, the power P_scale => SP. The area A_scale => A/S2. The power density per unit area increases by factor S3. Cause localized heating and heat dissipation problems. Electric field increases by factor S. Can cause failures such as oxide breakdown, punch-through, and hot electron charging of the oxide. With all of these problems, why not use full scaling reducing voltages as well? Done Over last several years, departure from 5.0V, 3.3V, 2.5V, 1.5 V 2.Does Scaling Really Work? Not totally as dimension become small, giving us our next topic. 8
Electromigration Effect
1. Wire
can tolerate only a certain amount of current density. 2. Direct current for a long time causes ion movement breaking the wire over time. n Current density falls off exponentially with depth into the conductor. 3. Perimeter of the wire, not the area important. 4. Use of copper (heavier ions) have helped in tolerating electromigration.
These figures are derived from Digital integrated circuit a design perspective, J. Rabaey Prentice Hall 10
Self Heating
1. Electromigration
of the current. 2. Self-heating is just proportional to the amount of current the wire carries. 3. Current flow causes the wire to get heated up and can result in providing enough energy to carriers to make them hot carriers. 4. Self-heating effect can be reduced by sizing the wire (same as electromigration).
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Effects always present, but masked for larger channel lengths Effects absent until a channel dimension becomes small Many, but not all of these effects represented in SPICE, so a number of the derivations or results influence SPICE device models.
2.Short
Channel Effects
What is a short-channel device? The effective channel length (Leff) is the same order of magnitude as the source and drain junction depth (xj).
Velocity Saturation and Surface Mobility Degradation Drift velocity vd for channel electrons is proportional to electric field along channel for electric fields along the channel of 105 V/cm
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LD Source Drain (p+) n+ n+ Junction Depletion Region Junction Depletion Region Gate-induced Buck (p-Si) Depletion Region 14 VB=0 (p+)
L + LD L1 S 2L
Thus, the channel charge per unit area is reduced by the factor:
+ 1 LS LD 2L
Next, need LS and LD in terms of the source and drain junction depths and depletion region junction depth using more geometric arguments. Once this is done, the resulting reduction in threshold voltage VT due to the short channel effect can be 16 written as:
LD xdm
xj
xj
n+
17
(p-Si)
QNC
Fig. 3.26
I D (subthreshold )
c 0
LB
VT
e kT e kT
GS
DS
VT
Long-channel threshold
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Thinning of tox As oxide becomes thin, localized sites of nonuniform oxide growth (pinholes) can occur, and can cause electrical shorts between the gate and substrate. The dielectric strength of the thin oxide may permit oxide breakdown due to application of an electric field in excess of breakdown field. May cause permanent damage due to current flow through the oxide.
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(n+)
LD
Gate
LD
(n+)
xj
n+
(p+)
Substrate (p-Si)
25
LM: mask length of the gate L: channel length LD: gate-drain overlap Y: diffusion length W: width of the source and drain diffusion region
Fig. 3.29
Cdb MOSFET
(DC Model)
Cutoff No channel formation => Cgs = Cgd = 0. The gate capacitance to the substrate Cgb = Cox W L Linear The channel has formed and the capacitance is from the gate to the source and drain, not to the substrate. Thus Cgb=0 and Cgs Cgd (Cox W L)/2 28
In saturation, the channel does not extend to the drain. Thus, Cgd=0 and Cgs (Cox W L)*2/3 These capacitances as a function of VGS (and VDS) can be plotted as in Kang and Leblebici Fig.3.32. Note that the capacitance seen looking into the gate is Cg: CoxW( 2L/3+2LD) Cg= Cgb+ Cgs + Cgd CoxW(L+2LD) For manual calculations, we approximate Cg as its maximum value.
Capacitance Cgb(total) Cgd(total) Cgs(total) Cut-off CoxWL CoxWLD CoxWLD Linear 0 CoxWL/2+CoxWLD CoxWL/2+ CoxWLD Saturation 0 CoxWLD 2CoxWL/3+ CoxWLD
This component of input capacitance is directly proportional to L and W and inversely proportional to tox.
30
MOSFET Capacitances Junction Capacitance Geometry (1/3) Junction Capacitances 1. Capacitances associated with the source and the drain 2. Capacitances of the reversed biased substrate-to-source and substrate-to-drain pn junctions. 3. Lumped, but if the diffusion used as a conductor of any length, both its capacitance and resistance need to be modeled in a way that tends more toward a distributed model which is used for resistive interconnect.
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Junction between p substrate and n+ drain (Bottom) Area: W(Y+xj) = AD Junction between p+ channel stop and n+ drain (Sidewalls) Area: xj(W+2Y) = xj PD
33
xd =
36
2 Si N A + N D ( V ) q N A ND 0
Q j = Aq
N A ND N A ND (0 V ) xd = A 2 Si q N A+ ND N A+ ND
(1V / )
0
1/ 2
with
37
C j0 =
S q NAND 1 2 N A + N D 0
i
Keq =
38
2 0 0 V 2 0 V1 V1 V 2
Summary
Full scaling (constant field scaling) better than constant voltage scaling if the power supply value can be changed. Scaling is subject to small geometry effects that create new limitations and requires new modeling approaches. The short-channel effect, narrow-channel effect, mobility degradation, and subthreshold conduction all bring new complications to the modeling of the MOSFET. Geometric and capacitance relationships developed permit us to calculate: a) the two overlap capacitances due to lateral diffusion, b) the three transistor-mode dependent oxide capacitances c) the voltage-dependent bottom and sidewall junction capacitances for the sources and drain, and d) fixed capacitance source and drain capacitances values for 39 a voltage transition in manual calculations.