Adv Digital Design

By Dr. Shoab Ahmed Khan

shoab@avaz.com shoab@avaz com

Fall 2002

Multipliers
Engineering Education Trust Center for Advanced Studies in Engineering

The art of algorithm to architecture mapping

Multipliers
SequentialandArrayMultipliers

WhyMultipliers? Why Multipliers?

UsedinmanyDSPapplications
Vectorproduct,matrixmultiplication Convolution Filtering(tapdelaylinefilter,adaptivefilter,FIR,IIR,..) g( p y , p , , , )

Atleastonegoodreasonforstudyingmultiplicationand divisionisaninfinitenumberofwaysofperformingthese division is an infinite number of ways of performing these operationsandhencethereisaninfinitenumberofPhDs (or expensivepaidvisitstoconferencesinUSA)tobewonfrom inventingnewformsofmultipliers inventing new forms of multipliers AlanClements ThePrinciplesofComputerHardware,1986
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PhDDissertationonMultiplier PhD Dissertation on Multiplier

Adv. Digital Design By Dr. Shoab A. Khan

Multiplier
Basicideaisprettysimple,multiplyingA,andBtwoNbits numbers

A*B=P A*B=P
DonebygeneratingNnumberofpartialproducts,andaddingthem together:

Rowofdotsisapartialproduct: fd i i l d

ResultofmultiplyingAbyone bitofB(Aisthemultiplicand) Resultisa2Nbitproduct

ForintegeroperationswantLSBNbits, ForFractional(Qn.m)wantMSBNbits, Qn1.m1xQn2.m2
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Unsigned Multiply

4x4 multiply (p = a x b) 4x4multiply(p=axb)

a3b1 a3b2 a3b3 p7 p6 a2b3 p5 a2b2 a1b3 p4

a3

a2 b2 a2b0 a1b1 a0b2 p2

a1 b1 a1b0 a0b1

a0 b0 a0b0

b3 a3b0 a2b1 a1b2 a0b3 p3

p1

p0

0101 6 0110 5 0000 0101 0101 0000 0 0 0 1 1 1 1 0 30

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SEQUENTIALMULTIPLIERS SEQUENTIAL MULTIPLIERS

Adv. Digital Design By Dr. Shoab A. Khan

ShiftandAddMultiplier Shift and Add Multiplier

Amultipliercanbeimplementedusinga p p g repeatedshiftandaddalgorithm Thenumbertoberepeatedlyshiftedandadded isthemultiplicand is the multiplicand Thenumberoftimesitisshiftedandadded dependsonthemultiplier depends on the multiplier TakesNcycles,andgeneratesandaddsone partialproducteachcycles: Theresultistheproduct
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Unsignedshiftaddmultiplier(design1)
64bitMultiplicandreg,64bitALU, 64bitProductreg,32bitmultiplierreg

Multiplier = datapath + control

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Unsignedshiftaddmultiplier(version 1) )

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Observations
1/2bitsinmultiplicandalways0
64 bit dd i 64bitadderiswasted t d

0sinsertedinleftofmultiplicandasshifted
leastsignificantbitsofproductneverchanged onceformed

Insteadofshiftingmultiplicandtoleft, shiftproducttoright? p g
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MULTIPLYHARDWARE(Design2)
32bitMultiplicandreg,32bitALU, 64bitProductreg,32bitMultiplierreg

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ExampleofMultiplicationforDesign2 Example of Multiplication for Design 2

Partial Product is accumulated and shifted right at each step hift d i ht t h t

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Canwedobetter? Can we do better?

Productregisterwastesspacethatexactly Product register wastes space that exactly matchessizeofmultiplier

C bi M lti li CombineMultiplierregisterand it d Productregister

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Design3
32bitMultiplicandreg,32bitALU,64bitProductreg,(0bit Multiplierreg)

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ShiftandAddMultiplier Shift and Add Multiplier

shift_reg B

Prod

0 A Shift_reg A

n-bit Adder

mux 1

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Example

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SignedMultiplier Signed Multiplier

What about signed multiplication? Whataboutsignedmultiplication? Applydefinitionof2scomplement pp y p
Needtosignextendpartialproducts andsubtractattheend and subtract at the end BoothsAlgorithmiselegantwayto multiplysignednumbers
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Signed Multiplier

8x8 signed multiply 8x8signedmultiply

Signbitextension
11010011 -45 45 00101100 +44 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 1 1 1 11 1 1 1 0 1 0 0 1 1 1 1 1 1 11 1 0 1 0 0 1 1 0 0 0 00 0 0 0 0 0 0 0 1 1 11 1 0 1 0 0 1 1 0 00 0 0 0 0 0 0 0 000000000 1 1 1 1 1 0 0 0 0 1 0 0 0 1 0 0 -1980 1980
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Example: Signed by Signed

In case the multiplier is a negative number, while calculating the last partial product i.e. multiplying the multiplicand with the MSB bit, which has negative weight, the 2s complement of the multiplicand, is i used as th partial product d the ti l d t

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SignedMultiplier Signed Multiplier

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ParallelMultipliers

ARRAYMULTIPLIERS ARRAY MULTIPLIERS

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CarrySaveAdder Carry Save Adder

X=001011 Y=010101 + Z=111101 S= 100011 C= 011101 X n Y n CSA n+1 C n+1 S Z n

Digitalmultiplicationflow
Nbitinputsoperands(N=4)

PartialProductArrayGeneration =N

shiftedbinarynumbers hift d bi b Partial Product Array Reduction PartialProductArrayReduction =reductionto2binarynumbers Finaladdition =2nbitfinalproduct
Adv. Digital Design By Dr. Shoab A. Khan 24

Multiplier
Multiplier Multiplication Formation of Partial Products

Addition of Partial Products (Reduction)

Final Addition Stage

Product P d t

Partialproductgenerationfor6bitby6bitmultiplication

multiplier a5 a0

multiplicand b5 b0

ppij

columns to be added

PartialProductGeneration
UseanarrayofANDgatestoproducepartialproductsinparallel

PartialProductGenerationinVerilog Partial Product Generation in Verilog

define WIDTH = 6 module multiplier (a, b, prod); input [WIDTH-1:0] a,b; output [2*WIDTH-1:0] prod; t t [2*WIDTH 1 0] d reg [WIDTH-1:0] pp [0:WIDTH-1]; [ WIDTH 1:0] [0: WIDTH 1]; always@(a or b) for(i=0; i<WIDTH; i=i+1) pp[i] = a & {WIDTH { b[ i ] } };

DOTNotation DOT Notation

Level n

Level ( n+1)

sum carry

sum carry

(Full Adder)

(Half Adder)

No action

Partial product reduction

Three d are shown h dots h Each symbolizes a partial product Using U i FA reduces th d these t t bit to two bits One has the weight of 20(sum) The other has the weight of 21(carry) This type of reduction is known as 3 to 2 reduction or carry saves reduction y The two dots are reduced to 2 using a HA

PartialProductReduction Partial Product Reduction

CarrySaveReductionScheme Carry Save Reduction Scheme DualCarrySaveReductionScheme WallaceTreeReductionScheme ll d i S h DaddaTreeReductionScheme

12x12CarrySaveReduction Scheme

Level 1

HA

FA

FA

FA

FA

FA

HA

P0

Level 2

HA

FA

FA

FA

FA

FA

HA

P1

Level 3

HA

FA

FA

FA

FA

FA

HA

P2

Level 4

HA

FA

FA

FA

FA

FA

HA

P3

PC10

PS9 PC9

PS8PC8

PS7PC7

PS6PC6

PS5PC5

PS4 PC4

PS3

Free product bits

Carry Save Array

DualCarrySaveReduction Dual Carry Save Reduction

In dual carry save reduction scheme the Indualcarrysavereductionscheme,the partialproductsaredividedinto2equalsize groups Thecarrysavereductionschemeisappliedon boththegroupssimultaneously both the groups simultaneously Thisresultsintotwopartialproductlayersin eachgroup h

WallaceTreeMultipliers Wallace Tree Multipliers

One of the most commonly used multiplier Oneofthemostcommonlyusedmultiplier architecture Wallace Tree multiplier falls in the category of WallaceTreemultiplierfallsinthecategoryof logtimearraymultiplier Th Thenumberofadderlevelsincreases b f dd l l i logarithmicallyasthepartialproductrows increase

WallaceTreeMultipliers Wallace Tree Multipliers

Groupingthepartialproductsintogroupsofthreecarriesout thereduction Unlikelineartimearrays,thesepartialproductgroupsare reducedsimultaneouslythroughcarrysaveaddition reduced simultaneously through carry save addition technique Each partial product row spits out two rows Th These rows th then, with other rows f ith th from other partial product th ti l d t groups, form a reduced matrix This process continues until only two rows are left At this stage, no further reduction is done The final rows are added together for the final product

AdderLevelsinWallaceTreeReductionScheme
Number of partial Products 3 4 5n6 7n9 10 n 13 14 n 19 20 n 28 29 n 42 43 n 63 Number of full adder Levels 1 2 3 4 5 6 7 8 9

6x6Wallacetree

2 sComplementSignedMultiplier 2s Complement Signed Multiplier

SignedMultiplication:
Rememberfor2scomplementnumbersMSBhasnegative weight: N 2

X = xi 2 xn 1 2
i i =0

n 1

ex:6=110102 =020 +121 +022 +123 124 =0+2+0+8 = 0 + 2 + 0 + 8 16 = 6 =6

SignedMultiplier Signed Multiplier

What about signed multiplication? Whataboutsignedmultiplication? Applydefinitionof2scomplement pp y p
Needtosignextendppandsubtract finalpp final pp

SignExtension Sign Extension

SXXXXXXXXXX SXXXXXXXXXX SXXXXXXXXXX SXXXXXXXXXX SXXXXXXXXXX SXXXXXXXXXX 000000XXXXXXXXXX 00000XXXXXXXXXX 0000XXXXXXXXXX 000XXXXXXXXXX 00XXXXXXXXXX 0XXXXXXXXXX 111111XXXXXXXXXX 11111XXXXXXXXXX 1111XXXXXXXXXX 111XXXXXXXXXX 11XXXXXXXXXX 1XXXXXXXXXX

IF S=0

S = Si bit Sign S = 0 : Positive S = 1 : Negative

IF S=1

Signextensionviapaddingof1 stotheleft Sign extension via padding of 1s to the left

SignExtensionElimination Sign Extension Elimination

1111111 111111SXXXXXXXXXX 11111SXXXXXXXXXX 1111SXXXXXXXXXX 111SXXXXXXXXXX 11SXXXXXXXXXX 1SXXXXXXXXXX SXXXXXXXXXX SX XX XX XX XX XX 1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 111111 11111 1111 111 11 1 1000001

Sign extension correction vector

S SX SXX 10 00

S X X X 0

S X X X X 0

XXXX XXX XX X

CorrectionVectorComputation

Example: Singed x signed

CV: 0010 000 0010_000

StringProperty String Property

7=111=81=1001 31=11111=321 Or100001=321=31
In string of 1s, replace the least significant 1 with 1 and represent it with a bar on 1 Replace rest of th 1 i th string with 0 R l t f the 1s in the t i ith 0s Replace 0 of the end of string with a 1 Keep repeating this operation with all the strings of 1s in binary representation of the number

Example
00111101101111011101 00111101101111100101 00111101110000100101 00111110010000100101
String String String String

01000010010000100101
Hence the number of 1(s) has reduced from 14 to 6. Both have the same value. l

BoothRecodingAlgorithm Booth Recoding Algorithm

Boothrecodingmakesuseofthe stringproperty. gp p y

ModifiedBoothRecoding Modified Booth Recoding

Two Basic Operations in Multiplying TwoBasicOperationsinMultiplying
generationofpartialproducts accumulation of partial products accumulationofpartialproducts

TwoWaysofSpeedUp
acceleratetheaccumulation Partialproductreductiontechnique reducethenumberofpartialproducts d h b f i l d modifiedBoothrecoding

BasicIdea Basic Idea

Radix2 partialproduct=(multiplicant)x{0,1} Radix4
partial product =(multiplicant)x{00,01,10,11} partialproduct (multiplicant) x {00, 01, 10, 11}

x x + +

Whyarewedoingthis? Why are we doing this?

We have a 3 which is difficult to be handled Wehavea3whichisdifficulttobehandled Simpleshiftingcantbeperformedtohandle it Numbersarerequiredtobeinthisform (2,1,0,+1,+2) (2 1 0 +1 +2) Becauseifweget3,itmeans2+1hence resultingin2partialproducts resulting in 2 partial products

ModifiedBoothRecoding Modified Booth Recoding

The modified Booth recoding algorithm exploits the string g g p g property This technique reduces number of pps into half Partitioning the multipliers in groups of two and generating one row of pp for each group to achieve this reduction From left to right each pair is observed for string property along with the higher order bit of the previous pair For the first pair a zero is appended at left As the string property is applied on three bits, there are eight possibilities:

21 20 000: nostring.Thegroupiscodedwitha0. 001: endofstringiscodedas1 0 0 1: end of string is coded as 1

BoothRecoding Booth Recoding

010: startandendofastringatbit0,codedas21 20 =+1. 011: anendofstringatbitlocation0,codedas21=+2 100: astartofastringatbitlocation1;codedas21=2 101: astartofastringatbitlocation1andanendofstring 1 0 1: a start of a string at bit location 1 and an end of string athighbitlocationofthepreviouspair,21 + 20=1

BoothRecodingTable

BasicIdea Basic Idea

I t d f Insteadofmultiplyingwithasinglebit lti l i ith i l bit Wemultiplywithtwobitshence makingthepartialproductshalfinNo.

A= B=

10 10

10 10

11 11

01 01

For these two bits Booths algorithm restricts the value to be (-2, -1, 0, +1,+2) +2 means Shift left A by one +1 means Copy A in the answer 0 means copy all 0s 0s -1 means 2s complement and then copy -2 means 2s complement and then shift left

Booth sAlgorithm Booths Algorithm

Form pairs using string property Formpairsusingstringproperty 0 10 1011 01 UsetheMSBofthepreviousgrouptocheck forthestringpropertyonthepair,use0for thefirstpair

As the string property is applied on three bits there bits, are following eight possibilities: 21=2 20=1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 1 2 -2 2 -1 -1 1 0

Example!
X

10101101 1 0 0 0 1 1 0 10

100 001 110 010

-2 +1 -1 1

So the partial products have been reduced from 8 to 4 in number

Example!
10 11 01 -2 +1 -1 1 1 1 1 0 1 1 0 1 0 1 0 0 1 1 1 1 0 1 1 1 0 0 0 1 0 0 1

1 0 1 0 0

1 0 1 1 0

1 0 1 0 1

1 0 1 0 1

1 0 0 1 1

BoothRecoder
0 b b0 1 BR0
a 0 2 a a 2 a a 0 2 a a 2 a a 0 2 a a 2 a a 0 2 a a 2 a

5:1

Partial 5:1 Product Reduction Tree 5:1

b2 b3

BR1

b4 b5

BR2

b6 b7

BR3

5:1

Adder
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