Combinational Logic: Combinational Logic: Analysis and Design Analysis and Design

Combinational Logic:
Analysis and Design
Digital Logic Analysis and Design
Poras T. Balsara & Dinesh K. Bhatia

Center for Integrated Circuits and Systems
Department of Electrical Engineering
University of Texas at Dallas
Combinational Logic: Analysis & Design
Functional and Timing Analysis

Decoders and Encoders
Multiplixers and Demultiplexers
Programmable Logic Devices (PLDs)
ROM based logic
Field Programmable Gate Arrays (FPGAs)
Tristate Logic
© ptb/dkb (February 1, 2008) Introduction 2
1
Functional Analysis of Combinational
Circuits
Combinational circuit => no feedback (no loops); output is

only
l ddependent
d t on th
the currentt iinput.
t
To determine the functionality of a combinational circuit

find the truth table or K-map for the circuit:
Assign a unique name to each node in the network.
Moving from input to output, for each labeled node, write a
b l
boolean equation
i as a ffunction
i off prior
i nodes.
d
Find boolean equation for output(s); simplify the equation to
minterm (maxterm) form (i.e., CSOP or CPOS form).
Fill in truth table or K-map
Example: functional analysis
Boolean equations for internal nodes: Truth table for function f

a b c f
T1 = b c
0 0 0 1
T 2 = T1⋅a = b c ⋅a 0 0 1 1
0 1 0 1
T 3 = T1 = b c
0 1 1 1
Boolean equation for the final output: 1 0 0 0
1 0 1 0
f = T 2 + T 3 = b c ⋅a + b c = b c + a 1 1 0 0
1 1 1 1
2
Additional examples
T1
T2
Example 1
T3
T1
T2
T3
T4 Example 2
Timing Parameters
Rise Time (tr), the time required for a signal to transition
from 10% of its maximum value to 90% of its maximum
value.
value
Fall Time (tf), the time required for a signal to transition

from 90% of its maximum value to 10% of its maximum
value.
Propagation Delay (tpLH, tpHL), the delay measured from

the time the input is at 50% of its full swing value to the
time the output reaches its 50% value.
3
Timing parameters (contd…)
Example: Gate delay

Determine the worst case propagation delay through
these circuits.
4
Timing Analysis of Combinational
Circuits
Using gates with finite propagation delays, tpLH and tpHL
instead of zero gate delays used in functional analysis.
Gate tpLH tpHL

INV 3 ns 2 ns
XOR 5 ns 4 ns
Vin 0→1 Transition on Vin
V1 2
Gate tpLH tpHL
V2 3
INV 3 ns 2 ns
XOR 5 ns 4 ns
V3 2
5
Vout 4
8 ns
t=0
1→0 Transition on Vin
Vin
V1 3
V2 2
V3 3
5
Vout 4
9 ns
5
Example: Timing Analysis
Karnaugh Maps
Truth tables are a convenient form to represent equations
but they don’t aid in the simplification of logic equations.
Karnaugh maps (K-maps) are similar to TT’s and they

lead to graphical methods for boolean expression
simplification.
A K-map is a multi-dimensional tabulation of function

values.
Each minterm is assigned an entry (a cell) in the table.

The cell contains the value of the function for the
corresponding minterm.
6
1 variable K-map: f(a)
2 variable K-map: f(a,b)
3-variable K-map: f(a,b,c)
7
4-variable K-map: f(a,b,c,d)
K-map Example 1
f = a+ bc + d
f ( a , b , c , d ) cd
abb 00 01 11 10
00
d d
bc bc
01
d d
a a a b a
bc b
bc
11
d d
a a a a
10
d d
8
f = a+ bc + d
f ( a , b , c , d ) cd
abb 00 01 11 10
00 1 1
d d
bc bc
01 1 1 1
d d
a a a b a
bc b
bc
11 1 1 1 1
d d
a a a a
10 1 1 1 1
d d
K-map Example 1’
f ( a ,b, c , d ) f = a+ bc + d
ab
cd 00 01 11 10
a a
00
d d d d
a a
01
bc a bc a
11
bc a bc a
10
d d d d
Note: This K-map is drawn by swapping the placement of variable pairs ab and cd
9
f = a+ bc + d
f ( a ,b, c , d )
ab
cd
d 00 01 11 10
a a
00 1 1 1 1
d d d d
a a
01 0 0 1 1
bc a bc a
11 0 1 1 1
bc a bc a
10 1 1 1 1
d d d d
K-Map Properties
Minterms mapped to any two adjacent cells differ in
exactly one bit position
Example f ( w , x , y , z ) = ∑ ( 0,2 ,3,4,6,8,10 ,11 )
f ( w, x , y, z )
yz
wx 00 01 11 10
00 1 1 1
01 1 1
11
10 1 1 1
10
The sum of two minterms in adjacent cells can be
simplified to a single product (AND) term with one less
variable.
Example
f ( a , b , c ) bc
a 00 01 11 10
0 1 1 1
1 1 1
If we combine adjacent minterms in the first column we get,
abc + abc = bc (a + a ) = bc
That is, variable a is eliminated.
K-Map Based Minimization

The purpose of using K-maps is to aid in the simplification
of logic expressions.
Use of 1’s in K-maps gives minterm SOP form directly.

Use of 0’s in K-maps gives maxterm POS form directly.
Minterms (maxterms) that can be combined differ in

exactlyy one bit p
position.
Minimization using K-maps is done by grouping

“adjacent” minterms (maxterms).
11
Conditions for grouping:
Minterm (maxterm) groups are restricted to have size that is a
power of 2, e.g., 1, 2, 4, 8, …
All K-map cells in a group must have a 1 as their K-map entry for
grouping minterms (or 0 as their K-map
K map entry for maxterm groups).
All minterms (maxterms) must be adjacent; they must differ in
exactly i bits where, 2i is the size of the group.
To minimize a function, find the set of groups which

include all the required minterms; the function is the sum
of these groups (or if maxterms are used then the function
is the product of the groups).
The larger the groups, the better. Why?
Example: Grouping Minterms

f(w,x,y,z) yz
wx 00 01 11 10 Minterms:
0001 = m1
00 1 1
0011 = m3
1000 = m8
01
1001 = m9
1011 = m11
11 1 1100 = m12
10 1 1 1
{{m1,m3}
, } {{m9,m11}
, }
Groupings:
{m1,m9} {m8,m9} {m1,m3,m9,m11}
{m3,m11} {m8,m12}
Simplified Expression: f(w,x,y,z) = {m1,m3,m9,m11} + {m8,m12}

= x z + wyz
12
Example: Grouping Maxterms
f(w,x,y,z) yz
wx 00 01 11 10 Maxterms:
0000 = M0
00 0 1 1 0
0010 = M2
0100 = M4
01 0 0 0 0
0101 = M5
0110 = M6
11 1 0 0 0 0111 = M7
1010 = M10
10 1 1 1 0 1101 = M13
1110 = M14
1111 = M15
Groupings
p g ((note: all g
groupings )
p g are not listed):
{M0,M2,M4,M6}, {M4,M5,M6,M7}, {M5,M7,M13,M15},
{M2,M6,M10,M14}, {M6,M7,M14,M15}
Simplified Expression: f(w,x,y,z) = {M0,M2,M4,M6}{M5,M7,M13,M15}

{M2,M6,M10,M14}
= (w + z )(x + z )(y + z )
Logic Minimization: Example 1
yz yz
x 00 01 11 10 x 00 01 11 10
0 1 1 1 0 1 0 1 1
1 1 1 1 1 0 0 1
Sum of Products: Product of Sums:
( ,y, ) = z + x y
F(x,y,z) ( ,y, ) = (y + z ) (x + z )
F(x,y,z)
# INV = 2 # INV = 2
# AND2 = 1 # AND2 = 1
# OR2 = 1 # OR2 = 2
=> For example 1 SOP is SMALLER
13
Don’t Care Input Combinations
Sometimes functions are incompletely specified; the
function is not defined for some minterms.
Ö outputs
t t really
ll ddon’t
’t matter
tt when
h th
these input
i t combinations
bi ti occur,
or
Ö these input combinations never occur in normal operation.
These input combinations are known as don’t care

conditions.
Don
Don’tt cares are entered as X
X’ss in the K-map (sometimes D or d
are also used).
During simplification, X’s can be treated as 1’s or 0’s.
Don’t Care: Example
G (a , b , c , d ) = ∑ (0,4 ,8 ,12 ,13 ) + d (5 ,11 )
G
cd
ab 00 01 11 10
00 1
01 1 X
11 1 1
10 1 X
G (a , b , c , d ) = b c + c d
14
Example: Combinational Logic Design
Design a circuit that accepts binary numbers between 1

and 5 and ggenerates an output
p equal
q to the number of 1’s
in the input. Use only 2-input logic gates.
Determine the number of inputs and outputs

No. of inputs = 3
No. of outputs = 2
1. Create a truth table 2. K-maps and logic minimization
Inputs Outputs z0 b1 b0
b2 00 01 11 10
b2 b1 b0 z1 z0
0 X 1 1
0 0 0 X X
1 1 X X
0 0 1 0 1
z 0 = b0 + b2 b1
0 1 0 0 1
z1 b1 b0
0 1 1 1 0
b2 00 01 11 10
1 0 0 0 1 0 X 1
1 0 1 1 0
1 1 X X
1 1 0 X X
z1 = b2 b0 + b1 b0
or
1 1 1 X X z1 = b0 (b2 + b1 )
15
3. Gate level implementation
z1 = b0 (b2 + b1 )
z 0 = b0 + b2 b1
How fast can you run this circuit (or what is the throughput) ?
(i.e., how often can you supply new inputs to this circuit)
Implicant (Table) Based Minimization

Implicant: any set of 1’s that can be grouped together
(size 1 or greater).
Prime Implicant: an implicant which cannot be combined

with another implicant to form a larger implicant.
A prime implicant of a logic function F(x1,…,xn) is a normal
product term P(x1,…,xn) that implies F, such that if any variable is
removed from P, then the resulting product term does not imply F.
Minimal SOP Expression: a subset of the prime

implicants (possibly the entire set) – also known as the
essential prime implicants.
16
Examples
yz
wx 00 01 11 10
Some implicants
00 1
01 1 1
11 1 1 1 1
Prime Implicants
10 1 1
Essential Prime Implicants

How are the essential prime implicants determined?
Build a table of the prime implicants and their component

minterms as follows:
Prime implicants are listed along the vertical axis of the table
(i.e., rows of the table).
The minterms in the function are listed along the horizontal axis
(i.e., columns of the table).
Entry (i,i j) of the table is marked if the minterm at the head of
column j is contained in (covered by) prime implicant in row i.
17
Process the table as follows:
1. Find all minterms which are marked only once. The prime
implicant which contains that minterm will be in the minimal
expression. Mark as “covered” all minterms contained in such
prime implicants (primary essential prime implicants)
implicants).
2. Repeat step 1 until there are no more minterms contained in only
1 unselected prime implicant.
3. Find all minterms that have not been covered by prime implicants
from steps 1 and 2. Choose the minimum number of additional
prime implicants (secondary essential prime implicants) required
to cover the remaining minterms.
Example:
For a 4-variable function F(a,b,c,d), the prime implicant ac
covers minterms aXcX, i.e., ab’cd’, ab’cd, abcd’, abcd (or
minterms m10, m11, m13, m15)
Minimization Example
F(w,x,y,z) yz
wx 00 01 11 10
00 1
01 1 1 1
11 1
10 1 1 1 1
F (w, x , y , z ) = ∑ (m1 , m 4 , m 6 , m 7 , m 8 , m 9 , m10 , m11 , m15 )
18
1. Create and process the implicant table
m1 m4 m6 m7 m8 m9 m10 m11 m15
xyz X X
wxz X X
wxy X X
xyz X X
wy z X X
wx X X X X
F (w, x, y, z ) = ∑ (m1,m4 ,m6 ,m7 ,m8,m9 ,m10,m11,m15)
2. Determine the primary essential prime implicants
• m1 is only covered by x y z ; m4 is only covered by w x z ;
m8 is
i only
l covered by w x
db
• x y z + w x z + w x covers m1 , m 4 , m 6 , m8 , m 9 , m10 , m11
3. Determine the secondary essential prime implicants
• m7 and m15 are not covered; choose x y z to cover both of them.
4. Minimal expression is: F = xyz + wxz + wx + xyz

Example:
Simplify to SOP form:
(w + x )y + z + wxz = ((w + x )y ⋅ z ) + wxz

= (((w + x ) + y )z ) + w x z
= ((w x + y )z ) + w x z
= ((w + y )(x + y )z )+ w x z
= (w x + w y + x y + y y )z + w x z
= (w x z + w y z + x y z + y z )+ w x z
= w x (z + z ) + y z (w + x + 1 )
= wx + yz
19
Example:
Simplify to SOP and POS forms.
(a b + c )(b + c d ) = ab + abc d + bc + c c d
= ab + abc d + bc + 0
(
= a b 1 + c d + bc )
= ab+bc KK SOP form
= b (a + c ) KK POS form
Example:
Simplify to POS form:
f (x , y , z ) = x y z + x y + x y z
(
= xy z + z + xy )
= xy+ xy
(
= x+x y )
= 1⋅y
=y
20
Boolean Expressions and Truth Tables
To convert boolean expressions to truth table:
Expand the expression into the minterms (i.e., canonical SOP form) and
enter 1’s in truth table rows (or, expand into canonical POS and enter 0’s
for each maxterm).
Example
x y z f
0 0 0 1
f (x , y , z ) = z + y z 0 0 1 0
(
= z x + x + yz ) 0 1 0 1
0 1 1 1
= x z + yz + x z
( ) (
= x z y + y + yz x + x + x z y + y) ( ) 1
1
0
0
0
1
1
0
= xyz + xyz + xyz + xyz + xyz + xyz 1 1 0 1
= ∑ (0 , 2 , 3, 4 , 6 , 7 ) 1 1 1 1
Truth Tables and Boolean Expressions

To convert a truth table to a boolean expression:
Write a canonical SOP expression that consists of all minterms
(or write a canonical POS using maxterms) and then simplify the
algebraic expression.
Example
f (x , y , z )= ∑ (0, 2 , 3, 4, 6, 7 )
= xyz + xyz + xyz + xyz + xyz + xyz

( ) (
= x z y + y + yz x + x + x z y + y) ( )
= x z + yz + x z
( )
= z x + x + yz
= z + yz
21
K-map Example 2
f ( w, x , y, z ) = wz + x y + x
f ( w, x , y, z )
yz
y
wx 00 01 11 10
00
01
11
10
K-map Example 2
f ( w, x , y, z ) = wz + x y + x
f ( w, x , y, z )
yz
y
wx 00 01 11 10
00 1 1 1 1
x x x x
xy xy
01 1 1
wz xy xy wz
11 1 1 1
wz wz
10 1 1 1 1
x x x x
22
Logic Minimization: Example 2
yz
wx 00 01 11 10
00 0 1 0 0
01 0 1 1 0
11 1 1 1 1
10 1 1 0 0
SOP: POS:
F (w , x , y , z )= w x + w y + y z + x z F (w , x , y , z )= (w + z )(x + y )
# INV = 1 # INV = 1
# AND2 = 4 # AND2 = 1
# OR2 = 3 # OR2 = 2
=> For example 2 POS is SMALLER
Multiplexers
Multiplexing means transmitting a large number of
information units over a smaller number of channels or lines.
A digital
g multiplexer
p ((MUX)) selects binary
y information from
one of many input lines and directs it to a single output line.
Data selector (2n:1 MUX).
Inputs: 2n data inputs, n select lines.
Output: 1 data output line.
23
Internal Structure of a 4:1 MUX
A 2n:1 MUX needs 2n, (n+1)-input AND gates for selection and a
2n-input OR gate to generate the final output.
=> AND/OR logic structure
MUX Output Boolean Expression

2:1 MUX
Out = s ⋅ D0 + s ⋅ D1
4:1 MUX
Out = s1 s0 ⋅ D0 + s1 s0 ⋅ D1 + s1 s0 ⋅ D2 + s1 s0 ⋅ D3
General expression for 2n : 1 MUX

2n −1
Out = ∑ (mi ⋅ Di ) where mi is the i th minterm
i =0
24
MUX Based Logic Design
MUXes are sometimes called a hardware look-up table.
To implement an n-variable function using a 2n:1 MUX
Use a 2n:1 MUX, connect n input variables to the n select lines
(in the correct MSB-LSB order).
Wire MUX input Di to 1 if function includes minterm mi. All other
inputs are set to 0.
Example: Implement the function
F (a , b , c ) = ∑ (1, 2, 4, 7 )
using
us g a MUX U o of app
appropriate
op ate ssize.
e
MUX Based Logic

Advantages:
Easier to design combinational circuits.
Easier to debug circuits designed using multiplexers
multiplexers.
Disadvantages:
Multiplexers can become very large for a large number of inputs.
=> Good for small circuits.
Normally, any function with more than 4 variable is

impractical for direct implementation (i.e., using a single
MUX).
Use tree of small MUXes or using a variable as MUX data input or
Shannon’s Expansion Theorem for implementing large functions.
25
Multiplexer Tree
A larger MUX can be implemented using a tree of smaller
MUXes.
Example: Implement the function F (a , b , c ) = ∑ (1, 2, 4, 7 ) using
smaller MUXes instead of one 8:1 MUX.
Using a Variable as MUX Data Input

It is possible to implement an (n+1)-variable function
using a 2n:1 MUX
In addition to the constants 0 and 1, one variable or its
complement is connected to the data inputs
inputs.
Example: Use a 4:1 MUX to implement z (a , b , c )= ∑ (3, 5, 6 , 7 )
Use c as a MUX data input, i.e., a and b are select inputs..
z bc
00 01 11 10 z b
0 1
z (a , b , c ) = a b c + a b c + a b c + a b c
a a
0 0 0 1 0 0 0 c = c (a b ) + c (a b ) + c (a b ) + c (a b )
OR
1 0 1 1 1 = c ⋅ m1 + c ⋅ m 2 + c ⋅ m 3 + c ⋅ m 3
1 c 1
= c ⋅ m1 + c ⋅ m 2 + m 3 ⋅ (c + c )
0
c = c ⋅ m1 + c ⋅ m 2 + 1 ⋅ m 3
c z (a,b,c)
1
= 0 ⋅ m 0 + c ⋅ m1 + c ⋅ m 2 + 1 ⋅ m 3
a b
26
Example: MUX Based Logic
Example: Implement the function f (a , b , c ) = ∑ (1 , 2 , 4, 7 )
using 4:1 MUX.
Use variable a as MUX data input, i.e., b and c are select inputs.
f (a,b,c)=∑(1,2,4,7)
= ab c + a b c + ab c + a b c
= a(m1 ) + a(m2 ) + a(m0 ) + a(m3 )
MUX Based Logic: Generalized Method
To implement an (n+1)-variable function using a 2n:1 MUX

we use n variables as select (control) inputs.
E h combination
Each bi i fformed d using
i these
h n variables
i bl
selects exactly two rows of the truth table
(2 rows => exactly one of 4 possible values).
Truth table to multiplexer mapping:
I1 I2 … In In+1 F
… 0 0 0 1 1
1 0 1 0 1
select 0 I n+1 I n +1 1
inputs
27
Example: MUX Based Logic Design
a b c d F
0 0 0 0 1
0 0 0 1 1
1
0 0 1 0 0
d
0 0 1 1 1 1 D0
d D1
0 1 0 0 0
0 0 D2
0 1 0 1 0 1 D3 8:1
out
d D4 MUX
F
0 1 1 0 1 d D5
1 d D6
0 1 1 1 1
d D7
1 0 0 0 1 s2 s1 s0
d
1 0 0 1 0
a b c
1 0 1 0 0
d
1 0 1 1 1
1 1 0 0 1
d
1 1 0 1 0
1 1 1 0 1
d
1 1 1 1 0
Example:
a b c d F
0 0 0 0 1
1 F
0 0 0 1 1 bc
0 0 1 0 0 a 00 01 11 10
d
0 0 1 1 1
1 0 1 0
0 1 0 0 0
0 0 1 d 1 0
0 1 0 1 0
1 1 1 0
0 1 1 0 1
0 1 1 1 1
1 1 0 1 1
1 0 0 0 1
1 d d d d
d 0
1 0 0 1 0 1 0 0
1 0 1 0 0
d
1 0 1 1 1 K-map cell entry
1 1 0 0 1
d F0 value of F when d=0
1 1 0 1 0
1 1 1 0 1
d F1 value of F when d=1
1 1 1 1 0
28
Shannon’s Expansion Theorem
F (x1 , x 2 ,K , x i ,K , x n ) = x i ⋅ F (x1 , x 2 ,K , 0 ,K , x n )
+ x i ⋅ F (x1 , x 2 ,K ,1,K , x n )
out = s ⋅ D0 + s ⋅ D1
F (x1 , x 2 ,K , 0 ,K , x n ) D0 2:1
out F (x1 , x 2 ,K , x i ,K , x n )
MUX
F (x1 , x 2 ,K ,1,K , x n )
D1
S
xi
Example: Use of Shannon’s Expansion

Implement F (w , x , y , z ) = w x + x y + w z + x z
= w ⋅ {x y + x z}+ w ⋅ {x + x y + z + x z } = w ⋅ {x y + x z }+ w ⋅ {x + z }
{ [ ] } {
= w ⋅ x ⋅ y + z + x ⋅ [0] + w ⋅ x ⋅ [1] + x ⋅ z [ ]}
= w ⋅ {x ⋅ [ (y ⋅1 + y ⋅ z ) ] + x ⋅ [0]}+ w ⋅ {x ⋅ [1] + x ⋅ [ z ]}
1 D0
[y + z ]
{x y + x z }
out
2:1
z D1
s D0
out
2:1
0 D1
s
y D
D0
F (w , x , y , z )
out
2:1
D1
D0 s
1
out
2:1
z D1
s
{x + z } w
x
29
Demultiplexer
Demultiplexer is an inverse of a multiplexer – it connects
one input to one-of-2n outputs using an n-bit select input
The time a teacher takes in explaining is

inversely proportional to the information
retained by students
30
Decoders
Binary-to-Decimal decoder: n inputs, 2n outputs (n x 2n
decoder). Some decoder have enable inputs.
E h output
Each t t represents
t a minterm
i t off an n-variable
i bl
function. The output that corresponds to the minterm that
appears on the inputs is asserted (active low or high
depending upon the device), all other outputs are inactive.
s1 s0 EN D3 D2 D1 D0
0 0 1 0 0 0 1
0 1 1 0 0 1 0
1 0 1 0 1 0 0
1 1 1 1 0 0 0
X X 0 0 0 0 0
Decoders can be used to implement logic functions as

follows:
31
BCD to SEVEN SEGMENT DISPLAY
A B C D a b c d e f g
0 0 0 0 1 1 1 1 1 1 0
0 0 0 1 0 1 1 0 0 0 0
0 0 1 0 1 1 0 1 1 0 1
0 0 1 1 1 1 1 1 0 0 1
0 1 0 0 0 1 1 0 0 1 1
0 1 0 1 1 0 1 1 0 1 1
0 1 1 0 1 0 1 1 1 1 1
0 1 1 1 1 1 1 0 0 0 0
1 0 0 0 1 1 1 1 1 1 1
1 0 0 1 1 1 1 1 0 1 1
d d d d 0 0 0 0 0 0 0
Build a 4x16 decoder using 2x4 decoders (decoder tree)..

a b c d EN minterm
0 0 0 0 1 m0
0 0 0 1 1 m1
0 0 1 0 1 m2
0 0 1 1 1 m3
0 1 0 0 1 m4
0 1 0 1 1 m5
0 1 1 0 1 m6
0 1 1 1 1 m7
1 0 0 0 1 m8
1 0 0 1 1 m9
1 0 1 0 1 m10
1 0 1 1 1 m11
1 1 0 0 1 m12
1 1 0 1 1 m13
1 1 1 0 1 m14
1 1 1 1 1 m15
X X X X 0 0
32
Encoders
Encoder is opposite of decoder. Its output code has
fewer bits than the input code.
Bi
Binary E
Encoder:
d
Input: 1-out-of-2n code (decimal input).
Output: n-bit binary code.
Priority Encoder
Consider a system with 2n devices, each of which
indicates a request for service.
a binary encoder can be used to determine the requesting device
if and only if at most one input is asserted at a time.
multiple requests at the same time can be handled by assigning
priority to the input lines, so that when multiple requests are
asserted, the encoding device produces the number of the
highest-priority requestor => a priority encoder.
D0 D1 D2 D3 b1 b0
1 0 0 0 0 0
X 1 0 0 0 1
X X 1 0 1 0
X X X 1 1 1
33
ROM Based Logic
ROM => Read Only Memory
Any boolean expression in the CSOP form can be
implemented using decoders (to generate all minterms)
and OR gate (to obtain the final output).
ROM, PROM, EPROM, EEPROM – PLDs based on a
table lookup.
Designer specifies the contents of the table. Inputs are used to
index into the table.
ROM is a PLD that includes AND/OR structure in a single

IC (AND => decoder).
Fixed AND array (decoder) generates all minterms;
designer determines which minterms are to be used to
implement the required boolean function
=> Fixed AND array, Programmable OR array.
A ROM is a memory device

(table) in which m-bit binary
data can be stored in each
of its 2n locations (minterms)
34
Structure of a ROM
Example: 32 x m ROM
32 locations or words (minterms) each of which has m bits.
5-bit
5 bit input is required to generate a minterm. Each 5-bit
5 bit input
combination uniquely selects a location (minterm). => This input is also
called its address and so the m bits in a location form the data.
32 decoder outputs are

connected through programmable
links to inputs of each of the
m output OR gates.
ROM Program
Programming of a ROM is done by retaining the links
corresponding to each minterm of a function Fi at the
i th OR gate and breaking (blowing) the rest
rest.
Program for a ROM is specified by describing the data
(contents) for each address (location) in that ROM.
For a multi-input, multi-output logic implemented in a ROM:
Addresses correspond to minterms.
Each bit of data correspond to one output of a multi-output logic.
At a given address in a ROM, a “1” for a data bit corresponds to the
“1” in the truth table for that output function and the given minterm.
ROMs are less efficient in implementing “random logic”

because they generate all minterms rather than taking
advantage of any minimization that may be possible.
35
Example: ROM Based Logic
Implement the following using an 8 x 4 ROM.
F1 (x , y , z ) = ∑ (0,1 , 2 , 5 , 6, 7 )
F2 (x , y , z ) = ∑ (3, 4, 7 )
Programmable Logic Devices

Programmable Logic Devices (PLDs) are devices with
prefabricated logic circuits and interconnect structure;
the circuit designer decides what functions the chip will
implement.
Chips usually provide AND gates wired to OR gates and

therefore usually implement SOP logic (FPGAs may not have
an AND/OR structure).
36
PLDs
PLDs with AND/OR logic structure:
PAL: Programmable AND array, Fixed OR array.
ROM
ROM: Fi d AND array, P
Fixed Programmable
bl OR array.
PLA: Programmable AND array, Programmable OR array.
There are other PLDs that generally do not use the

conventional AND/OR structure. These are called
Field Programmable Gate Arrays (FPGAs).
Logic Structures of PAL, PROM and PLA devices
37
PAL Based Logic
Programmable Array Logic (PAL) have programmable
AND array and fixed OR array.
D i
Designer specifies
ifi which
hi h lit
literals
l are iincluded
l d d iin each
h
product; specification of product terms in sums is usually
fixed by the manufacturer.
PAL 16L8
38
PAL Structure
Example: PAL Based Logic
39
Example: PAL Based Logic
B
2
C
3
ROMs versus PALs/PLAs

How do you choose between a ROM and a PAL/PLA-
based implementation ?
It depends on the structure of the functions being

implemented. That is,
1. # of unique product terms that must be generated to implement
all the output function,
2. the degree to which these terms can be shared among multiple
output functions
functions,
3. the number of terms that must be ORed together to implement a
given output function.
40
ROMs versus PALs/PLAs
PALs/PLAs based design:
Effective when # of unique terms is small and the degree of sharing
is high (PAL/PLAs do not always provide enough outputs from the
AND array if you need to generate many product terms).
PALs have limited # of terms contributing to output (fixed OR array).
Minimizing needed to reduce # of terms and increase sharing
=> it takes longer to design a circuit.
ROMs based design:

Effective
Eff ti when
h # off unique
i terms
t is
i llarge.
No minimizing needed => shorter design time.
ROM size is determined solely by the # of inputs and outputs, not
by the number of product terms. However, size of the ROM
doubles with each additional input.
Field--Programmable Gate Array (FPGA)

Field
RAM-based FPGA (Xilinx)
41
RAM-based Configurable Logic Block (CLB) Architecture
FPGA
MUX-based FPGA with fuse-based programmable
interconnect (Actel)
42
MUX-based Logic Module Architecture
Tristate Logic
Tristate
T i t t logic
l i allows
ll multiple
lti l outputs
t t tot be
b connected
t d together
t th as
long as only one output is active at any given time.
A tristate control (T ) is added to the output of a gate.
Output of this gate is left floating (HiZ state) when the tristate control
is inactive.
43
CMOS Tristate Inverting Buffer
Use of Tristate Buffers

Several tristate devices can be
connected together to share a single
p wire ((e.g.,
output g a data line of an n-bit
bus) as long as only one device
becomes the driver at any given time.
It is better not to disable one device

and enable another at the same time
since it may create driving conflicts on
the single output wire.
ai can drive the bus as

long as Ti = “1”
44
Combinational Logic Design Problems
Understand the Problem:

understand input/output behavior
identify the inputs,
inputs outputs,
outputs and control signals
draw a top level block diagram if necessary
Formulate in a Standard Representation:
truth tables or Boolean equations
Choose an Implementation:
discrete logic gates
programmable logic devices: PAL, PLA, ROM, FPGA
Apply the Design Procedure:
follow the representation → minimization → implementation
algorithm mechanically
simulate your circuit before implementing it on actual devices
implement it on actual devices and verify your implementation.
Do it yourself
Use algebraic manipulation to show that for a three input
varibles a,b, and c, ∑ m(1, 2,3, 4,5, 6, 7) = a + b + c
F a function
For f ti f (a, b, c, d ) = ∑ m(0, 2,3, 6,9,11,14) , use Shannon’s
Sh ’
expansion to derive an implementation using 2-to-1
multiplexers.
For a function f (a, b, c, d ) = ∑ m(0,1, 2,3,5, 7,8,10,13,15) , use implicant
table to realize the the minimum SOP form. Realize the
function using NOR gates only.
Simplfy the function f ( w, x, y, z ) = w.x. y + x. y.z + w. y.z to a POS
form using basic theorems. Derive a canonical POS form
out of the simplified POS form.
45

Combinational Logic: Combinational Logic: Analysis and Design Analysis and Design

Uploaded by

Copyright:

Available Formats

You might also like

Combinational Logic: Combinational Logic: Analysis and Design Analysis and Design

Uploaded by

Document Information

Original Description:

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Combinational Logic: Combinational Logic: Analysis and Design Analysis and Design

Uploaded by

Copyright:

Available Formats

Combinational Logic:

Analysis and Design

Digital Logic Analysis and Design

Poras T. Balsara & Dinesh K. Bhatia

Combinational Logic: Analysis & Design

 Functional and Timing Analysis

© ptb/dkb (February 1, 2008) Introduction 2

 Combinational circuit => no feedback (no loops); output is

 To determine the functionality of a combinational circuit

© ptb/dkb (February 1, 2008) Introduction 3

Example: functional analysis

 Boolean equations for internal nodes:  Truth table for function f

© ptb/dkb (February 1, 2008) Introduction 4

© ptb/dkb (February 1, 2008) Introduction 5

 Fall Time (tf), the time required for a signal to transition

 Propagation Delay (tpLH, tpHL), the delay measured from

© ptb/dkb (February 1, 2008) Introduction 6

© ptb/dkb (February 1, 2008) Introduction 7

Example: Gate delay

© ptb/dkb (February 1, 2008) Introduction 8

Gate tpLH tpHL

© ptb/dkb (February 1, 2008) Introduction 9

Vin 0→1 Transition on Vin

© ptb/dkb (February 1, 2008) Introduction 11

 Karnaugh maps (K-maps) are similar to TT’s and they

 A K-map is a multi-dimensional tabulation of function

 Each minterm is assigned an entry (a cell) in the table.

© ptb/dkb (February 1, 2008) Introduction 12

 2 variable K-map: f(a,b)

© ptb/dkb (February 1, 2008) Introduction 13

 3-variable K-map: f(a,b,c)

© ptb/dkb (February 1, 2008) Introduction 14

© ptb/dkb (February 1, 2008) Introduction 15

© ptb/dkb (February 1, 2008) Introduction 16

© ptb/dkb (February 1, 2008) Introduction 17

© ptb/dkb (February 1, 2008) Introduction 19

© ptb/dkb (February 1, 2008) Introduction 20

If we combine adjacent minterms in the first column we get,

That is, variable a is eliminated.

© ptb/dkb (February 1, 2008) Introduction 21

K-Map Based Minimization

 Use of 1’s in K-maps gives minterm SOP form directly.

 Minterms (maxterms) that can be combined differ in

 Minimization using K-maps is done by grouping

© ptb/dkb (February 1, 2008) Introduction 22

 To minimize a function, find the set of groups which

 The larger the groups, the better. Why?

© ptb/dkb (February 1, 2008) Introduction 23

Example: Grouping Minterms

Simplified Expression: f(w,x,y,z) = {m1,m3,m9,m11} + {m8,m12}

Simplified Expression: f(w,x,y,z) = {M0,M2,M4,M6}{M5,M7,M13,M15}

Logic Minimization: Example 1

Sum of Products: Product of Sums:

=> For example 1 SOP is SMALLER

© ptb/dkb (February 1, 2008) Introduction 26

 These input combinations are known as don’t care

© ptb/dkb (February 1, 2008) Introduction 27

Functional and Timing Analysis

Combinational circuit => no feedback (no loops); output is

To determine the functionality of a combinational circuit

Boolean equations for internal nodes: Truth table for function f

Fall Time (tf), the time required for a signal to transition

Propagation Delay (tpLH, tpHL), the delay measured from

Karnaugh maps (K-maps) are similar to TT’s and they

A K-map is a multi-dimensional tabulation of function

Each minterm is assigned an entry (a cell) in the table.

2 variable K-map: f(a,b)

3-variable K-map: f(a,b,c)

Use of 1’s in K-maps gives minterm SOP form directly.

Minterms (maxterms) that can be combined differ in

Minimization using K-maps is done by grouping

To minimize a function, find the set of groups which

The larger the groups, the better. Why?

These input combinations are known as don’t care

Design a circuit that accepts binary numbers between 1

Determine the number of inputs and outputs

Prime Implicant: an implicant which cannot be combined

Minimal SOP Expression: a subset of the prime

Build a table of the prime implicants and their component

General expression for 2n : 1 MUX

=> Good for small circuits.

Normally, any function with more than 4 variable is

To implement an (n+1)-variable function using a 2n:1 MUX

Truth table to multiplexer mapping:

Decoders can be used to implement logic functions as

Build a 4x16 decoder using 2x4 decoders (decoder tree)..

ROM is a PLD that includes AND/OR structure in a single

ROMs are less efficient in implementing “random logic”