ELEN E6321 Advanced Digital Electronics Circuits

Lecture 15: Power Supply

Acknowledgement: Prof Dennis Sylvester and David Blaauw

Outline
Power supply Packaging Power grid Package On-chip decoupling capacitors Transient analysis

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Power supply
Goal:
Supply a constant voltage (temporal/spatial) to all devices on chip

Problem:
Must get current from voltage regulator to chip

Supply system does not start from chip pins but includes board Supply network design is very difficult, even though small number of transistors
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From the regulator to the chip

Decoupling cap

Flip chip C4

Decoupling cap

C4: Controlled Collapsed Chip Connects

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Supply network model

PCB Package Chip

Decoupling cap Shorter wires, more R than L

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ITRS

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Voltage drop (1/2)

IR drop
VIR = IR

Max at peak current Scaling of Idc P

P=15W P=150W (10x)

I
P I = = 20 V

Ldi/dt drop

Due to change in current Scaling of Vac dI dt

f=200MHz f=1GHz (5x)
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Vdd=2.5V Vdd=1.25V (0.5x) dI VL = L dt

dI/dt
VL = 35
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I = 7
Advanced Digital Electronics Design

Voltage drop (2/2)

Time of drop is different. Do not strictly add
I

VIR

VL

Pulsed noise DC noise (sustained) under/over shoot Supply variation both: Time (temporal) Area (spatial)

Vdrop
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Problems due to power grid noise (1/3)

Sustained drop: Performance degradation
td CV 1 1 I Vgs Vt Vdd Vss Vt

V td

AC Noise: Functional/delay noise

Acts as standard noise pulse Difference not absolute DRIVER voltage drop Uniform drop is OK
RECEIVER

Vo,driver

Vg,receiver

Vs,driver

Vs,receiver

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Problems due to power grid noise (2/3)

TDDB: Time Dependent Dielectric Breakdown
Due to overshoots (inductance) Hot electrons cause injection into gate oxide, may get trapped degrade the performance of the transistor Limit on Vdd

Electromigration
High current densities displace metal atoms out of place due to momentum transfer.
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Problems due to power grid noise (3/3)

Cu is better than Al AC vs DC signal AC has e- moving in both directions DC only moves e- in one direction
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Elements of power supply system - Outline Board Package Chip

Power grid Decoupling cap

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Board design (1/3)

Decoupling cap Flip chip C4

Due to inductance Z Desired

Decoupling cap

1 Z = R + jL + j C

wr

r =
w
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1 LC
C
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Board design (2/3)

Decoupling cap Flip chip C4

Decoupling cap
Low freq Big Cap High freq Small Cap

Chip

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Board design (3/3)

Make sure resistance is small Decap design: act to filter high frequency current
Small cap w/low L near chip to suppress high frequency current
Try to get as close to chip as possible

Large cap w/higher L chip

further away from

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Package types (1/3)

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Package types (2/3)

Wire bonding
Advantages:
Cheap Allows for thermal expansion

Disadvantages:
High inductance (typical 5nH) Limited pads (~200)

To reduce R More metal layers To reduce L Lower distance from connections, bring cap closer
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Package types (3/3)

Flip-chip or C4 (controlled collapse chip connect)
Advantages:
Lower inductance (0.1nH) lower distance High number of pads (~1000)

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Pentium Package

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Power Integrity & Package

Package design becoming increasingly complicated
Detailed 3D modeling and simulation is necessary Magnetic coupling affects supply voltage integrity Runtime effects!

Large number of power/ground layers in current packages Significant Power supply variations caused by the package
chip
capacitor Solder balls capacitor

chip carrier

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Power Supply Variations Package Effects

VDD GND Planes Balls C4s

Power IR Drop by the package

Is usually non- uniform across the various C4 Can be difficult to predict and analyze

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On-Chip Power Delivery

C4 balls Connection to package

Connection to circuits

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Results: VDD Profile

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Voltage Map of Worst IR-Drop

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Power Grid design (1/3)

Tree
Local grids Simple Metal utilization is efficient Single wire failure

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Power Grid design (2/3)

Grid
High end processor Lots of metal Lower resistance Lines up with C4 Less J, better electromigration Spatial variation is lower Highly redundant

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Power Grid design (3/3)

Plane
Power planes, reserve two layers of metal Good to reduce inductive coupling

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Decoupling cap Implicit (1/3)

n-well cap

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Decoupling cap Implicit (2/3)

Vdd grid Vdd grid

Cgd,N/P
Cgd Cdb Csb Cgs

Cdb,N Ci,gnd Cgs,N

GND grid

GND grid

Ceff =

1 (Cdb, N + Cgs, N + Cdb,P + Cgs,P ) + 1 (Ci, gnd + Ci,Vdd ) + Cgd , N + Cgd ,P 2 2

Depends on state of circuit Current injected/extracted at different locations Includes both device and interconnect parasitics
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Decoupling cap Back of the envelope (3/3) Implicit decoupling capacitance is the capacitance that is not switching Assuming a switching factor of s
P = fCswitchVdd C switch P = 2 fVdd
2

C switch = sCtotal

Cdecap = (1 s )Ctotal Cdecap 1 s P = s fVdd 2

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Decoupling cap explicit (1/4)

Reliability: Thin oxide gate can short. Yield problem High gate leakage

Short only if double failure Gate voltage is half, less sensitive to gate failure Less cap

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Decoupling cap explicit (2/4)

Turns off the cap in case of oxide failure Less gate leakage Unusable if the transistor fails
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Variation of previous

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Active decoupling cap explicit (3/4)

Vdd
C/2
discharge
charge discharge
V

charge

C/2 Non-overlapping
Q = Vdd C C C Vdd + V n n n 1 C = C Vdd + V n n

Normal cap
Q = V C

This scheme

Charge Q = Vdd C
Discharge Q = C (Vdd V ) n

For n=2

1 C Q = C Vdd + V 2 2
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Active decoupling cap explicit (4/4)

Active decap design using miller effects High gain, high BW amplifiers is needed
Challenges for multi GHz microprocessors
J. Gu, et al., TVLSI, 2009

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DC-DC converters, Buck

Typical off-chip buck converter topology Simplified power delivery network for Intel Pentium 4 processor in 90nm technology

An off-chip DC-DC buck converter High voltage transistors High quality inductance Large capacitance. On-chip DC-DC converters Same load regulation Smaller capacitance Inductance is small, limited to materials.

DC-DC converter in the microprocessor die (a) and on a 3D-stacked die with through vias (b)
Karnik T, et al, Feasibility of monolithic and 3D-stacked DC-DC converters for microprocessors in 90nm technology generation, IEEE ISLPED04

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DC-DC Converter, Switch Cap

Fixed ratio conversions (e.g. 1/2, 1/3, ) Regulation away from the ratio is inefficient Better on-chip capacitor density than inductor
Example: trench decap from eDRAM process
L. Chang et al., VLSI Symposium, 2010

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Linear regulators (1/2)

Source-follower topology: Fast load regulation Good high frequency noise rejection Large M0 transistor even with overdrive

Common-source topology: Low dropout voltage w/o overdrive Small M0 transistors with large Vgs Load regulation by amplifier slow Worse supply rejections

Hazucha P, et al, An Area-Efficient, integrated, linear regulator with Ultra-fast load regulation, IEEE Symposium on VLSI Circuits, 2004

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Push-Pull (2/3)

Push-Pull can be very fast w/ digital loops

Internal reference generation Digital comparators in a push-pull fashion

More suitable for modern processors with high frequency supply noise
E. Alon et al., Integrated Regulation for Energy-Efficient Digital Circuits, JSSC, 2008

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High-tension power delivery (3/3)

a) Traditional linear regulation with large power xtor b) Power xtor is replaced with logic and a push-pull regulator (or switch capacitor circuits) Supplying higher Vdd (with lower current) Transition overhead b/w domains Efficiency degrades with load mismatch
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less impedance demands!

S. Rajapandian, et al, Charge-Recycling Voltage Domains for Energy-Efficient Low-Voltage Operation of Digital CMOS Circuits, IEEE ICCD, 2003

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Power grid model (1/3)

V (t )

L V (t ) = IR + I e C

Rt 2L

sin(r t )

r =
IR

1 LC

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Power grid model (2/3)

IR-drop

VIR I , R

Solved with more metal Spatial variation of voltage LdI/dt-drop

L VL I C

Damping

Decoupling cap can only help with 1 / C Current step input Out of reset Instructions

R 2L

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Power grid model (3/3)

Resonance

r =

1 LC

1 L Quality factor Q = R C
We do not want the system to resonate

10-15 years ago

r > clk

Harmonics of the clock might hit r Tune r to avoid clock harmonic

r kclk
k harmonic

r < clk Today Due to circuit activity, activation frequency can be lower than clk Cannot tune to avoid clock harmonic, depends on instruction stream
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kclk r l

k harmonic l loop
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How to fix
Reduce R: Use more metal. Tree Grid VIR but less damping Plane Q

Reduce L: Thin package, bondwire, flip-chip. More pads Q r VL difficult to control Increase C: Decoupling capacitance, but only Q VIR VL Area
C

Decrease I: Turn modules slowly, larger reset latency

I
VIR VL

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Measured Voltage During Transience

Voltage measured on package power plane @ 400 MHz w/ alternating stream of LO and HI power instructions

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Transient Analysis (200MHz Design)

Ramp: 0.4A (avg.) to 4A (avg) in one cycle
current time

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FFT Analysis (200 MHz Design)

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Resonance

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Transient Analysis Results

Design P1 P2 P3 Clk freq (MHz) 200 300 500 wr freq (MHz) 120 115 90 IR-drop (mV) 101 67 150 Undersho ot (mV) 183 246 345 Overshoot (mV) 100 159 199

No significant increase in IR-drop as speed and power increase However, noise due to power transience is increasing rapidly Decrease in resonance frequency is of critical concern.

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