Mini Project Report ON Equivalent Series Resistance Meter: AWH Engineering College, Calicut, Kerala University of Calicut

MINI PROJECT REPORT ON EQUIVALENT SERIES RESISTANCE METER
Presented By NAJLA P.R RESHMA K SHOUKEEN A.K SILJIYA K
Department of Electronics & Communication Engineering
AWH ENGINEERING COLLEGE, CALICUT, KERALA UNIVERSITY OF CALICUT
Single Button Electronic Lock
Mini Project Report 2011
2012
Department of ECE
AWH EC, Calicut
Department of Electronics & Communication Engineering
CERTIFICATE
Certified that this is the bonafide record of the project titled
EQUIVALENT SERIES RESISTANCE METER

Carried out by the under mentioned students NAJLA P.R RESHMA K SHOUKEEN A.K SILJIYA K In Partial fulfillment of the requirement for the award of bachelor of technology degree of electronics and communication engineering under the University of Calicut during the year 2011. Kuttikkatoor, Calicut Mini project co-ordinator Mr.MUHAMMED K.M Date: Prof. L. Mredhula Head of the Department
Department of ECE
AWH EC, Calicut
ACKNOWLEDGEMENT
This mini project is a testimony to the intensity, performance, motivation, and commitment of many individuals who have contributed to the successful completion of this mini project. We extend our sincere thanks to Dr. Shoukath Ali Karuvatt, Principal and Prof. L Mredhula, HOD, Electronics & Communication Engineering, for encouraging and aiding us throughout the project. We are extremely indebted to our mini project co-ordinator Mr.Muhammed K.M, Lecturer, ECE Dept. for her constant help and encouragement during the course of our project work.
Department of ECE
AWH EC, Calicut
DECLARATION
We the students of sixth semester, Electronics and Communication Department, AWH Engineering College, have successfully completed the mini project entitled EQUIVALENT SERIES METER to be submitted to the Calicut University as a part of our sixth semester curriculum by our own effort and with the help of our project co-ordinator Mr.Muhammed K.M Lecturer, ECE department.
NAJLA P.R RESHMA.K SHOUKEEN A.K SILJIYA K
ABSTRACT
The objective of the Project is to design and setup an easily programmed, single-button electronic lock that controls the powering on/off of any electrical device. The same security code is used to switch on this load as well as to switch it off once it had been switched on earlier. The designed circuit uses inexpensive CMOS logic. The lock is operated by entering a series of short and long presses from a push button switch. The unlock code is a series of 8 presses, which is a pre-decided sequence of short and long presses. In this work, the unlock code is a hardwired sequence of 4 adjacent long-short presses. A short press is a quick jab to the button; a long press is slightly a longer. The activation time of less than ~0.4 second corresponds to a short press and an activation time greater than ~0.6 second corresponds to a long press at the input. Any activation time between
Department of ECE
AWH EC, Calicut
0.4 second and 0.6 second is considered as an invalid press. This avoids the ambiguity between a short press and a long press. An invalid press will break the code. If L represents long press and S represents short press then the hardwired code sequence used in this work is LSLSLSLS. The same sequence is used for locking and unlocking the system. This sequence can be changed by hardware re-programming. The designed system starts up in RESET mode as indicated by a RED LED ON. It remains ON for about 5 seconds. This is the WAITING PERIOD. During the WAITING PERIOD, any button-press will be ignored. After the WAITING PERIOD is over, RED LED turns OFF and GREEN LED turns ON indicating the READY State. System remains in READY state for only about 3.5 seconds before which first press must be registered. If the system remains idle for ~3.5 seconds in the READY state, it switches itself to the RESET mode and WAITING PERIOD is activated. This sequence will continue until someone tries to enter the code. When a button-press is made during the READY State, the GREEN LED remains ON indicating that the READY State is extended. System toggles to the RESET mode if the next button-press is not entered within ~3.5 seconds of the previous press. The unlock or lock command is issued only if the correct sequence of 8 presses is entered during the READY state with a time gap not greater than 3.5 seconds between successive switch-press operations.
Department of ECE
AWH EC, Calicut
CONTENTS
CONTENTS.......................................................................................................................7 1. INTRODUCTION.........................................................................................................1 2. BLOCK DIAGRAM OF THE SYSTEM.....................................................................2 4. HARDWARE DESIGN..............................................................................................28 5. PCB DESIGN PROCEDURE.....................................................................................32 RESULTS ........................................................................................................................35 7. CONCLUSIONS.........................................................................................................36 8. BIBILIOGRAPHY......................................................................................................37 9. DATASHEETS...........................................................................................................38
Department of ECE
AWH EC, Calicut
1. INTRODUCTION
An Electronic Lock is an electronic subsystem that provides access control. Access control may be required to control access to some facility entry to a secure area through an access-controlled door is an example. Powering-ON and Powering-OFF a secure/critical electrical or electronic load through access-control mechanism is another example. The man-machine interface of commonly available electronic locks usually fall under two categories the card-swipe mechanism and the key-pad code entry mechanism. A different man-machine interface that is more difficult to tamper with and hence is more secure is attempted in this Mini-Project. The interface consists of a single push-button switch that has to be pressed and kept pressed for a pre-designed sequence of periods for a preprogrammed number of times. For instance, in the electronic lock designed in this Project, the user has to press the push-button switch 8 times with the first press lasting for > 0.6 sec, the second lasting for < 0.4 sec and then repeat this pattern 4 times to activate the output. The number of switch-presses and the pattern that comprise the security code can be modified by modifying/re-wiring the hardware.
1.1
User Level Description of the System

The external interface presented to the user consists of two LEDs (one RED and one
GREEN) and a Push-Button Switch. The labeled instruction requests the user to (i) enter the code sequence while the GREEN LED is ON with not more than 3.5 sec delay between successive code sequence entries (ii) wait till RED LED goes OFF and GREEN LED comes back to ON condition before trying again in case wrong code was entered inadvertently.
1 Department of ECE AWH EC, Calicut
2. BLOCK DIAGRAM OF THE SYSTEM

The system block diagram for the Single Button Electronic Lock designed in this Project is given in Fig. 2.1
2.1
Debounce Block
The Schmitt trigger NAND gates used in the input of the circuit debounces the code
entry switch. Logic of Schmitt trigger NAND gate is same as that of ordinary NAND gates. But in Schmitt trigger NAND gates, transition from one logic level to another takes place at Lower Trigger Point (LTP) and Upper Trigger Point (UTP) voltages at the input. A LOW to HIGH transition of the inputs takes place at VUTP and a HIGH to LOW transition of input takes place at VLTP. In other words, the gate switches at separate voltages for positive and negative going signals.
2.2
Pulse Sorter Block

The PULSE OUT from the debounce network is fed to PULSE SORTER block which
separates LONG and SHORT pulses with the help of an analog circuitry. The PULSE SORTER block produces separate outputs for LONG press and SHORT press. The LONG or SHORT LINE gets activated accordingly. These outputs connect to the AND-OR select gates.
2.3
Pulse Selector Block

The PULSE OUT line of the debounce network clocks a decade counter with decoded
outputs. Each press of the button clocks the counter. The count output lines are use to steer the LONG and SHORT LINES into another decade counter with decoded outputs through ANDOR select gate. As the first counter steps through its counts, certain of its output positions represent LONG pulse. Unconnected lines represent SHORT positions. This coding arrangement sets the combination. The count out lines of LONG positions are ORed and the result is used to channelize the LONG LINE through an AND gate into the clock input of second counter. Negated version of the ORed output is used to channelize the SHORT LINE.
2.4
Reset Block
The functions of the RESET block are: To start the system in the waiting interval when powered up. Reset the system if the user takes more than 3 seconds between two consecutive presses. Ensure that the system is reset at the end of 8 presses. Keep the system in wait mode for 5 seconds after every system reset. 3 AWH EC, Calicut
Department of ECE
The RESET block takes PULSE OUT and COUNT OUT line from the first counter IC as its inputs and produces a RESET command at the output which is connected to both the counters.
2.5
Output Block
The AND-OR select gate produces an output only if the code is entered in the
programmed sequence. The second counter counts the output of the AND-OR select gate and produces a unlock/lock command only if it counts all the eight pulses. The unlock/lock command is a HIGH pulse of brief duration. This command is applied as clock to a JK flip flop to toggle its output. The JKFF output remains HIGH until the system is locked by entering the same code or due to a power outage. The output of the JKFF activates the relay, which controls any electrical load or door lock.
2.6
Logic Family Used in the Design CMOS Logic

The ICs used in the designed system is of the CMOS family. Two important
characteristics of CMOS devices are high noise immunity and low static power consumption. Significant power is only drawn when the transistors in the CMOS device are switching between on and off states. Consequently, CMOS devices do not produce as much waste heat as other forms of logic, for example transistor-transistor logic (TTL) or NMOS logic, which uses all n-channel devices without p-channel devices. CMOS uses complementary and symmetrical pairs of p-type and n-type metal oxide semiconductor field effect transistors (MOSFETs) for logic functions. CMOS is widely used for general purpose logic circuitry.
2.7
The Circuit Diagram of the System

The complete circuit diagram of the Single Button Electronic Lock is shown in Fig. 2.2.
Different blocks in this diagram will be explained in detail in subsequent chapters.
Fig. 2.2 Complete Circuit Diagram of Single Button Electronic Lock
3. CIRCUIT OPERATION
This Chapter explains the operation of various circuit blocks involved in the Single Button Electronic Lock System in detail.
The Debounce Block

The S-R (SET- RESET) Latch A latch is a type of bistable logic device or multivibrator. The S-R latch has two outputs labeled and and two inputs labeled S and R. The state of the latch corresponds to the level of (HIGH or LOW, 1 or 0) and is of course, the complement of that state. It can be constructed using either two cross coupled NAND gates or two cross coupled NOR gates. Using two NOR gates, an active HIGH S-R latch can be constructed and using two NAND gates an active LOW S-R latch can be constructed. The name of the latch, S-R or SETRESET, is derived from the name of its inputs.
Fig. 3.1 (a) Active High S-R latch
(b) Active LOW S-R latch
For an active LOW S-R latch, when the output is high, the latch is in SET state. It will remain in this state indefinitely until a LOW is temporarily applied to R input. With a LOW on R input and a HIGH on S, the output of the gate G2 is forced HIGH. This HIGH on output is coupled to one of the input of G1, and since the S input is HIGH, the output of G1 goes LOW. This LOW on the output is then coupled back to the input of G2, ensuring that the output remains HIGH even when the LOW on the R input is removed. When the output is LOW, the latch is in RESET state. Now the latch remains indefinitely in RESET state until a LOW is applied to S input. In normal operation, the outputs of a latch are always complements of each other. An invalid condition in the operation of active LOW S-R latch occurs when LOWs are applied to both S and R at the same time. As long as the LOW levels are simultaneously held on the inputs, both the AND gate outputs are forced HIGH, thus violating the basic 6 Department of ECE AWH EC, Calicut
complementary operation of the outputs. Also, if the LOW s are released simultaneously, both outputs will attempt to go LOW. Since there is always some propagation delay time of the gates, one of the gate will dominate in its transition from LOW output state. Thus in turn forces the output of the slower gate to remain HIGH. In this situation, you cannot reliably predict the next state of the latch. The table summarizes the logic operation in truth table form. The operation of active HIGH input NOR gate latch is similar but requires the use of opposite logic levels. S 0 0 0 0 1 1 1 1 R Qn Qn State 0 0 X Indeterminate (Invalid) 0 1 X 1 0 1 Set 1 1 1 0 0 0 Reset 0 1 0 1 0 0 No Change 1 1 1 Truth table of an active LOW S-R latch
Latch as a contact bounce eliminator Fig. 3.2 Circuit Diagram of Debounce Block
U1A R1 100K +12V U1B Pulse
R2 100K S1
An example of S-R latch is in the elimination of mechanical switch contact bounce. When the pole of the switch strikes the contact upon switch closure, it physically vibrates or bounces several times before finally making a solid contact. Although these bounces are very short in duration, they produce voltage spikes that are often not acceptable in digital systems. An S-R latch can be used to eliminate the effects of switch bounce as shown in Fig. 3.2. The switch is normally in position 1, keeping the S input LOW and the latch SET. When the switch is pressed to position 2, S input goes HIGH because of the pull-up resistor to Vcc, and R input goes LOW on the first contact. Although R remains LOW only for a very short time 7 Department of ECE AWH EC, Calicut
before the switch bounces, this is sufficient to RESET the latch. Any further voltage spikes on the R input due to switch bounce do not affect the latch, and it remains in RESET. It is noticed that the output of the latch provides a clean transition from HIGH to LOW thus eliminating the voltage spikes caused by contact bounce. Similarly, a clean transition from LOW to HIGH is made when the switch is released to position 1. The output is taken as the pulse input to the rest of the blocks.
Pulse Sorter Block
Fig. 3.3 Circuit Diagram of Pulse Sorter Block The output from the debounce circuit may be either a long or short pulse. The pulse sorter block differentiates the long and short pulses and activates long or short line accordingly. All switch presses greater then 0.6 second causes the LONG LINE to go LOW for a brief time period (~10ms). Similarly, for all press less than 0.4 second will cause a momentary LOW pulse (~10ms) to appear on the SHORT LINE. The circuit that is contained in this block is shown in Fig. 3.3.
Single Button Electronic Lock Formation of Long Line Output Case 1:
The button is not pressed, i.e. pulse signal is HIGH. The diode D3 is forward biased. So capacitor C2 charges through resistor R6 to 12V. Thus the input of LONG GATE in the Long Line path is HIGH. The output of this gate is NANDed with the pulse signal to form the long pulse output. In this case the LONG GATE output is LOW and this is NANDed with the HIGH input pulse which causes the output at the LONG LINE to be HIGH. Case 2: The button is kept pressed for > 0.6 sec, i.e. pulse signal LOW for > 0.6 sec. The diode D3 is reverse biased so the capacitor discharges through R4 from 12V to 0V. Till the capacitor voltage is above the lower trigger point voltage of the Schmitt NAND gate (4.44V approx for 12V supply), the input to the LONG GATE remains HIGH which causes the LONG LINE to remain HIGH. When the capacitor voltage crosses the lower trigger point (0.6 sec is enough for this to happen), the input to the LONG GATE switches to LOW causing the output to be HIGH. The HIGH output of the LONG GATE is NANDed with the pulse input (LOW). Thus the LONG LINE output remains HIGH. The capacitor continues to discharge to 0V. Case 3: The pulse signal goes high when the button is released. Now the LONG GATE output (HIGH) and the HIGH input pulse appears as inputs to the NAND gate causing a HIGH to LOW transition on the LONG LINE. In this case, the diode D3 is forward biased and the capacitor stops discharging and start charging to 12V through resistor R6. Until the capacitor voltage reaches above the upper trigger point voltage of the Schmitt NAND gate (8.2V approx for 12V supply), input at the LONG GATE remains LOW causing the LONG LINE to remain LOW. Capacitor voltage on reaching upper trigger point, the input of the LONG GATE switches to HIGH causing a LOW to HIGH transition on the LONG LINE. Use of D3 & R6: If the charging was through R4, charging time constant is as high as about 470ms. Thus the charging will be slow. During charging process, even if a SHORT press is entered, it will be misinterpreted as a LONG press. The charging time of the capacitor through R6 is less and thus a LOW pulse of about 30ms is obtained on the LONG LINE. 9 Department of ECE AWH EC, Calicut
Single Button Electronic Lock Response of the circuit to short press:
The LONG pulse sorter circuit does not respond to a short input pulse. This can be explained as follows. When a short pulse is encountered, the capacitor C2 starts discharging. But before the capacitor voltage drains out to lower trigger point voltage of the Schmitt NAND gate, the button is released and the pulse input goes high. The capacitor again charges back to 12V. Thus the input at the LONG GATE remains HIGH causing the LONG LINE to remain HIGH. Simulation Results: This circuit block was simulated using Orcad Pspice 9.1. A Digital Stimulus Source DigStm available from SOURCSTM library was used instead of switch mechanism to implement the pulse input. This source function can be edited with the help of Stimulus Editor program that is contained in Orcad Pspice package. The DigStm source was edited to input various long-short combinations to the circuit to verify correct operation of the circuit under all possible operating conditions. Fig. 3.4 obtained from such a simulation shows the process of long line output formation clearly. On a long pulse of ~0.8 sec C2 discharges to 3.7 V well below the lower trip point of NAND gate thereby producing a level transition in the LONG LINE output when pulse signal goes back to HIGH. However, on a short pulse of ~0.2sec C2 discharges only to 8.9 V thereby preventing a level transition in the LONG LINE output.
Fig. 3.4 Simulation output showing formation of long line output Formation of Short Line Output Case 1: The button is not pressed, i.e. the pulse signal is high. The diode D2 is in forward bias and thus the capacitor C3 charges through resistor R5 to 12V. Also, capacitor C1 charges through resistor R1. Since the diode D1 is reverse biased, the voltage drop across resistor R2 is zero. Thus one of the SHORT GATE input is LOW. This causes the SHORT GATE output to be HIGH. Case 2: The button is kept pressed for < 0.4 sec, i.e. the input pulse is LOW for < 0.4 sec. The diode D2 is reverse biased. The capacitor C3 discharges through R3. The RC time constant of the discharge path is so adjusted that the capacitor voltage does not reaches the lower trigger point voltage of the Schmitt NAND gate before the short press is released, thus holding second input of the SHORT GATE HIGH. The capacitor C1 discharges to 0V through the parallel 11 Department of ECE AWH EC, Calicut
combination of R1 and R2. A voltage of 0.5V appears at the first input of the SHORT GATE which is considered as LOW. Thus the SHORT GATE output remains HIGH. Case 3: The pulse signal goes HIGH when the button is released. The capacitor C1 is initially at 0V. It acts momentarily as a short circuit for the sudden transition of the pulse from 0V to 12V. Thus first input of the SHORT GATE switches from LOW to HIGH. This produces a HIGH to LOW transition at the SHORT GATE output. Capacitor C1 charges through resistor R1 and C3 through R5. The pulse on the SHORT LINE remains LOW until the SHORT GATE input voltage decays to lower trigger point voltage of the Schmitt NAND gate. After this point, the first input of the SHORT GATE switches to LOW causing the output to switch form LOW to HIGH. Response of the circuit to long press: In this case C3 discharging through R3 during the switch pressed period will go below the lower trip point of NAND gate and the gate input will recognize it as a LOW signal. At the release of switch the pulse signal goes HIGH and produces a short duration pulse at the other input line of NAND gate. Simultaneously C3 charges through R5 and D2. However, gate will not register the C3 voltage as HIGH input unless this voltage goes above upper trip point of NAND gate (because this voltage crossed the lower trip point of NAND earlier). By the time this happens the short duration pulse that appears at the other input of NAND gate would have tapered down to a value lower than lower trip point of gate. Thus the NAND gate goes through (0,0) input just before switch release, (1,0) just after switch release and (0,1) after some time. Thus, the SHORT LINE output does not record any level transition.
Fig. 3.5 shows the simulation output in the SHORT LINE path for the same set of conditions as under Fig. 3.4.
Fig. 3.5 Simulation output showing formation of short line output
Response to Medium Length Pulse Input A switch press lasting between 0.4 sec to 0.6 sec produces a medium length pulse in pulse line. In this case the capacitor C2 in long line path does not discharge down to lower trip point of NAND gate. Thus, the long line output will not register any level transition. However, the capacitor C3 in short line path will get enough time to discharge to below the lower trip point of NAND gate while the pulse signal is LOW. Thus, the short line output also will not register any level transition. Fig. 3.6 that shows the simulation output for a medium length pulse input (0.5 s) illustrates these points.
Fig. 3.6 Simulation output for a medium length switch press operation
The Pulse Selector Block

The circuit diagram of Pulse Selector Block is given in Fig. 3.7 Fig. 3.7 Circuit Diagram of Pulse selector Block
The Pulse Selector Block consists of a decade counter with decoded outputs and a longshort selector. 3.3.1 The Decade Counter CD4017BC is a 5 stage divide by 10 Johnson counter with 10 decoded outputs and a carry-out bit. These counters are cleared to zero state by a HIGH on their reset line. This counter advances on the positive edge of the clock signal when the clock enable signal is in the LOW state. The decoded outputs are normally in the LOW state and go to HIGH state only at their respective counts. The decoded outputs remain high for one full clock cycle.
The pulse signal from debounce circuit is given as the clock input (pin no 14) to the counter. Whenever the switch is pressed and released a positive edge clock signal is received by the counter at the switch release. The counter produces a HIGH output at the appropriate output pin; i.e. for the 1st positive edge (at the end of 1st button press) first HIGH output is obtained at pin no: 2. Rest of the output pins remain at LOW state. Similarly for second positive edge (2nd button press) second HIGH output is obtained at pin no: 4. Rest of the output pins are at LOW level. The outputs of the decade counter are hardwired to four repeated long-short sequences; i.e. the assumption is that the pin numbers 2,7,1,6 will have HIGH output only when a long press is entered. Therefore the output pins 2,7,1,6 are combined into OR operation via an OR gate. 3.3.2 Long - Short Selector Selector circuit consists of an AND-OR gate configuration. The assumed long output lines of the decade counter are connected via OR gates (three two input OR gates are used to implement a 4-input OR gate). This 4-input OR gate output is one input to an AND gate (Gate A). The other input is the long pulse signal line from the pulse sorter block. Whenever the 4input OR gate output is HIGH i.e., at the end of 1st , 3rd, 5th and 7th switch press operations) the long pulse line is connected to Counter-II as clock input by AND gate A and OR gate C. A negated version of 4-input OR gate output is one input to the AND gate B and the second input is the short pulse signal line from Pulse Sorter Block. Whenever the 4-input OR gate output is LOW i.e., at the end of 2nd , 4th, 6th and 8th switch press operations) the short pulse line is connected to Counter-II as clock input by AND gate B and OR gate C. The AND gate with both inputs shorted together in the long line path is placed there to equalize the propagation delays in two paths in order to prevent short duration glitches at the clock_in line of the Counter-II. The button is pressed and then released. Assume the press is a long-press. The pulse sorter block operates and gives a HIGH to LOW pulse with a low pulse width approx. 30 ms at the long pulse line output. The short pulse line output remains at logic 1. This implies long pulse is detected at the long line and the long line has a HIGH-LOW-HIGH pulse transition output. The pulse signal is fed as the clock signal of the Counter-I (the counter shown in Fig. 3.7). Upon receiving the first low to high transition the counter makes its first output line i.e. pin no: 2 high. This high pulse enables the long pulse signal to reach the Counter-II (this 16 Department of ECE AWH EC, Calicut
counter is not shown in Fig. 3.7. It is a part of the Output Block) clock line through AND-OR gate. The button is pressed for the 2nd time and released. Assume it is a short press. The short pulse line output of pulse sorter block gives a HIGH-LOW-HIGH transition output. Long pulse line output of pulse sorter block remains at logical 1. In the Counter-I (the counter shown in Fig. 3.7) the 2nd press is the second clock pulse. So, counter makes the 2nd output line (pin no.4) HIGH and the rest of the output lines are at LOW state. Thus, all the long output pins of counter are at LOW state. So, the output of the 4-input OR gate is 0. Therefore, the AND gate labeled A gives a LOW output. The 0 output of 4-input OR gate is inverted to get output 1. This HIGH output permits the short pulse line to become the clock_in for Counter-II through the OR gate labeled C. Similarly, if the button is pressed in the correct LSLSLSLS sequence 8 low to high transitions will be obtained as the clock for the second counter (clock to second counter is denoted by clock_in in the Fig. 3.7). If an incorrect code is pressed, say LLLSLSLS the clock_in will receive only 7 low to high transitions. At the end of second press a HIGH-LOW-HIGH transition appears in the long pulse signal line and no such transition appears in the short pulse signal line. However, the Counter-I outputs + 4-input OR gate is hard-wired such that at the end of second press the short pulse signal line will be passed on to the output of the block to appear as c-clock_in of the Counter-II in the output block. Therefore, Counter-II receives the short pulse line as clock and there is no transition in that line. Thus, the Counter-II does not count the second buttonpress. The rest of the pulse sequence is according to the hard-wired sequence. So the clock_in signal line delivers 7 rising clock edges to Counter-II in Output Block 4 from long pulse signal line and 3 from short pulse signal line. Counter-II will count up to 7 only and hence the output JK FF will not be affected.
3.4
The Output Block

The circuit diagram of Output Block with the Power-ON Reset for output FF is shown
in Fig. 3.8.
Fig. 3.8 The Output Block with Power-ON Reset included The Output block consists of a CD4017 decade counter (Counter-II) and a JK flip flop connected in toggle mode .The CD4017 decade counter is the second decade counter used in the system. The clock to the counter is the clock_ in signal from the Pulse Selector Block. The reset signal for this counter comes from the RESET block output line. The 8th decoded pin output of the counter is the clock input for the JK flip flop.
Single Button Electronic Lock 3.4.1 The JK Flip Flop: The truth table of the JK flip flop is shown below.
J
0 0 0 0 1 1 1 1
K
0 0 1 1 0 0 1 1
Qn
0 1 0 1 0 1 0 1
Qn+1
0 1 0 0 1 1 1 0
Truth Table of a JK Flip-flop From the truth table it is clear that the JK flip flop always changes state with clock when J = K= 1. The JK flip flop toggles each time a valid clock pulse occurs. The RESET and SET terminals are the non-synchronous inputs to the flip flop. The output response to SET and RESET terminals is independent of the J and K inputs. In this case the flip flop is in toggle mode. A power on reset is provided at the RESET pin of the flip flop. The power supply voltage which appears across the resistor at the reset pin on application of DC power resets the FF to LOW. The capacitor charges to the Vdd voltage (in about 3ms) and a low voltage appears at the reset pin after that. This deactivates the reset pin and the JK flip-flop operates in the toggle mode operation subsequently.
When the correct code sequence LSLSLSLS is entered the clock_in is a series of 8 LOW to HIGH pulse transitions. This clocked to the second counter gives HIGH output at the corresponding output pins. During the 8th clock pulse (.i.e., 8th correct press) the counter in Fig. 2.8 makes its 8th decoded output pin HIGH. This output HIGH pulse is the unlock/lock signal. This HIGH output is the clock of the JK flip flop. The JK flip flop is in toggle mode .i.e., both J and K are in HIGH state. The HIGH clock output activates the JK flip flop. When the J , K inputs and the clock are in HIGH state the output of the JK flip flop is the inverted earlier output state. Since the earlier output state was LOW (due to Power-ON Reset) the present output Q is HIGH. During testing this HIGH output was used to drive the anode of a white LED via an 8.2K resistor.
When an incorrect code sequence say LLLSLSLS is entered the pulse selector block misses a long pulse and the clock_in gets only 7 LOW to HIGH pulse transitions. Thus, the 8th pin output of the Counter-II is LOW (since there is no corresponding clock pulse). Therefore, the clock input to JK flip-flop does not get any transition edge. So it continues to remain in earlier LOW state output. The lock or unlock command is not issued and the white LED does not glow.
3.5
The Load Block
Fig. 3.9 Circuit Diagram of the Load Block A relay is an electrically operated switch. Relays are used where it is necessary to control a circuit by a low-power signal (with complete electrical isolation between control and controlled circuits), or where several circuits must be controlled by one signal. A simple electromagnetic relay consists of a coil of wire surrounding a soft iron core, an iron yoke which provides a low reluctance path for magnetic flux, a movable iron armature, and one or more sets of contacts (there are two in the relay pictured). The armature is hinged to the yoke and mechanically linked to one or more sets of moving contacts. It is held in place by a spring so that when the relay is de-energized there is an air gap in the magnetic circuit. In this condition, one of the two sets of contacts in the relay pictured is closed, and the other set is open. Other relays may have more or fewer sets of contacts depending on their function. The relay in the 20 Department of ECE AWH EC, Calicut
picture also has a wire connecting the armature to the yoke. This ensures continuity of the circuit between the moving contacts on the armature, and the circuit track on the printed circuit board (PCB) via the yoke, which is soldered to the PCB. When an electric current is passed through the coil it generates a magnetic field that attracts the armature, and the consequent movement of the movable contact(s) either makes or breaks (depending upon construction) a connection with a fixed contact. If the set of contacts was closed when the relay was deenergized, then the movement opens the contacts and breaks the connection, and vice versa if the contacts were open. When the current to the coil is switched off, the armature is returned by a force, approximately half as strong as the magnetic force, to its relaxed position. When the coil is energized with direct current, a diode is often placed across the coil to dissipate the energy from the collapsing magnetic field at deactivation, which would otherwise generate a voltage spike dangerous to semiconductor circuit components. A 12V DC relay with a contact rating of 10A rms was used in this Project. The relay coil has 400 Ohms resistance and will take about 30 mA from 12 V supply. A BC107 transistor with a base resistance of 10k was used to drive the coil. A 1N4002 diode was connected across the coil to absorb the magnetic energy of the coil when the transistor switch is switched off. The AC load used in the Project was a lamp rated for 230V, 50Hz AC supply.
The Reset Block

The RESET block uses Monostable circuits for generating Reset signal. Two Monostable circuits are used (generated using Schmitt NAND gates). 3.6.1 Monostable Using Schmitt NAND Gate To use a Schmitt NAND as a Monostable one input line of the NAND is permanently in high state and the other input line is connected to an RC network. One end of the resister is connected to ground and the other to input line. One end of the capacitor is connected to input line and the other to the trigger input. See Fig. 3.10. The diodes shown in the Fig. 3.10 are the internal protection diodes inside the CD4093 IC. Similar diodes are connected internally at the other input pin too; but they are not shown in the figure.
Fig. 3.10 A Positive Edge Triggered Monostable Using Schmitt NAND Gate For a positive edge-triggered Monostable the trigger input should be normally LOW and then it should go HIGH. Monostable triggers at that edge. When input is LOW for sufficiently long duration, the Capacitor charges to zero volts. Therefore, the NAND gate second input is LOW. Therefore the output of the gate is HIGH. That is, the stable state of Monostable is HIGH. When the trigger input suddenly goes from LOW to HIGH, since the capacitor cannot change its voltage instantaneously, all the jump in input appears across the resistor. That is, the second input of NAND gate goes HIGH. So its output goes LOW. Now the capacitor will charge from the HIGH input through the resistor thereby increasing the voltage across the capacitor and decreasing the voltage across the resistor. When the voltage across the resistor reaches the lower triggering voltage of the Schmitt NAND gate output of the gate changes state and goes back to HIGH. Therefore, the time for which the output remains LOW is the time taken by the capacitor to charge to (Vdd-VLT ) charging from Vdd through R. VLT of NAND Schmitt is designed to be approximately 37% of Vdd. This time will be approximately one time constant = RC. Even after the Monostable times out the capacitor continues to charge and complete charging if the input continues to be HIGH. When input pulse goes LOW again the fully charges capacitor gets connected to Ground with +ve polarity and Vdd appears at the NAND gate input. At this point the protection diode internally connected within the NAND gate with its cathode at the input and the anode at Ground will quickly discharge the capacitor to near zero, thereby preparing it for next triggering.
Operation of the Reset Block The circuit diagram of the Reset Block is given in Fig. 3.11. 22 Department of ECE AWH EC, Calicut
Fig. 3.11 The RESET Block Circuit Diagram This circuit works in three modes. Mode 1: Switch in un-pressed condition (i.e., no code entry taking place) PULSE signal is HIGH under this condition. Assume that the second Monostable U5 in Fig. Output is in stable state, i.e., HIGH. The AND gate passes on Vdd to R2-C3 circuit. C3 charges and when it reaches the upper trigger point of Schmitt NAND gate ( after 3.3 sec in the design) the U1 output goes LOW. The signal count-out will go from LOW to HIGH only at the end of 8th switch-press. When the switch is inactive, the count-out signal is always LOW. Therefore, U3 output is HIGH. Now U2 inputs are logical 0 and logical 1 (it was 1 and 1 before capacitor reached VUT). Therefore, when capacitor reaches VUT, U2 output goes from LOW to HIGH causing triggering of first Monostable U4. Its output goes from HIGH to LOW and remains LOW for about 50ms. At the end of 50ms U4 output goes from LOW to HIGH causing second Monostable to trigger. Second Monostable output goes normal HIGH state to LOW state. Immediately R2 C3 is shorted to Ground and C3 empties through D1 , making U2 input (1,1) and U2 output LOW. This ensures that second Monostable U5 is not disturbed further and is allowed to complete its timing (that is about 5 seconds in the design). RESET signal is the inverted output of the second Monostable U5. This is sent to both CD4017 counters as Reset signal making any switch-press during this 5 sec interval ineffective.
At the end of 5 secs the second Monostable times out. Its output goes HIGH and the entire cycle starts all over again. Thus, in this mode the circuit behaves as an oscillator. The RED LED connected at the output of U6 (not shown in the Fig. 3.11) indicates the RESET state. The GREEN LED connected to U5 output (not shown in Fig. 3.11 ) indicates the period during which code input can start. 23 Department of ECE AWH EC, Calicut
Single Button Electronic Lock Mode 2 - Case 1: User inputs code without over-delay
In this case user must have started inputting the code when the second Monostable is in normal state (that is , when GREEN LED was ON). Therefore, the pulse signal will be passed on to R2-C3 by the AND gate. Whenever the switch is pressed C3 goes to 0V through D1. Between the switch-presses C3 charges. If the user does not wait for more than 3.5 sec between two successive presses C3 will not get a chance to charge to VUT of the Schmitt NAND gate. Therefore, the first Monostable will not get trigger from that path. The trigger signal for this Monostable is the ORd output from two input signals one from R2-C3 path and another from the count-out signal path. This OR gate is realized by using three NAND gates (U1 , U2 and U3). By De Morgans theorem (AB) = A + B Therefore, the only way the first Monostable can get triggered is by count-out (8th coded output of first CD4017 counter, indicating that 8 switch-presses have been executed) going HIGH. count-out goes HIGH when the user releases the switch after 8th press. It will remain HIGH till the counter is RESET or the user presses the switch 9 th time. At the rising edge of count-out first Monostable gets triggered and after ~50ms the second Monostable gets triggered. Once the second Monostable is triggered, the counters get RESET. It is unlikely that a user can press a switch within 50ms of pressing and releasing it once. Therefore, the system will enter RESET mode once the user enters 8 switch-presses. He may have entered the code correctly. In that case the second counter must be given a chance to count to 8 and thereby toggle the output flip-flop before the system enters RESET mode. The first Monostable timing period of 50ms is provided for this purpose only. Note that the output flip-flop is not subject to this RESET. Mode 2 - Case 2: User inputs code with excessive delay In this case, when the user leaves more than 3.5 sec between two successive presses, C3 charges to VUT and puts the entire system in RESET mode even before he can input 8 presses. Subsequent code entry will be ignored and the user has to start all over again after the system comes out of RESET. Mode 3 - Power-ON condition Before powering ON all capacitors are carrying 0 V. U2 output immediately after power is switched ON is 0. C1 is holding 0V. Therefore, R1 voltage is 0V. So first Monostable output 24 Department of ECE AWH EC, Calicut
is HIGH immediately after power comes ON. It was 0 before power was switched ON. That is , the first Monostable output registers a change from 0 to 1 immediately on switching ON the DC power supply to the system. Thus, the second Monostable gets a trigger input (LOW to HIGH transition) immediately after power is ON. Therefore, the second Monostable starts timing and puts the system in RESET mode after the power is switched ON. This is the reason why a Power-ON RESET is not arranged for the two CD4017 counters. However, the output toggle flip-flop does not get a RESET from the RESET block and a separate Power-ON reset is arranged for this flip-flop in the output circuit.
3.7
Operation of the System

The Switch is connected to a Debouncing circuit. The normal output of this circuit
when the Switch is in un-pressed condition is HIGH. When the Switch is pressed, the output changes level to LOW and remains LOW as long as the Switch is held pressed. The output goes back to HIGH state when the Switch is released. Thus, the Debounce circuit converts the Switch press into a normally HIGH digital signal that goes LOW and remains LOW for the duration of Switch press. This signal is denoted by pulse here onwards. The Switch press operation is classified into three categories based on the duration for which the Switch is held in pressed condition. If it is held for < 0.4 sec the resulting pulse signal is a short pulse. If it is held for > 0.6 sec, the resulting pulse signal is a long pulse. If it is held for a period more than 0.4 sec but less than 0.6 sec, the resulting pulse signal is a medium pulse. Medium pulse is not used in the code sequence. Only long and short pulses are used in forming the code sequence. If medium pulse is entered while code entry, the code entered will get interpreted as a wrong code. The code is formed by pre-deciding the sequence of long and short pulses and the total number of pulses that the user has to enter. The pulse signal is sorted into two separate signal lines called the short line and the long line - by analog and digital circuitry. Both lines are normally in the HIGH state. When the Switch is pressed and the resulting pulse signal is a long pulse, the long line signal goes from its normally HIGH state to LOW state for a few milliseconds starting from the instant at which the Switch is released whereas the short line signal will continue to remain HIGH. Similarly, when the Switch is pressed and the resulting pulse signal is a short pulse, the short line signal goes from its normally HIGH state to LOW state for a few milliseconds starting from the instant at which the Switch is released whereas the long line signal will continue to remain
HIGH. If the pulse signal is a medium pulse, both long line and short line signals will continue to remain HIGH. The pulse signal is used to advance the count in a decade counter (Counter-I) with decoded outputs. The counter is clocked at positive edge. Thus, the counter advances count when the Switch is released from pressed condition. The decoded outputs of this counter are normally LOW and go HIGH at the relevant count. When the user enters the 8 th code entry and releases the Switch, the 8th decoded output of the counter goes HIGH and remains HIGH till the counter is reset or the user enters 9th press. But the system is designed such that the user will not be able to enter 9th switch-press and the system goes to RESET mode at the end of 8th press. This RESET action is initiated by the 8th decoded output of the counter going HIGH. Assume that the code sequence is LSLSLSLS where L stands for a long press and S stands for a short press. In this case, the decoded outputs 1,3,5,7 of Counter-I are connected as inputs to a 4-input OR gate. When the output of this OR gate is HIGH, the long line signal is passed on as the clock_in signal of a second decade counter with decoded outputs (Counter-II). When this OR gate output is LOW, the short line signal is passed on as clock_in signal of Counter-II. An AND-OR Selector gate performs this function. Thus, if the user actually enters LSLSLSLS, Counter-II will get 8 clock pulses and its 8th decoded output will go from its normal LOW state to HIGH state and will remain HIGH till it is reset. The LOW to HIGH transition on 8th decoded line in this counter is used to toggle a JK FF that had been reset by a power-on reset mechanism. The JK Toggle FF output is used to drive a transistor switch that powers the relay coil. The relay contact in the load circuit closes, thereby powering the AC load. Power to this load will get switched off when the same code is successfully entered once more. However, assume that the user entered LSLLLSLS instead of LSLSLSLS. In this case, at the end of 4th press the system will connect the short line signal to clock input of Counter-II. But since the user entered L instead of S, the short line will not contain any transition. The level transition is actually on long line. Thus, the Counter-II will get three count pulses from short line and 4 count pulses from long line and will count only up to 7 before reset. Therefore, its 8th decoded output does not register any transition and the output of JK FF state is unaffected. The user is permitted to enter only 8 presses at a stretch. This is implemented by putting the entire system in the RESET mode for about 5 seconds after the user releases the 8th switch press. Both the decade counters (but not the output JK FF) get reset at the beginning of 26 Department of ECE AWH EC, Calicut
RESET mode and continue to remain in that condition during the entire RESET mode. Switchpresses during this interval are simply ignored. However, the user may have entered the code correctly and the output has to be activated before putting the system in RESET mode. This is ensured in the RESET circuitry. Reset signal is issued to the counters only after the Counter-II gets enough time to toggle the output JK FF in the event of correct code entry. However, the time delay provided for this purpose is not enough to permit the user to press the switch 9th time after releasing the 8th press. The reset circuitry also forces the user to enter the switch-presses without exceeding the time limit between successive presses. If user takes more than 3 seconds between two presses, the RESET circuit puts the system into RESET mode, thereby forcing the user to wait for 5 seconds before he can try again. Further, the reset circuitry ensures that the system starts up in RESET mode on powering up.
4. HARDWARE DESIGN
The selection of components in various blocks is described in this Chapter. The various specifications are listed below. Maximum Short pulse duration = 0.4 sec Minimum Long pulse duration = 0.6 sec Maximum time delay between two successive button presses = 3.5 sec Minimum Wait Interval = 5 sec
4.1
Selection of Components in Pulse Sorter Block
Selection of R4, R6 and C2 in Long Line path
R4 and C2 must be such that the discharging capacitor must reach VLTP of Schmitt NAND from Vdd only after 0.6sec. Solving for , we get,
0.6
VLTP = Vdd e
Substituting Vdd = 12V and VLTP = 4.44V, we get 0.6 sec. A tantalum electrolytic capacitor with low leakage with 4.7 F was available. This was chosen for C2. Considering that there can 0 .6 = V ln dd VLTP be 5% tolerance in component values 150k standard value was chosen for R4. R6 and C2 must be such that C2 will charge up to Vdd before the user can press the switch after releasing it. No user can press a switch within 100ms of releasing it once. Hence time constant of charging path must be around 100ms/2.2 (2.2 times time constant is the rise time of an RC circuit). This is around 45ms. We have already decided that C2 is 4.7 F. Hence R6 must be around 10k. Standard value of 10k is chosen. The width of HIGH-LOW-HIGH pulse in the long pulse signal line is decided by the duration of long press and the time constant R6C2. The minimum width is the time required by C2 to charge from Vdd to VUTP starting from VLTP. The maximum width is the time required by C2 to charge from Vdd to VUTP starting from 0. The expression for this width may be derived as 28 Department of ECE AWH EC, Calicut
T = R6C 2 ln
Vdd Vo Vdd VUTP
Where Vo = 0 for maximum width and VLTP for minimum width. Substituting relevant values, we get the minimum width as ~25 ms and maximum width as ~47ms.
Selection of R3, R5 and C3 in Short Line path R3 and C3 must be such that the discharging capacitor must reach VLTP of Schmitt NAND from Vdd only after 0.4sec. This requires the time constant to be ~ 0.4 sec. A 1F electrolytic capacitor was chosen for C3. Considering component tolerances, it was decided to try 330k for R3 and change it to 390k if required during testing stage. R5 and C3 must be such that C3 will charge up to Vdd before the user can press the switch after releasing it. Any resistance in the range 10k 50k is enough for this purpose. 33k is chosen.
Selection of R1, R2 and C1 in Short Line path When pulse goes HIGH on switch release, the voltage across R1 jumps to Vdd and then decreases exponentially with a time constant R1C1. The maximum width of short pulse is decided by the time taken for this resistor voltage to reach VLTP. That will be about one time constant. However this time constant must be lower than 0.5R5C3 to ensure that if C3 voltage touched VLTP (indicating that the switch-press was not short), then it should not charge up to VUTP before voltage across R1 goes down to VLTP. Hence R1C1 is taken as 10 ms. C1 is chosen as 0.1F ceramic disc type and then R1 will be 100k. R2 simply limits the discharge current of C1 when the switch is pressed again. It can be in the range 10k 100k.
4.2
Selection of Components in Reset Block

The components R2 and C3 in the Reset Block ensure that the system in idle state cycles
between about 3 sec of Ready for code input state as indicated by lighted up GREEN LED and about 5 sec of Wait state as indicated by lighted up RED LED. R2 and C3 further decide the maximum permitted time delay between successive switch presses. The time involved is the time taken by C3 to discharge through R2 from Vdd to VLTP. We have seen that this time is roughly one time constant itself. Thus R2C3 must be around 3.5sec. A 10F tantalum electrolytic capacitor with low leakage was available. Therefore R2 29 Department of ECE AWH EC, Calicut
must be 330k. However, experimentally it was seen that a 220k is needed there. This may be due to component tolerances. The pulse width of first monostable must be more than the maximum pulse width in the long pulse and short pulse lines. This value was seen to be 47ms earlier. Hence, the first mono is designed for about 47ms timing by choosing C1 = 0.047F and R1 = 1M. The pulse width of second monostable decides the duration of Reset period. The desired reset period is 5 sec. Then R3C2 must be ~5sec. A 10F tantalum electrolytic capacitor and 470k resistor are chosen.
4.3 ICs
Components List
Sl. NO 1 2 3 4 5
IC NAME CD4093 CD4017 CD4071 CD4081 CD4027
IC DESCRIPTION 2 Input Quad Schmitt NAND gate Decade Counter/Divider Decoded Outputs Quad 2-Input OR gate Quad 2-Input AND gate Dual J-K Master/Slave Flip-Flop with Set and Reset with 10
NOS 3 2 1 1 1
RESISTORS Sl. NO 1 2 3 4 5 6 7 8 9 CAPACITORS Sl. NO 1 2 3 4 5 6 DIODES Sl. NO 1 2 LEDs Sl. NO 1 2 3 OTHERS RELAY STSP PUSH BUTTON SWITCH STDP COLOUR GREEN RED WHITE NOS 1 1 1 TYPE 1N4148 1N4001 NOS 3 1 VALUE 4.7uF 0.082uF 1uF 10uF 0.047uF 0.1uF NOS 1 1 1 2 1 1 TYPE Tantalum Disc Electrolytic Tantalum Disc Disc RESISTOR 1M 470 K 330 K 220 K 150 K 100 K 33 K 10 K 8.2 K NOS 1 1 1 1 1 5 1 2 3
5. PCB DESIGN PROCEDURE

The PCB designing procedure consists of following steps.
Drawing the Circuit Schematic

Drawing of the circuit schematic is done using ExpressPCB schematic capture software. It includes many libraries with thousands of component symbols. Required symbols are selected from the library and placed in the schematic. After placing the components, the interconnections are completed using wire or bus control. Part reference is assigned for each component. Each component has to be assigned footprint or PCB pattern name. The footprint gives actual physical size representation of the components on the PCB artwork.
Design Rule Check and Netlist Creation

After the circuit schematic has been completed with all required information such as part reference and footprints, the design rule check can be used for checking errors in the design. It checks for duplicate part reference, overlapped lines and dangling lines. After the schematic design, it is processed by a program called Netlist Rule Checker which checks for wiring errors. The final operation done before starting PCB artwork is the Netlist creation. A Netlist software or tool takes the circuit schematic as input and generates a list of components used. This can be used as an information source for remaining stages.
Creating the PCB Artwork

The steps involved in creation of PCB layout are Linking the schematic: The schematic developed has to be linked into the PCB software when starting a new design. Operation begins with bringing all component footprints on design screen with a nest of interconnection. This interconnection indicates connection between the pins of components which helps in routing and placing the trace lines.
Drawing the board outline and placing components: Depending upon the density of components and connections, size of the board is designed. Outline of the PCB is drawn accordingly. Now the components have to be placed in optimum positions. The software automatically calculates the minimum interconnection distance through routing.
Routing: It is the process of interconnection of component using copper track of required width.
5.4
PCB Design Issues Using the design software there are cases when connections cannot be given due to
complexity of schematic. In those cases connections are given through net aligning. Power lines are provided with greater width than the signal lines. The next step is post processing. Top layer, bottom layer and the component layer can be viewed separately. 5.5 Soldering Process Soldering is the process of joining the leads of the components to the PCB pads by heat using a filter material for the purpose of making continues and permanent path for the flow of electricity. Make the layout of components in the circuit. Plug in the cord of soldering iron in to the mains to get it heated. Straighten and clean the component leads using a blade or knife. Apply a little flux on the leads. Take a little solder on soldering iron and apply the molten solder on the leads. This process is called tinning. Clean the tip of the soldering iron. Keep the bit always clean form oxide formation while soldering. Do not over heat the PCB and the devices. Soldering must be done in minimum time to avoid dry soldering and heating up of components. Wash the residue using acetone and brush.
Soldering Equipments
Solder Flux Soldering iron 33 Department of ECE AWH EC, Calicut
Single Button Electronic Lock Soldering gun Soldering station
5.6
PCB Layout Fig. 5.1 PCB Layout Diagram Top Layer Copper
Fig. 5.2 PCB Component Placement Diagram
RESULTS
The Single Button Electronic Lock Circuit as per the design explained in earlier Chapters and as per the Bill of Materials detailed in Chapter 4 was wired up in Bread Board and tested. The load that was controlled was an electric lamp working from 230V,50Hz AC Supply. All modes of operation of the circuit were verified experimentally. Under idle condition, the system was seen to light up GREEN LED for 3.5 sec and RED LED for 4.6 sec cyclically. Correct code entry was seen to result in lamp going ON if it was OFF before and lamp going OFF if it was ON before. This was verified by different people entering code at different speeds. Incorrect code entry never resulted in a change in state of the lamp. When the user left a time gap more than 3.5 sec between switch presses, the circuit went into RESET mode immediately. Code entered during RESET mode was ignored by the circuit.
7. CONCLUSIONS
Conclusion
The Single Button Electronic Lock designed and tested in this Mini-Project functioned as per design specifications. It is a technically feasible product.
Future Work
The following modifications can be taken up to improve upon this basic design. The current system allows the user unlimited trials. The number of times a user can try to enter code can be limited to 3 or 4. After 3 or 4 wrong code entries the system should enter a lock-out condition that can be reset only by security personnel. The hard-wired code can be made programmable with the help of DIP switches. This can be done by connecting all the 8 decoded outputs of Counter-I to a 8-input OR gate through selector AND (two input) gates. The selector lines of the 8 AND gates can be set at 0 or 1 by DIP switch setting. The 8-input OR gate output can be used to steer the long pulse and short pulse lines to Counter-II as in the current design. Provision for separate codes for switching ON the load and switching OFF the load may be provided.
8. BIBILIOGRAPHY
1. Christopher E Strangio, Digital Electronics, PHI, New Delhi, 1987. 2. Adel s Sedra, Kenneth C Smith, Microelectronic Circuits, Oxford University Press, New Delhi, 2008. 3. Floyd & Jain, Digital Fundamentals, Pearson Education, 2009. 4. Maxwell Strange, Foulton, MD, Single-Button Lock Provides High Security, EDN Magazine. 5. Datasheets of CD4093, CD4081, CD4017, CD4027 www.datasheetcatalog.com
9. DATASHEETS

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MINI PROJECT REPORT ON EQUIVALENT SERIES RESISTANCE METER

Presented By NAJLA P.R RESHMA K SHOUKEEN A.K SILJIYA K

Department of Electronics & Communication Engineering

AWH ENGINEERING COLLEGE, CALICUT, KERALA UNIVERSITY OF CALICUT

Single Button Electronic Lock

Mini Project Report 2011

AWH EC, Calicut

Single Button Electronic Lock

Mini Project Report 2011

Department of Electronics & Communication Engineering

EQUIVALENT SERIES RESISTANCE METER

AWH EC, Calicut

Single Button Electronic Lock

Mini Project Report 2011

AWH EC, Calicut

Single Button Electronic Lock

Mini Project Report 2011

NAJLA P.R RESHMA.K SHOUKEEN A.K SILJIYA K

AWH EC, Calicut

Single Button Electronic Lock

Mini Project Report 2011

AWH EC, Calicut

Single Button Electronic Lock

Mini Project Report 2011

AWH EC, Calicut

Single Button Electronic Lock

Mini Project Report 2011

User Level Description of the System

1 Department of ECE AWH EC, Calicut

Single Button Electronic Lock

Mini Project Report 2011

2. BLOCK DIAGRAM OF THE SYSTEM

2 Department of ECE AWH EC, Calicut

Single Button Electronic Lock

Mini Project Report 2011

Pulse Sorter Block

Pulse Selector Block

Single Button Electronic Lock

Mini Project Report 2011

Logic Family Used in the Design CMOS Logic

The Circuit Diagram of the System

Different blocks in this diagram will be explained in detail in subsequent chapters.

4 Department of ECE AWH EC, Calicut

Fig. 2.2 Complete Circuit Diagram of Single Button Electronic Lock

Single Button Electronic Lock

Mini Project Report 2011

The Debounce Block

Fig. 3.1 (a) Active High S-R latch

(b) Active LOW S-R latch

Single Button Electronic Lock

Mini Project Report 2011

Single Button Electronic Lock

Mini Project Report 2011

Pulse Sorter Block

8 Department of ECE AWH EC, Calicut

Single Button Electronic Lock Formation of Long Line Output Case 1:

Mini Project Report 2011