1.

Functional Diagrams and Function Symbols*

J. E. JAMISON
(2003)

The purpose of this section is to help the reader establish a uniform means of depicting and identifying mainly digitalbased application software functions used for measurement, monitoring, and control. It is done by presenting a designation system including graphic symbols and identication codes as well as functional diagramming techniques that were formerly known as the Scientic Apparatus Manufacturers Association (SAMA) system. It must be noted that a signicant part of this section has been extracted from the revision work of the ISA SP5.1 subcommittee, and much of it has been based on draft working documents being utilized at the time of this writing, documents with which one of the authors has been actively involved. Other portions of this section are based on the authors experience in the industry and are not any part of the SP5.1 subcommittee proposed forthcoming revision. A disclaimer to any future ISA standards documents is hereby stated: The reader is cautioned that the draft ISA document that provided much of the information in this section has not been approved as of the time of this writing. It cannot be presumed to reflect the position of ISA or any other committee, society, or group.

The intent is to pass along to the reader the best and latest thinking on this subject at this point in time. ISA FUNCTIONAL DIAGRAMMING (EX-SAMA)* Instrument and Control Systems Functional Diagramming Symbol tables are given for use in preparing instrument and control loop functional diagrams, which are not normally shown on process ow diagrams (PFDs) and piping and instrument diagrams (P&IDs). They are used to depict monitoring and control loops in functional instrument diagrams, functional logic diagrams, application software diagrams, sketches, and text. They shall be prepared from the following: a) Instrument line symbols b) Instrument functional diagramming symbols c) Mathematical function block symbols Equivalent P&ID Loop, Functional Instrument and Electrical Diagrams See statement of permission in the footnote below. a) P&ID loop schematic:

71

LT

LSH 01 Start

LSL 01

LIC 01

HS 01B-1 Stop H-O-A

01A 01

SP FT FIC 01 FV

01B-2

HS

HS

01

01

FO

* Used with permission of the Instrumentation, Systems and Automation Society.

31
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General Considerations

b) Functional instrument diagram:

LT
*01

FT
*01

H/ L

A N D

A K I
HS*1A

Auto

A N D
NOT

OR

NOT

I
HS*1B-1

Start

A N D

OR

A N D

Start Pump

HS*1B-2

Stop

A N D

Overload

S R

NOT

F(x)

Reset

c) Electrical schematic diagram:

START HS-01B-1

M1 STOP HS-01B-2 LSL-01 H 0 HS-01A OL M

M2 LSH-01

Note: There is no equivalent electrical schematic for the process control instrumentation. Functional Diagramming Symbol Tables* The symbols used in Table 1.2a are not normally used on P&IDs but are used to diagram control systems at the
*The symbols have been extracted by ISA, with permission, from Scientic Apparatus Manufacturers Association SAMA Standard PMC 22.11981, Functional Diagramming of Instrument and Control Systems, which is no longer supported by SAMA.

hardware and function level for conguration and other purposes. The symbols in Table 1.2b are never used in P&IDs and are used to help document and diagram logic control designs and narratives. The present standard ISA S5.2 (ANSI/ISAS5.21976 [R1992]) is now being revised and rolled into the new ANSI/ISA-5.01.01 standard as proposed in the current (as of this writing) Draft 4. Symbols, truth tables, denitions, and graphs used in this section are in accordance with Draft 4 and are very different from S5.2. They are given here to illustrate the latest thinking in this area, including expanded

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1.2 Functional Diagrams and Function Symbols

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TABLE 1.2a Functional Diagramming SymbolsInstrument and Mathematical Functions (proposed for the next revision of ISA S5.1 [now ANSI/ISA-5.01.01] at the time of this writing)
No. 01 Symbol Description Measuring device Input device Readout device Output device Symbols from Tables 1.1h through 1.1k may be used Automatic controller Single-mode controller Discrete device driver Insert function symbols, as required to dene controller algorithm, from Table 1.2c Use for vertical diagramming Automatic controller Two-mode controller Insert function symbols, as required to dene controller algorithm, from Table 1.2c Use for vertical diagramming Automatic controller Three-mode controller Insert function symbols, as required to dene controller algorithm, from Table 1.2c Use for vertical diagramming Automatic signal processor Insert function symbol from Table 1.2c Use for vertical diagramming Automatic controller Two-mode controller Insert function symbols, as required to dene controller algorithm, from Table 1.2c Use for horizontal diagramming Automatic controller Two-mode controller Insert function symbols, as required to dene controller algorithm, from Table 1.2c Use for horizontal diagramming Automatic signal processor Insert function symbol from Table 1.2c Use for horizontal diagramming May be rotated 90 Final control element Control valve Insert function symbol identier from Table 1.2c (no. 14) Final control element with positioner Control valve with positioner Insert function symbol identier from Table 1.2c (no.14)
*

02

03

04

05

06

07

08

09

10

11

Manual signal processor (*) = A, adjustable signal generator (*) = T, signal transfer Manual auto station
T

12
A

See statement of permission on page 31.

timing functions. Application information and examples on the use of the binary symbols are given in Section 1.12, Binary Logic Diagrams, and they use the current standard ANSI/ISAS5.21976 (R1992).

Binary logic switching and memory functions are used in analog or sequential control schemes. In truth tables and graphs, logic one (1) is true and logic zero (0) is false.

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General Considerations

TABLE 1.2b Instrument and Control System Functional Diagramming SymbolsBinary Logic, Memory, and Time Functions (proposed for the next revision of ISA S5.1 [now ANSI/ISA-5.01.01] at the time of this writing)
No. 01 A B C x A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 02 A B C x A 0 1 0 0 0 1 1 1 0 0 0 1 1 1 0 1 B 0 0 1 0 0 1 0 0 1 1 0 1 1 0 1 1 C 0 0 0 1 0 0 1 0 1 0 1 1 0 1 1 1 x 0 0 0 0 1 0 0 1 0 1 1 0 1 1 1 1 O 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 OR O 0 1 0 0 0 1 1 1 0 0 0 1 1 1 0 1 B 0 0 1 0 0 1 0 0 1 1 0 1 1 0 1 1 C 0 0 0 1 0 0 1 0 1 0 1 1 0 1 1 1 x 0 0 0 0 1 0 0 1 0 1 1 0 1 1 1 1 O 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 A B C X 1 0 A N D O Symbol/Truth Table AND gate. Output is true only if all inputs are true. Denition/Graph

O t 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

OR gate. Output is true if any input true.

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

A B C X

O t 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

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TABLE 1.2b Continued Instrument and Control System Functional Diagramming SymbolsBinary Logic, Memory, and Time Functions (proposed for the next revision of ISA S5.1 [now ANSI/ISA-5.01.01] at the time of this writing)
No. 03 A B C x A 0 1 0 0 0 1 1 1 0 0 0 1 1 1 0 1 B 0 0 1 0 0 1 0 0 1 1 0 1 1 0 1 1 C 0 0 0 1 0 0 1 0 1 0 1 1 0 1 1 1 x 0 0 0 0 1 0 0 1 0 1 1 0 1 1 1 1 O 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 n O Symbol/Truth Table Denition/Graph Qualied OR gate with greater than or equal to qualications. Output equals 1 if number of inputs equal to 1 are greater than or equal to n inputs. Truth table and graph are for n equals 2.

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 04 A B C x

A B C X

O t 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

>n

Qualied OR gate with greater than qualications. Output equals 1 if number of inputs equal to 1 are greater but not equal to n inputs. Truth table and graph are for n equals 2.

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

A 0 1 0 0 0 1 1 1 0 0 0 1 1 1 0 1

B 0 0 1 0 0 1 0 0 1 1 0 1 1 0 1 1

C 0 0 0 1 0 0 1 0 1 0 1 1 0 1 1 1

x 0 0 0 0 1 0 0 1 0 1 1 0 1 1 1 1

O 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1

A B C X

1 0

O t 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

(Continued)

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General Considerations

TABLE 1.2b Continued Instrument and Control System Functional Diagramming SymbolsBinary Logic, Memory, and Time Functions (proposed for the next revision of ISA S5.1 [now ANSI/ISA-5.01.01] at the time of this writing)
No. 05 A B C x A 0 1 0 0 0 1 1 1 0 0 0 1 1 1 0 1 B 0 0 1 0 0 1 0 0 1 1 0 1 1 0 1 1 C 0 0 0 1 0 0 1 0 1 0 1 1 0 1 1 1 x 0 0 0 0 1 0 0 1 0 1 1 0 1 1 1 1 O 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 1 0 n O Symbol/Truth Table Denition/Graph Qualied OR gate with less than or equal to qualications. Output equals 1 if number of inputs equal to 1 are less than or equal to n inputs. Truth table and graph are for n equals 2.

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 06 A B C x

A B C X

O t 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

<n

Qualied OR gate with less than qualications. Output equals 1 if number of inputs equal to 1 are less but not equal to n inputs. Truth table and graph are for n equals 2.

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

A 0 1 0 0 0 1 1 1 0 0 0 1 1 1 0 1

B 0 0 1 0 0 1 0 0 1 1 0 1 1 0 1 1

C 0 0 0 1 0 0 1 0 1 0 1 1 0 1 1 1

x 0 0 0 0 1 0 0 1 0 1 1 0 1 1 1 1

O 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0

A B C X

1 0

O t 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

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TABLE 1.2b Continued Instrument and Control System Functional Diagramming SymbolsBinary Logic, Memory, and Time Functions (proposed for the next revision of ISA S5.1 [now ANSI/ISA-5.01.01] at the time of this writing)
No. 07 A B C x A 0 1 0 0 0 1 1 1 0 0 0 1 1 1 0 1 B 0 0 1 0 0 1 0 0 1 1 0 1 1 0 1 1 C 0 0 0 1 0 0 1 0 1 0 1 1 0 1 1 1 x 0 0 0 0 1 0 0 1 0 1 1 0 1 1 1 1 O 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 1 0 =n O Symbol/Truth Table Denition/Graph Qualied OR gate with equal to qualications. Output equals 1 if inputs equal to 1 are equal to n inputs. Truth table and graph are for n equals 2.

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 08 A B C x

A B C X O

t 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Qualied OR gate with not equal to qualications. Output equals 1 if inputs equal to 1 are not equal to n inputs. Truth table and graph are for n equals 2.

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

A 0 1 0 0 0 1 1 1 0 0 0 1 1 1 0 1

B 0 0 1 0 0 1 0 0 1 1 0 1 1 0 1 1

C 0 0 0 1 0 0 1 0 1 0 1 1 0 1 1 1

x 0 0 0 0 1 0 0 1 0 1 1 0 1 1 1 1

O 0 1 1 1 1 0 0 0 0 0 0 1 1 1 1 1

A B C X

1 0

O t 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

(Continued)

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General Considerations

TABLE 1.2b Continued Instrument and Control System Functional Diagramming SymbolsBinary Logic, Memory, and Time Functions (proposed for the next revision of ISA S5.1 [now ANSI/ISA-5.01.01] at the time of this writing)
No. 09 A NOT O Symbol/Truth Table NOT gate. Output is false if input is true. Output is true if input is false. A 1 0 1 0 t 1 10 A B S R C D 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Denition/Graph

A 1 0

O 0 1

Basic memory. Outputs C and D are always opposite. If input A equals 1, then output C equals 1, and D equals 0. If input A changes to 0, output C remains 1 until input B equals 1, then C equals 1, and D equals 0. If input B equals 1, then output D equals 1, and C equals 0. If input B changes to 0, output D remains 1 until input A equals 1, then D equals 1, and C equals 0. If inputs A and B are simultaneously equal to 1, then outputs C and D change state. A B C D t 1 2 3 4 5 6 7 8 Set dominant memory (So dominant). Outputs C and D are always opposite. If input A equals 1, then output C equals 1, and D equals 0. If input A changes to 0, output C remains 1 until input B equals 1, then output C equals 1, and D equals 0. If input B equals 1, then output D equals 1, and C equals 0. If input B changes to 0, output D remains 1 until input A equals 1, then output D equals 1, and C equals 0. If inputs A and B are simultaneously equal to 1, then output C equals 1, and D equals 0. A B C D t 1 2 3 4 5 6 7 8 1 0 1 0

1 2 3 4 5 6 7 8

A 0 1 0 0 0 1 0 1

B 0 0 0 1 0 1 0 1

C 0 1 1 0 0 1 1 0

D 1 0 0 1 1 0 0 1

11 A B So R C D

1 2 3 4 5 6 7 8

A 0 1 0 0 0 1 0 1

B 0 0 0 1 0 1 0 1

C 0 1 1 0 0 1 1 1

D 1 0 0 1 1 0 0 0

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TABLE 1.2b Continued Instrument and Control System Functional Diagramming SymbolsBinary Logic, Memory, and Time Functions (proposed for the next revision of ISA S5.1 [now ANSI/ISA-5.01.01] at the time of this writing)
No. 12 A B Symbol/Truth Table S Ro C D Denition/Graph Reset dominant memory (Ro dominant). Outputs C and D are always opposite. If input A equals 1, then output C equals 1, and D equals 0. If input A changes to 0, output C remains 1 until input B equals 1, then output C equals 1, and D equals 0. If input B equals 1, then output D equals 1, and C equals 0. If input B changes to 0, output D remains 1 until input A equals 1, then output D equals 1, and C equals 0. If inputs A and B are simultaneously equal to 1, then C equals 0, and D equals 1. A B C D t 1 13 I t PD O 2 3 4 5 6 7 8 Pulse duration, xed. Output O changes from 0 to 1 and remains 1 for prescribed time duration t when input I changes from 0 to 1. 1 0

1 2 3 4 5 6 7 8

A 0 1 0 0 0 1 0 1

B 0 0 0 1 0 1 0 1

C 0 1 1 0 0 0 0 0

D 1 0 0 1 1 1 1 1

NONE I

1 0

O t t t 14 I t DT O Off-time delay. Output O changes from 0 to 1 when input I changes from 0 to 1. Output O changes from 1 to 0 after input I changes from 1 to 0 and has been equal to 0 for time duration t. I 1 0

NONE

O t t t (Continued)

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40

General Considerations

TABLE 1.2b Continued Instrument and Control System Functional Diagramming SymbolsBinary Logic, Memory, and Time Functions (proposed for the next revision of ISA S5.1 [now ANSI/ISA-5.01.01] at the time of this writing)
No. 15 I R NONE I t GT O Symbol/Truth Table Denition/Graph On-time delay. Output O changes from 0 to 1 after input I changes from 0 to 1 and I remains 1 for prescribed time duration t. Output O remains 1 until a. Input I changes to 0. b. Reset R changes to 1. 1 0

R 16 I R NONE I t LT O Pulse duration, variable. Output O changes from 0 to 1 when input I changes from 0 to 1. Output O changes from 1 to 0 when a. Input I has equaled 1 for time duration t. b. Input I changes from 1 to 0. c. Reset R changes to 1.

1 0

R See statement of permission on page 31.

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1.2 Functional Diagrams and Function Symbols

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TABLE 1.2c Mathematical Function Block Symbols (proposed for the next revision of ISA S5.1 [now ANSI/ISA-5.01.01] at the time of this writing)
No. 01 Symbol/Function Equation/Graph
M = X 1 + X 2 .+ X n X Xn X1 X2 M

Denition Output equals the algebraic sum of inputs.

Summation

02

/n
Average

M = X1 + X2 X

. +

X n/n M X1 X2 X3 t t

Output equals the algebraic sum of the inputs divided by number of inputs.

03

Difference

M = X1 X2 X X1 X2 M

Output equals the difference between two inputs.

04

X
Multiplication

M = X1 X2 X X1 M X2

Output equals the product of the two inputs.

t1

t1

05

Division
t1 t t1 t

M = X1 / X2 X X1 X2 M

Output equals the quotient of the two inputs.

06

2 X
Square

M=X X

Output is equal to the square of the input.

M

07

M= X X

Output is equal to the nth power of the input.

M

Exponential
t t

(Continued)

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General Considerations

TABLE 1.2c Continued Mathematical Function Block Symbols (proposed for the next revision of ISA S5.1 [now ANSI/ISA-5.01.01] at the time of this writing)
No. 08 Symbol/Function Equation/Graph
X M= X M

Denition Output is equal to the square root of the input.

Square Root

09

n
nth Root

M= X

X M

Output is equal to the nth root of the input.

10

K or P
Proportional

M = KX X M

Output is proportional to the input. Replace K with 1:1 for volume boosters. Replace K with 2:1, 3:1, etc. for integer gains.

t1

t1 t1 t

11

-K or -P
Reverse Proportional

M = KX X

Output is inversely proportional to the input.

M t1 t

12

or I
Integral

M = (1/TI ) X

X dt M

Output varies with the magnitude and time duration of the input. Output is proportional to the time integral of the input. TI, the integral time constant.

t1

t2

t1

t2

13

d/dt or D
Derivative

M = T D (dX/dt) X M

Output is proportional to the time rate of change of the input. TD , derivative time constant.

t1

t1

14

(X)
Unspecified Function

M = (X) X M

Output is a nonlinear or unspecied function of the input. Function is dened in note or other text.

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TABLE 1.2c Continued Mathematical Function Block Symbols (proposed for the next revision of ISA S5.1 [now ANSI/ISA-5.01.01] at the time of this writing)
No. 15 Symbol/Function Equation/Graph
M = X(t) X M

Denition Output equals a nonlinear or unspecied time function times the input. Output is a nonlinear or unspecied time function.

(t)
Time Function

t1

t1

16

>
High Select

M = X 1 for X 1 X 2 , M = X 2 for X 1 X 2 X X1 X2 M

Output equals greater of two or more inputs.

t1

t
X 2 , M = X 2 for X 1 X 2

t1

17

<
Low Select

M = X 1 for X 1 X

Output equals lesser of two or more inputs.

X1

X2

t1

t1

18

>
High Limit

M = X1 for X1 H, M = X2 for X1 H X X M

Output equals the lower of the input or high limit values.

t1

t1

19

<
Low Limit

M = X1 for X1 L, M = X2 for X1 L X X M

Output equals the higher of the input or low limit values.

t1

t1

20

V
Velocity Limiter

dM/dt = dX/dt (dX/dt H, M = X) dM/dt = H (dX/dt H, M X) dX/dt>H X M dM/dt=H

Output equals input as long as the input rate of change does not exceed the limit value that establishes the output rate of change until the output again equals the input.

t1

t2

t1

t2

(Continued)

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General Considerations

TABLE 1.2c Continued Mathematical Function Block Symbols (proposed for the next revision of ISA S5.1 [now ANSI/ISA-5.01.01] at the time of this writing)
No. 21 Symbol/Function Equation/Graph
M=X+b X M

Denition Output is equal to input plus an arbitrary value.

+
Positive Bias

t X M

22

Negative Bias

M=Xb X M

Output is equal to input minus an arbitrary value.

t X M

25

/
Conversion

I = P, P = I, etc. I P

Output signal type is different from that of input signal. * is equal to: E voltage, A analog I current, B binary P pneumatic, D digital R resistance, H hydraulic O electromagnetic, sonic Output state is dependent on the value of the input. Output changes state when the input is equal to or higher than an arbitrary high limit.

26

H
High Signal Monitor

(State 1) M = 0 @ X < H (State 2) M = 1 @ X X X H State 1 State 2

t1

t1

27

L
Low Signal Monitor

(State 1) M = 0 @ X H (State 2) M = 1 @ X > X X L State State 1 2 M

Output state is dependent on the value of the input. Output changes state when the input is equal to or lower than an arbitrary low limit.

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TABLE 1.2c Continued Mathematical Function Block Symbols (proposed for the next revision of ISA S5.1 [now ANSI/ISA-5.01.01] at the time of this writing)
No. 28 Symbol/Function Equation/Graph
(State 1) M = 1 @ X L (State 2) M = 0 @ L < X < H (State 3) M = 1 @ X X M X H L t t State 1 State 2 State 3

Denition Output states are dependent on value of input. Output changes state when input is equal to or lower than an arbitrary low limit or equal to or higher than an arbitrary high limit.

HL
High/Low Signal Monitor

29

T
Transfer

(State 1) M = X1 (State 2) M = X2 X X1 M
State 2

Output equals input that is selected by transfer. Transfer is actuated by external signal.

X2

State 1 t t

See statement of permission on page 31.

2003 by Bla Liptk