The 7th International Conference on Power Electronics

October 22-26, 2007 / EXCO, Daegu, Korea

PS2

Digital Current Mode Control Approach for the Parallel Module DC-DC Converters
Bohyung Cho Seoul National University Department of Electrical Engineering San 56-1, Sillim-dong, Gwanak-gu, Seoul, 151-742 Email: bhcho@snu.ac.kr Hyunsu Bae Seoul National University Department of Electrical Engineering San 56-1, Sillim-dong, Gwanak-gu, Seoul, 151-742 Email: bhsue@pesl.snu.ac.kr not be implemented. Thus, a parallel interleaved converter control method using the sliding mode control was proposed [3]. However, this controller design technique is very complex and the expansion of the modules is not convenient. A simplified digital peak current mode controller whose operation is similar to analog peak current program mode was proposed in [8, 9]. However, this approach still used an analog current loop. An all state feedback control for the DC-DC converters has been proposed for the systematic controller design [3, 19-24]. These algorithms used a LQR approach [19, 24], sliding mode control [3, 21] for the robust control, and an (observed based) integral control scheme for reference voltage tracking [20, 22-23]. However, most of these algorithms are based on the continuous time domain, which needs the approximated transformation to the discrete time domain for a realization of digital controller, and single module converter control. In [23], the discrete time domain design is mentioned but the basic controller structure is similar to the continuous integral control. In [3, 22], the parallel module converter control issue is discussed. However, this controller design technique is also very complex and the expansion of the converter module is not convenient because the algorithms use a high order state and a multi-input system. In this paper, two kinds of a simple digital control scheme are presented for the parallel interleaved DC-DC converter. Of the two proposed schemes, one is a constant resistive load sink control scheme. This algorithm is very simple to implement with a digital controller and there is no power stage parameter dependency in the controller design. By converting the effective input characteristic of the converters seen by the power source to a resistive load sink, the proposed control scheme achieves the current sharing by using a nonlinear transformation. The second scheme is a digital state feedback control method using the pole placement technique. By changing a multi-input/multioutput system into a single-input/single-output system using a two loop control scheme, the proposed control scheme can precisely achieve the interleaved current sharing and can achieve the systematical controller design for digital implementation due to the fact that the controller design and analysis are performed in the discrete time domain. Thus, these simple algorithms fully utilizing the advantages of the digital controller are convenient for the expansion of the converter modules. For the verification of the proposed digital control schemes, a parallel module Buck converter with a TMS320F 2812 DSP has been built and tested.

AbstractThis paper presents the digital current mode control employing nonlinear resistive current mode control and digital state feedback control using the pole placement technique for parallel interleaved DC-DC converters. The former method achieves current sharing by converting the effective input characteristic of the converters seen by the source to a resistive load sink. The latter method derives the discrete state feedback controller structure for robust tracking control using the error state. For the design example of the two control scheme, a prototype hardware system with two 100W parallel module buck converters with a TMS320F2812 DSP has been built and tested.

I.

INTRODUCTION

With recent advances in digital systems, digital control has become increasingly feasible even for high frequency, low to medium power switching converters. Digital control offers the potential advantages of immunity to analog component variations, programmability and possibilities to improve performance using more advanced and sophisticated algorithms [1-10]. Ever increasing demands for the development of compact, lightweight power supplies with more power density, higher efficiency and fast dynamics, often require power conversion through parallel connected converters [11-12]. In order to achieve the current sharing among the converter modules, various analog current mode control methods such as peak current mode control, charge current mode control, average current mode control, etc [13-18] are used. However, a direct implementation of a digital control scheme for an analog current mode control method is not easy. In analog current mode control, the switch current or the inductor current is sensed and the switch duty cycles of each converter module are generated by comparing the sensed current to a reference. Because the switch or inductor current is a fast changing waveform and the switching frequency is high, the need for a very fast analog to digital converter (ADC) to produce multiple samples of the sensed current per switching period, which may require excessively complex hardware. Thus, a digital current mode control method that can match or exceed the performance of the analog current control method has been of much interest. In [4, 5], current estimation algorithms are proposed. These algorithms focus on the current mode control to improve the dynamics. Even though the dynamics is improved, the current sharing among the parallel converter modules may

The 7th International Conference on Power Electronics

October 22-26, 2007 / EXCO, Daegu, Korea

Fig. 1: The parallel interleaved buck converter

II. DIGITAL RESISTIVE CURRENT CONTROL USING THE EFFECTIVE INPUT CHARACTERISTIC OF THE CONVERTERS SEEN BY THE SOURCE A. Digital Resistive Current (DRC) Controller for the current mode control The proposed DRC control scheme is illustrated in Fig. 1. If the effective input characteristic of the converter seen by the source is a resistive load sink, the converter input current, i g , and the source voltage, v g , have the relation of
v g = rz i g

Fig. 2: The small signal block diagram in the discrete time domain

Gid ( z ) = Gvd ( z ) =

Vg Ts

z (1 a + ab) L z 2 + (a 2) z + (1 a + ab)

z LC z 2 + (a 2) z + (1 a + ab) T RTs L where a = s , b = , L = nor , Li Lnor RC L N

Vg Ts2

(3)

(1)

where, rz is the equivalent input resistance of the converter and is set to the given reference value of the DRC controller. If the buck converter is operated in the continuous conduction mode (CCM), the control duty ratio, d , required to realize the current mode control can be derived based on the DC gain of the converter as follows;
v g = rz d iL di = vg rze iL ,i (i = 1,2, , N and rze = N rz )

where, L is an equivalent inductance for the equivalent single module model of the parallel module converter [11], and Ts is the sampling time, which is the same as the switching period. For the small signal modeling of the controller, the perturbation and linearization of equation (2) gives
Vg D D D d (k + 1) = v g (k ) iL (k ) rz where D = Vg IL Rz Rz I L

(4)

(2)

Fig. 2 shows the small signal block diagram of the proposed control system. From the small signal block diagram, the control-to-output transfer function of the new power stage is given as follows;
Gvr ( z ) = VoTs2 z (5) LCR z z 3 + (a + 2) z 2 + (1 a + b + ab) z b(1 a + ab)

Imaginary Axis

where, iL is the output inductor current and N is the number of converter modules. For other types of converters, the control duty ratio can be derived by a similar procedure. If the parallel module converter is controlled using equation (2), the effective input characteristic seen by the source is a constant resistive load. Also, the current sharing among the converter modules is automatically achieved because the resistive load seen by the source is the same. The proposed DRC control method is quite simple and easy to realize in a digital controller. Furthermore, there is no power stage parameter dependency in the controller design. The control duty ratio is determined by the sensed voltage and current. B. Small signal modeling and stability analysis Small signal modeling was performed to analyze the dynamics and the stability for the proposed control system. Since the controller is realized in the digital domain, the discrete time domain analysis is useful for design guidelines. Using the discrete time modeling of the DC-DC converters [25 -26], the open loop transfer functions of the buck converter are as follows;

Fig. 3 shows the root locus of the control-to-output transfer function with respect to the load range in the CCM operation. It can be seen that the poles are placed outside of the unit circle, which means that sub-harmonic oscillation occurs at the light load condition.
Root Locus 1 0.8 0.6 0.4
4 x 10
-3

Root Locus

0.2
Imaginary Axis

3 2 1 0 -1 -2 -3 -4

0 -0.2 -0.4 -0.6 -0.8 -1 -1

-5 0.985 0.99 0.995 Real Axis 1 1.005 1.01

-0.5

0 Real Axis

0.5

Fig. 3: The root locus of control-to-output transfer function (sub-harmonic)

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The 7th International Conference on Power Electronics

October 22-26, 2007 / EXCO, Daegu, Korea

Root Locus 1 0.8 0.6

x 10
-3

Voltage source Current [A]

Root Locus

0.4 Imaginary Axis 0.2

Imaginary Axis

5 4 3 2 1 0 -1 -2 -3 -4

1 Rz

0 -0.2 -0.4 -0.6 -0.8 -1 -1

Voltage [V]

-5 0.97

0.975

0.98

0.985

0.99 0.995 Real Axis

1.005

1.01

Effective load characteristic of the DC-DC converters

Fig. 5: The origin shift of the equivalent resistance

-0.5

0 Real Axis

0.5

Fig. 4: The root locus of the control-to-output transfer function with the offset inductor current

To prevent this sub-harmonic oscillation, an offset current value, I Lk , is added to the proposed algorithm. The small signal model shown in Fig. 2 is still valid as follows;
v g = rz d (iL + I Lk ) d = rz (iL + I Lk ) vg

(6)

After the origin shift, the DC gain of the control-to-output transfer function can be similar at both the heavy and light load conditions, which enables the voltage loop compensation for the fast dynamics. Since there is only one low-frequency pole below the switching frequency in the control-to-output transfer function, a simple discrete PI voltage controller with an anti- windup loop is applied to the proposed DRC control. When the voltage compensator is designed, the positive feedback loop is needed because the control-to-output transfer function has a negative DC gain. D. Experimental verification The prototype hardware system, which consists of two 100W parallel module buck converters, was built as shown in Fig. 1. The converter parameters are: Vg = 60[V ] , Vo = 31[V ] ,
L1 = L2 200[ H ] , C = 100[ F ] and Fs = 100[kHz ] . The DSP control strategy using the synchronous PWM is used, which can sample the average inductor current and can easily generate two phase-shifted duty cycles for the interleaving control. Fig. 6 and 7 show the transient performance of the DRC control without the voltage loop at the resistive reference variation. Fig. 8 and 9 show the converter behavior, which closes the PI voltage control loop, in the presence of stepped load variation from 60[W] to 120[W] and vice versa. It is observed that the voltage regulation can be achieved and the interleaved current sharing is also possible during the transient period, as well as in steady state.

where, I Lk is the offset inductor current value, which is programmed in the digital processor.
Gvr ( z ) = VoTs2 z 3 2 LCR z z + (a 2) z + (1 a + b + ab) z b(1 a + ab) where = IL I L + I Lk

(7) By selecting the proper I Lk (> 0) value, the sub-harmonic oscillation can be suppressed as shown in Fig. 4. The poles of the control-to-output transfer function are placed inside of the unit circle for the given load range. Origin shift method of the resistance and Simple PI voltage loop compensation It is observed from equation (7) that the DC gain of the control-to-output transfer function is affected by the equivalent resistance of the converter. Thus, the system has poor dynamics at light load and it is difficult to design a voltage compensator for obtaining the desired loop gain. To solve these problems, the origin of the equivalent resistance can be shifted as shown in Fig. 5. Therefore, the DRC control algorithm is modified and the complete small signal model is expressed as follows;
v g = V1 + rz i g I 1 = V1 + rz d (iL + I Lk ) rz I1 d= Gvr ( z ) =
2 s

C.

v g V1 + rz I1 rz (iL + I Lk )

VoT I1 1 LCR z D (I L + I Lk ) z z 3 + (a 2) z 2 + (1 a + b + ab) z b(1 a + ab)

(8)

where, V1 , I1 are programmed in the digital processor as well.

Fig. 6: The resistive reference step variation (3W to 120W)

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The 7th International Conference on Power Electronics

October 22-26, 2007 / EXCO, Daegu, Korea

III. A.

DISCRETE STATE FEEDBACK CONTROL AVERAGE AND PROPORTIONAL TYPE CURRENT CONTROL

State feedback controller structure in the discrete time domain for robust tracking control Using the discrete time modeling method [25 -26], the average discrete time state equation of the DC-DC converters can be derived for the discrete state feedback controller.
x( k + 1) = Az x(k ) + Bz d (k ) + Bvgz v g (k ) + Bioz io (k ) y (k ) = C z x(k )

(9)

Fig. 7: The resistive reference step variation (120W to 3W)

The objective is to design an overall system such that the output y (k ) will track asymptotically any step reference input, r (k ) = R(constant) , even with the presence of an input disturbance and with plant parameter variations. The error state, e(k ) , and augmented state variable, z (k ) , u (k ) , w(k ) , are defined, and the input voltage, v g , and output current, io , are assumed to be sustained with one switching period.
& e(k ) = r (k ) y (k ) = R C z x(k ), z (k ) = x(k ) x(k + 1) x(k ) Ts

d (k + 1) d (k ) & & u (k ) = d (k ) , e(k ) C z z (k ) Ts & & w1 (k ) = v g (k ) 0, w2 (k ) = io (k ) 0 using Euler's method

(10)

Then, the system can be expressed by the augmented state vector [e(k ) z (k )]T .
e(k + 1) 1 Ts C z e(k ) 0 = + u (k ) Az z (k ) Bz z ( k + 1) 0 e( k ) u (k ) = [K1 K 2 ] z (k )

(11)

Fig. 8: The load step variation (60W to 120W)

If the expanded system is controllable, then there exists a state feedback gain such that the expanded system is stable. That means the output of the converters tracks the reference value. Furthermore, using the state feedback gain, the systems eigenvalues can be placed to the desired poles, which determine the performance of the feedback control system. The duty ratio for the converters can be derived from equation (10) and (11) as follows; d (k ) = d (k 1) K1Ts e(k 1) K 2 [x( k ) x(k 1)] (12) However, the system has a high order state and multi input when the converter module is expanded. For example, the system shown in Fig. 1 has three state variables and two independent input duty ratios. Furthermore, whenever the converter module is expanded, the redesign of entire controllers is always required. Thus, in order to perform the systematical controller design for the parallel module system, it is necessary to make a simple state feedback algorithm. B. Average type current control scheme First, the inner current loop controller is designed for the each converter module without the output capacitor, which has only one state variable, the inductor current, as shown in Fig. 1. Using the un-terminated modeling method, the state equation is derived and the discrete state equation employing equation (9) becomes

Fig. 9: The load step variation (120W to 60W)

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The 7th International Conference on Power Electronics

October 22-26, 2007 / EXCO, Daegu, Korea

& SW ON) iL ,i (t ) =

1 1 & v g (t ) vo (t ) , SW OFF) iL ,i = vo (t ) Li L

Vg Ts iL ,i ( k + 1) = iL ,i (k ) + d i (k ), i = 1,2, , N Li

(13)

where, the input voltage and output voltage are assumed to be the sustained during one switching period. From the same procedure in Section III.A, the state equation of the overall closed loop system is given as follows;
1 Ts e( k ) e(k + 1) = K1V g T 1 K 2V g T , Li L s s z (k ) z (k + 1) L L

(14)

The augmented system is a second order system. Therefore, the desired pole location can be easily obtained from the given converter specification, as well as the general second order systems response using the continuous and discrete time domain relationship. The given converter specifications are defined as follows; Settling time 100[ S ] , P.O. 1[%] . From the required system dynamics, the desired pole locations are given by
Settling time z desired 4Ts 100[ S ], P.O. 100e ln( r ) / 1[%] ln(r ) (15) = r = r cos( ) jr sin( )

Fig. 10: The average type state feedback current loop

Fig. 10 shows the state feedback current loop control system for the two module buck converter using average type current control. The state equation of the output capacitor is derived to design the outer voltage loop from Fig. 1.
& vo (t ) = 1 (iL (t ) io (t )) vo (k + 1) = vo (k ) + Ts iL (k ) C C where iL = iL ,1 + iL , 2 + + iL , N

(16)
Fig. 11: Inductor current response of average type current control

where, output current is assumed to be the sustained during one switching period. After closing the current loop, the parallel module converter becomes a SISO system, which has one control input, I L ,i ,ref , and one output, iL . Thus, the small signal model of the new power stage equation, which is terminated to the output capacitor, can be derived as follows;
0 iL (k ) Vg (K1Ts + K 2 )Ts Leq iL (k + 1) = d (k ) K1Ts + K 2 vo (k + 1) 0 Vg K1Ts2 + 0 Leq 1 1 Vg K 2Ts Leq K2 Ts C
T

0 Vg Ts Leq 1 0

0 iL ( k 1) 0 i (k ) L 0 d (k 1) 1 vo ( k )

K1Ts

L 0 I ref ( k ), Leq = N
Fig. 12: Inductor current response of average type current control

(17) It is difficult to design the outer voltage controller with the same procedure as in Section III.A because the state equation has four state variables due to the current loop states. Furthermore, the augmented system using equation (17) is uncontrollable because the duty ratio is determined by the internal state. Thus, another approach for designing the outer voltage loop is needed. However, the average type current mode control is still useful for the current control in applications such as the battery charger, the bi-directional converter in the hybrid automobile system and so on.

To verify the theoretical analysis, the prototype hardware was built and tested as shown in Fig. 1. The converter parameters are: Vg = 52[V ] , Vo = 28[V ] , L1 = L2 100[ H ] ,
C = 100[ F ] and Fs = 100[kHz ] . In this implementation, the

output is set to 28[V] using a constant voltage mode using electric load equipment. Fig. 11 and 12 show the inductor current of each module, which meets the required dynamics for the given specification.

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The 7th International Conference on Power Electronics

October 22-26, 2007 / EXCO, Daegu, Korea

C.

Proportional Type current control scheme The average type current mode control scheme is proposed for the current sharing. Even though the exact current control is possible, this approach poses a difficulty in designing the output voltage regulation loop. Thus, the proportional type current control scheme is proposed for the systematical output voltage control loop design. The control duty ratio is defined as d i (k ) = K c [I ref iL ,i (k )] , which is a proportional type state feedback controller in order to achieve the current sharing. Thus, the state equation of the current loop closed system employing equation (13) is a first order system as follows;
iL ,i (k ), d i (k ) = K c iL ,i (k ) Li L (18) 4Ts Vg Ts K c K c = L 1 exp 4Ts = exp 1 spec spec L Vg Ts Vg Ts K c iL ,i (k + 1) = 1 Li

Fig. 13: The complete state feedback control structure with the proportional type current control

where, spec is a settling time specification and K c is a feedback gain using the general 1st order systems response. In this case, although a steady state error for a given reference value exists, the current sharing can be achieved. For this analysis, the ESR of the inductor, rL ,i , is considered and the final value theorem of the average large signal converter model from equation (13) is used.
r 1 1 & iL ,i (t ) = L ,i iL ,i (t ) + d i (t )v g (t ) vo (t ), v g Vg , vo Vo Li Li Li iL ,i () = lim sI L ,i ( s ) =
s 0

Fig. 14: The proposed control system response during step load variation

Vg K c I ref Vo rL ,i + Vg K c

I ref

D rL ,i << Vg K c Kc

(19)

It is confirmed that the steady state inductor current is not related to the inductance, and the effect of ESR can be ignored. Thus, the proposed proportional current loop can achieve the current sharing. After closing the current loop, the parallel module converter becomes a SISO system, which has one control input, I L ,i ,ref , and one output, iL . Thus, the small signal model of the new power stage equation, which is terminated to the output capacitor, can be derived as follows;
Vg Ts K c iL (k + 1) 1 L eq = Ts vo (k + 1) C Vg Ts K c 0 i (k ) L + Leq I ref (k ) v o ( k ) 0 1

Output Voltage

300uS
Inductor current of Each module

(20)
Fig. 15: The proposed control system response during step load variation

From the same procedure in Section III.A, the state feedback controller can be designed to regulate the output voltage of the parallel module converter. The augmented discrete state equation becomes a 3rd order system. Thus, using the dominant pole approach for the pole placement technique, the desired pole locations can be obtained relating the given specification and the general 2nd order systems response as equation (15). The given converters specifications are defined as follows; Settling time spec 300[ S ] , P.O. 1[%] . From the required system dynamics, the desired pole locations are given by 10 z desired = r cos( ) jr sin( ) and [r cos( )] (21)

Fig. 13 shows the complete state feedback controller with the proportional type current control for the parallel module buck converter. Fig. 14 and 15 show the converter behavior, which closes the overall state feedback control loop in the presence of a stepped load variation from 85[W] to 170[W] and vice versa. The same converter parameters in the average type current control implementation are used. It is observed that the voltage regulation as well as the interleaved current sharing is achieved during the transient period, as well as in steady state. The response time is in good agreement with the required converter specification and thus confirms the theoretical analysis.

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The 7th International Conference on Power Electronics

October 22-26, 2007 / EXCO, Daegu, Korea

IV.

CONCLUSIONS
[7]

This paper presents the digital current mode control employing nonlinear resistive current control and digital state feedback control using the pole placement technique for the parallel interleaved DC-DC converters. The digital resistive current control converts the effective input characteristic of the converters seen by the source to a resistive load. Thus, this control scheme can achieve current mode control like the existing analog current mode control, while also achieving current sharing among the converter modules. Also, the sub-harmonic oscillation at the light load condition is defined and the method of avoiding this oscillation is presented by adding an offset inductor current value. For the design and stability analysis, the complete small signal analysis in the discrete time domain is performed. To regulate the output voltage, a simple discrete PI controller with an anti-windup loop and an origin shift of the resistance is designed for the purpose of fast dynamic response, as well as controller design convenience. Also, the discrete state feedback controller structure for robust tracking control is derived to regulate the converter output. Using the un-terminated modeling method, two types of the current control loops are designed to achieve current sharing; namely, the proportional and average current mode control methods. For the output voltage regulation, the outer voltage controller is designed using the new power stage, which is the current loop closed converter system without an output capacitor in the proportional type current control. For the design example of the proposed control schemes, two 100W parallel module buck converter with a TMS320F2812 DSP has been built and tested. Since these algorithms are quite simple and are designed in the discrete time domain, it is convenient for the digital realization and the expansion of the converter modules, as well as for the dynamics and stability analysis. ACKNOWLEDGMENT This study is partly supported by Korea Aerospace Research Institute (KARI). REFERENCES
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