POSTER PAPER International Journal of Recent Trends in Engineering, Vol. 1, No.

4, May 2009

Carbon Nanotubes A Solution for Tera Hertzs IC Interconnect

College of Engineering, Chengannur, India Email: nisha@ceconline.edu 2 VIT University, Center of Nanotechnology Research, School of Electrical Science, Vellore, India Email: jewan1@gmail.com possesses an inherent resistance against electron migration and has high thermal conductivity, which are essential properties for on chip interconnect. Though, the pioneer researchers from Standford University have successfully developed a method for replacing MWCNTs as gigahertz interconnects in 2008, even then the technology is still in its infancy.. The various structural simulation studies will help the process technologists in decision making. The work in this paper is trying to verify supporting bandwidth by SWCNT and bundled CNT interconnects for 22nm technology node, both at global and local level, without drivers in between. We have also verified its performance suitability with respect to ITRS prediction by normalizing the data with ITRS predicted data. In the current industry scenario copper interconnects needs a lot of drivers to provide satisfactory performance even at 10GHz range. This paper is organized as follows: Section II, which is a review of the existing work and discussion on the electrical model used for performance analysis Section III discusses the proposed work., Section IV includes the results of performance analysis and finally Section V draws the conclusion.
II. BACK GROUND AND MOTIVATION
1

Nisha Kuruvilla1, and J. P. Raina2

Abstract Single walled carbon nanotubes (SWCNTs) and bundled CNTs have emerged as promising candidates for future IC interconnect material due to their excellent inherent electrical and thermal properties. They will be an attractive solution for the resistivity and electromigration problems faced by traditional interconnects as technology scales into nanoscale regime. This paper makes an effort to evaluate the suitability of SWCNTs and bundled CNTs as futuristic Tera Hertz IC interconnects both at local and global level. This study indicates that bundled CNTs will be an ideal material choice as Tera Hertzs IC interconnects. Index Terms Carbon nanotube, interconnect, single walled carbon nanotube, contact resistance, performance analysis.

I. INTRODUCTION Increasing resistivity, rising demands on current density requirements and problems due to electromigration of traditional copper interconnects at nanoscale regime, are driving the need for new interconnect materials for integrated circuits(IC). The VLSI technology is said to be approaching limits in miniaturization; high packing density, high speed, high performance electronics and in portable battery operated equipment where copper interconnects cant perform reliably due to fundamental and material limits [1]-[5]. The increase in resistance leads to increase in propagation delay of the signal. Researches have proved that in copper, burn out occurred at current densities 80 MA/cm2[10]. Another main problem is electromigration, which limits performance and reliability of these interconnects [10],[11]. To realize the future dream of CMOS generation with solid background, it is important to investigate interconnects with extremely small feature sizes and high current capacity. Single walled metallic carbon nanotubes have been proposed as a possible replacement for on chip copper interconnects due to its compatibility with existing silicon technology [7] and its high current density, which is approximately 109A/cm2 [6]-[9].Carbon nanotubes (CNTs) were discovered by Sumio Lijima in 1991 [2]. CNTs are empty cylinders which can be viewed as rolled up sheets of a single or multiple concentric layers of graphene. The CNT with a single rolled up sheet of graphene is called single walled CNT (SWCNT), while the CNT having several concentric graphene layers is termed as multiwalled CNT (MWCNT). Depending on how the graphene layer or layers are rolled (chirality), it may exhibit conducting (metallic) or semiconducting behavior. CNTs can act as a ballistic conductor with mean free path of 1m. It 32
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Scaling the silicon CMOS transistor has been the main driving force behind the progress of the microelectronics industry for over three decades. The principal challenges for the semiconductor industry at the nanoscale are, power and performance optimization, device fabrication, control of variations at the nanoscale, and integration of a diverse set of materials and devices on the same chip. Many new device technologies are being proposed for the continued progress of nanoelectronics. of which, carbon nanotubes are one of the most interesting material options.. The inherent extraordinary electrical properties and small size. of the nanotubes-( rolled sheets of hexagonal carbon structures ) has drawn the attention of the fabrication technologists.. Their tiny size makes them faster than the existing interconnects available today.

POSTER PAPER International Journal of Recent Trends in Engineering, Vol. 1, No. 4, May 2009

Figure 2: Equivalent Circuit Model

Figure 1: Carbon Nanotube Interconnects for the Next Generation ICs

(Source :http://www.eniac.eu/web/SRA/processing.php)

The Figure 1 shows the schematic view of carbon nanotube interconnects for the next generation ICs. CNTs can act as a potential candidate as next generation IC interconnects due to its metallic nature with high current density even at very high temperature. The fabrication technologies for the realization of these interconnects are still in its infancy, The performance prediction of this novel technology will help fabrication engineers in decision making. There is also a need to identify the domains of on chip interconnections (local and global) where this novel interconnect technology is most suited as a potential interconnect candidate against ITRS predictions. This work is aimed at filling these gaps in the existing literature. A. Eqvalent Circuit Model for SWCNT and Bundlled CNT The Figure 2 shows the schematic of interconnect equivalent circuit diagram used for performance evaluation. This is an extended version of electrical model given in [12]. The resistance of SWCNT has three components. The first component is the resistance of ballistic SWCNT with perfect contact and its value is 6.4 K [13]. When the length of interconnect (L) is greater than its mean free path (Lo), an additional Drude like resistance (RCNT) is coming into picture due to scattering which is given by.

The capacitance offered by SWCNT consists of both quantum capacitance (Cq) and electrostatic capacitance (CE)[17], [12], [18]. The quantum capacitance offered by each conducting channel of a given nanotube has a theoretical value per unit length of 25aF/m. Assuming the presence of four conducting channels in a CNT, the effective quantum capacitance per unit length will be CQ= 4Cq 100aF/m. Also there is an electrostatic capacitance Ce between wire and the ground plane [17]. Since the same effective charges exist on both these capacitances (CE and CQ), when current flows through CNT, these capacitances appear to be in series in the effective circuit model as shown in Figure 1. SWCNT have both magnetic and kinetic inductance that can affect interconnect delay, noise and power consumption. The magnetic inductance (LM) is caused by induced voltage produced by time varying currents which is encapsulated in Amperes and Faradays laws. The kinetic inductance (Lk) is dependent on the sum of the kinetic energy of the left and the right moving electrons in a nanotube. No kinetic inductance was observed up to 10GHz [17], [12], [18]. Both LM and LK have been considered for the calculation in this work, since the predicted clock frequencies for future CMOS are above 10GHz. The number of CNTs (ncnt) in a bundle is given in [17]. The resistance of bundled CNT is calculated based on the assumption that all CNTs in the bundle are metallic. Since the CNTs are arranged as parallel conductors the resistance of bundled CNT is [17]

R f = RBundle =

h L RCNT = 2 4e L0

Risolated ncnt

(2)

(1)

The third component is due to imperfect metal-CNT contact [14]. Contact resistance is approximated as zero in this analysis. The total resistance is approximately equal to the sum of all the three contributions [13],[ 9], [12].The resistance of nanotube has a dependency on biasing voltage which leads to nanotube saturation. However in the case of current VLSI interconnects, a low voltage bias is sufficient which eliminates the problem of saturation of nanotubes at high electric fields [15], [16]. Hence they display excellent ohmic behavior and the resistance models explained above are valid.

For the calculation of capacitance we have used the same empirical formula by [17] and for the calculation of inductance the following expression is used

LBundle =

Lisolated ncnt

(3)

B. Previous Work on Performance of CNT Interconnects. Over the past four years several attempts were made by the researchers to evaluate the performance of CNT interconnects of various geometries. They also tried to check out its suitability on chip interconnects. Many of them compared its performance with alternative interconnect technology like copper, 3D interconnects and optical interconnects from various perspective. Here we are trying to comprehend some of the important studies of model based on CNT performance analysis. 33

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POSTER PAPER International Journal of Recent Trends in Engineering, Vol. 1, No. 4, May 2009 Most of the studies were directly or indirectly based on the model proposed by [12] based on Luttinger liquid theory. A comparative study with copper interconnects is carried out in [17]. Here they are not evaluating the performance variations under various loading conditions. Kinetic inductance has not been included in these studies mentioning that operating frequencies are below 10 GHz. But since predicted operating frequencies of ITRS are above 10GHz after 2008, the exclusion of kinetic inductances are not recommended. The study in [19] discusses various issues in bottom- up approach to integrate multiwalled carbon nanotube structures. The researches in [20] are comparing the latency variations of Cu, optical and CNT interconnects for various lengths and aspect ratio with repeaters. The worst case analysis of the supported bandwidth has not been conducted. In [21] the relative impacts of magnetic and kinetic inductances on various bundled CNT geometries have been analyzed. The variation in parasitic effects for various bundle size and diameters of CNTs are studied in [18]. Various studies have been conducted [16],[22],[23] for analyzing performance of SWCNT, bundled CNT or multiwalled CNTs as interconnects. Statistical analysis of performance due to contact resistance variations over various CNT geometries are carried out in [24]-[26]. However, none these studies provides a comprehensive analysis of bandwidth handling capacity of interconnects using SWCNT and bundled CNTs. Also none of them verifies its The performance proximity towards ITRS prediction. III. PROPOSED WORK This paper is trying to verify the maximum supporting bandwidths by various lengths of CNT interconnects both in SWCNT and bundled CNT mode without repeaters. The entire analysis have been carried out against the 22nm technology node using the SPICE software. The technology depended rise times, load capacitances, clock frequencies, aspect ratios, dielectric constants and spacing between wires for 22nm technology node are taken from ITRS data. A pulse with rise time as per 22nm technology node prediction is provided as the input. The performance analysis are verified under the conditions of FO1 (fan out of one) and FO4 (fan out of four) by terminating circuit with equivalent load capacitance as per ITRS predicted conditions. . The analyses were then carried out for checking out their suitability as on chip interconnects for 22nm technology node by normalizing the results with respect to predicted on chip clock frequencies. Throughout the analysis a lumped parameter model is used. This work is aimed at filling these gaps in the existing literature about the relationship between maximum supporting bandwidth with respect to length for various geometries and loading conditions. This method may significantly help towards the development of a CAD methodology for evaluating the process dependent performance of CNT interconnects.
IV. RESULTS AND DISCUSSION

technology node. Later these data were normalized with respect to the ITRS predicted frequency for the same technology node. The details are as given below. A. Supporting Bandwidth at Various Interconnect Levels The Figure 3 gives the details of supporting bandwidth at local level. It is evident that bundled CNTs will act as a potential candidate to support Tera Hertzs frequency under various loading conditions. SWCNTs can reliably support frequencies up to few 10s of MHz, where copper interconnects is found to be quite inadequate for reliable working. The performances of SWCNTs are highly affected by loading conditions. However it has been found that there is a sudden decrease in supporting bandwidth as length increases. The simulation results for global interconnects are as shown in Figure 4. Hence repeaters are unavoidable in the case of SWCNTs. However up to 20um bundled CNTs can provide satisfactory performance in par with prediction without repeaters.

Figure 3: Supporting Band Width Versus Interconnect Length for Local Interconnects

Figure 4: Supporting Band Width Versus Interconnect Length for Global Interconnects

In this work we evaluated maximum supporting bandwidth by SWCNTs and bundled CNTs for 22nm 34
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POSTER PAPER International Journal of Recent Trends in Engineering, Vol. 1, No. 4, May 2009 B. Comparative Analyses with ITRS Prediction ACKNOWLEDGMENT
The authors wish to thank Mr. Anilkumar C.V, Mr. Arun Greig John, Miss. Athulya A, Mr. Shinu Gervasis and Mr. Akhil G Nair, for the constructive discussions during this work. This work was done with the help of facilities procured by TEQIP funding at the College of Engineering, Chengannur India.

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[1] International Technology Roadmap for Semiconductors (ITRS), 2008, http://public.itrs.net [2] James D. Meindl Low Power Microelectronics: Retrospect and Prospect, Proceedings of the IEEE, pp 3-19, April 1995. [3] Roberto Suaya, Rafel Escovar and Salsador Ortiz, Modeling and Extraction of Nanometer Scale Interconnects: Challenges and Opportunities (Invited), Proceedings of the 23rd Advanced Metallization Conference (AMC), San Diego,CA, October 16-19, 2006. [4] Kaustav Banerjee, Sungjun Im and Navin Srivastava, Interconnect Modeling and Analysis in the Nanometer Era: Cu and Beyond, 22nd Advanced Metallization Conference (AMC), Colorado Springs, CO, September 27-29, 2005 [5] Kaustav Banerjee and Amit Mehrotra, Global Interconnect Warming, pp 16-32, Circuits and Devices, September 2001. [6] Sumio Lijima, Helical Microtubles of graphite carbon, Letters to Nature, vol.354,pp 56-58, Nov. 1991. [7] F.Kreupl, Andrew P Graham, M. Liebau, George S Duesberg, Robert Seidel, E.Unger and W.Honelin, Carbon Nanotubes in Interconnect Applications, Microelectron. Eng. vol. 64, pp. 1172-1174, Aug 2001. [8] B.Q.Wei, R. Vajai and P. M. Ajayan, Reliability and current carrying capacity of carbo nanotubes, Appl. Phys. Lett., vol. 79, pp. 1172-1174, Aug 2001 [9] M Bockrath, D. H. Cobden, P. L. McEuen, N. G. Chopra, A. Zettl, A.Thess and R. E. Smalley, Single electron transport in ropes of carbon nanotubes, Science, vol. 275, pp 1922-1925, 1997. [10] G. Schindler, G Steinlesberger, M. Engelhardt and W. Steinhogl, Electrical characterization of copper interconnects with end of roadmap feature sizes, Solid State Electronics, vol. 47, pp. 1233-1236, 2003. [11] Navin Srivastava and Kaustav Banerjee, Interconnect challenges for nanoscale electronic circuits, JOM, pp.3031, 0ct.2004. [12] P. J. Burke, Luttingger Theory as a model of the Gigahertz electrical properties of carbon nanotubes, IEEE Trans. on Nanotechnology, vol..1, pp. 129-144, Sept. 2002. [13] Paul, McEuen, Michael S. Fuhrer and Hongkun Park, Single-walled carbon nanotube electronics, IEEE Trans. on Nanotechnology, vol..1, pp. 78-85, Mar. 2002. [14] Th. Hunger, et al, Transport in ropes of carbon nanotubes: Contact Barriers and Luttinger Liquid Theory, Physical Review B. vol.. 69, 195406, 2004. [15] Z. Yao, et. al., High Field Electrical Transport in single wall carbon nanotubes, Physical Review Lett., vol..84, no.13, pp. 2941-2944, 2000. [16] Azad Naeemi, Reza Sarvari and James D Meindl, Performance comparison between carbon nanotube and copper interconnects for gigascale integration, IEEE Electron Device Lett., vol.. 26, pp. 84-86, Feb. 2005. [17] Navin Srivastava and Kaustav Banerjee, Performance analysis of carbon nanotube interconnects for VLSI applications, ,ICCAD, pp 383-390,2005. [18] Yehia Massoud and Arthur Nieuwoudt, Modeling and design challenges and solutions for carbon nanotube

Figure 5: Normalized Band Width w.r.t ITRS Prediction for Local Interconnects

Figure 6: Normalized Band Width w.r.t ITRS Prediction for Global Interconnects The comparative studies of performance of CNT interconnects as shown in Figure 5 indicates that bundled CNTs will be a potential candidate for future interconnect material and it is one order above the predicted performance at local level. The SWCNTs with FO1 can only provide performance in par predictions for 22nm technology node. The Figure 6 gives the details of normalization studies of performance with respect to ITRS prediction at global level. Up to 10m length all configurations showed better performance than predicted. But, for higher lengths the performance was found to be not in par with the prediction. Thus it is clearly evident that the repeaters are inevitable at those levels. V. CONCLUSION The applicability of CNT as Tera Hertzs interconnects both at local and global level has been verified with the help of simulations. Its potentiality to act as interconnects for 22nm technology node has also been verified. It was found that, bundled CNTs can perform reliably in Tera Hertzs range, while SWCNTs are also providing performance at par with prediction at local level. But in global level, repeater insertion is inevitable beyond 20m. The bundled CNTs may act as a potential interconnect material in future with the maturity of the fabrication process. 35
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POSTER PAPER International Journal of Recent Trends in Engineering, Vol. 1, No. 4, May 2009
based interconnect in future high performance integrated circuits, ACM Journal on Emerging Technologies in Computing Systems, vol. 2, pp 155-196 July 2006. Jun Li, Qi ye, Alan Cassell, Hou Tee Ng, Ramsey Stevens and Jie Han, Bottom-up approach for carbon nanotube interconnects, Applied Physics Lett., vol. 82, pp 24912493, April 2003. Kyung-Hoae Koo, Hoyeol Cho, Pawan Kapur and Krishna Saraswat, Performance comparison between carbon nanotubes, optical and Cu for future highperformance on- chip interconnect applications, IEEE Tr. On Electron Devices, vol. 54. No. 12, pp 3206-3213, December 2007. Arthur Nieuwoudt and Yehia Massoud, Performance implications of inductive effects for carbon nanotube bundle interconnects, IEEE Electron Device Letters, vol. 28, No.4, pp 305-307, April 2007. S. J. Trans, M. H. Devoret, H. Dai, A. Thess, R. E. Smalley, L. J. Georlga and C. Dekker, Individual carbon nanotubes as quantum wires, Nature, vol.. 386, pp 474477, 1997. [23] Mizuhisa Nihei, Masahiro Horibe, Akio Kawabata and Yuji Awano, Carbon nanotube vias for future LSI interconnects, Pro IEEE 2004 international interconnect technology conference , pp. 251-253, 2004 [24] Nisha Kuruvilla, J.P. Raina and C. V. Anilkumar, Load dependent performance analysis of SWCNT as VLSI interconncet, Pro. of National Conference on VLSI and Communication Engineering (NC-VCom 2008), Mar. 14th 15th 2008, pp 141-144. [25] Nisha Kuruvilla and C. V. Anilkumar, Performance analysis of carbon nanotube interconnects- a statistical approach, Pro. of International Conference on VLSI Design and Embedded Systems (ICVLSI08), Feb. 14th 16th 2008, pp 163-168. [26] Nisha Kuruvilla and J.P. Raina, Statistical Latency Analysis of Carbon Nanotube Interconnects due to Contact Resistance Variations, Pro IEEE ICM 2008 International conference on Microelectronics , December 2008

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