Chapter 1 Introduction Introduction to Chapter 1 Design Tools [2001] Design Options Semi-Custom Arrays Selection Which Array Technology?

Size o Design Support Issues Schematic Rules Checking Reformatters Design Upgrades o Exercises o Update 2000
o o o o o o

Introduction to Chapter 1
Application-Specific Integrated Circuits (ASIC) [1996]
Application-specific integrated circuits (ASICs) fit between the detailed full-custom circuit designs and the off-the-shelf pre-designed components. They offer the designer a faster method of tailoring the circuit to the task while retaining most of the fast design turn-around time offered by predesigned parts.

The Array
An ASIC array is a single die from a production wafer in the 1990s, it was generally two or three layers of metalization placed on top of a base array. Figure 1-1 provides an overview of the steps involved in building a semi-custom array. By 2001, the levels of metalization had climbed to an average of six layers of metalization. At least two layers are usually reserved for power-ground planes. The layers in the base array varied with the process with 26-28 layers in the base die being a reasonable assumption. Figure 1-1 Semicustom Array Processing

The base array is predesigned by the array vendor. It consists of the layers required to define the cells and the components within them. These components vary depending on the type of cell and the array family. They are resistors, diodes, transistors (bipolar or CMOS) with capacitance and impedances implied in the layering. The threshold voltage generators and other overhead circuitry will also be included in the base design. WAFER -----------------> DIE multiple die Individual array

The array designer will have already determined where the fixed power and ground pads are located, how many types and how many of each type of cell there is per array, and what design rules are required in the use of the array. The base array is pre-manufactured, reducing the turn-around time of the design between design acceptance and prototype or production. CBA Design System designers had the privilege of designing their own base die, including punch-outs for hard IP blocks, and power-ground routing for RAMs and soft IPs. The wafer is put through wafer-sort to determine good and bad die. The die is a prepackaged part which can be and is tested. When packaging is completed, the packaged part is retested. Wafer verification software (Dracula comes to mind) must verify all layers of the wafer, metallization and the base die, and verify that all IP blocks and memory blocks are properly connected. Hard IP blocks interconnect or "stitch" into all levels of the base die.

Customization
The customization of the array comes from the interconnect of the base array components. The interconnect is both the intraconnect between components within a cell to form a function, called a macro, and the interconnect between the macros to form the circuit module. One or more modules may be placed on an array. The interconnect between macros is considered the routing or nets. Routability is a measure of the ability to transform the design to physical metal etch patterns or the metallization of the array. The macros are formed by a predefined layout pattern that is not considered part of the routing problem. Macros may exist with several "footprints", which allow them to be positioned with different layout aspects. They also exist in different drive versions, which may also cause differences in the layout pattern. Switching a macro from one drive configuration to another may require its relocation in the circuit layout. With the high-speed arrays already available, the time delay or propagation delay through an interconnect net under heavy loading conditions may exceed the propagation delay through a macro. Priority pre-placement, design optimization for speed and other design approaches must be used to control the interconnect delays.

For DSM technologies, any technology below 0.18 micron, it is given that the interconnect delays will represent approximately 70% or more of the timing path delay
These tehnologies require pro-active design methodologies to be successful. Design partitioning, placement, and careful constraints are all required for a successful DSM design,

Design Tools - [2001]

In the 1990s the industry began to shift to EDA tools to handle the increased complexity of the ASIC designs. Any reasonable engineer can handle a design of up to 30,000 gates. When 6 million gates are involved, it would take multiple engineers years to complete one design. By the 1990s designs shifted from schematic capture, with the engineer selecting the appropriate macros from a library, to HDL code. VHDL is currently used in Europe and Verilog is currently used in the United States.

Design Tools - [1990s]

To perform a logical circuit design for an array-based circuit, the designer may choose between schematic capture, direct netlist creation, and the use of behavioral languages such as HDL and VHDL. Netlist generation as was done using Tegas is too tedious an approach for ASIC-based circuits past a minimal size. Netlist generation via a behavioral language or from schematic capture is the more usual approach. Translation programs exist to move a netlist in one format to a netlist in another format. The industry is still trying to expand the idea of EDIF, a common netlist that would allow input to any simulator and any placement system. For example: Verilog to Mentor translation is now possible using a Verilog netlist to create Mentor schematics. (Back-generation of schematics will remain a necessary step in spite of the push for behavioral descriptions as the preferred design tool.) Once an acceptable netlist has been generated by whatever means, the designer needs to check or verify that the design rules have not been violated. When the circuit is certified as acceptable and buildable, the circuit must be simulated according to the design submission requirements of the chosen vendor. The simulation must be checked. The design must be documented. Simulations involve control programs, stimulus generation, annotation delay files and descriptions. AC test analysis requires additional documentation. Which simulator can be used, and whether any timing verifier or other tools are available, is limited to what the array vendor supports. The simulation output files must be formatted according to vendor rules to allow the generation of test vectors. These will be transferred to the placement software and to testgeneration software. A submission may include dozens of files that must be tracked, controlled for revision level and managed to verify that the design submitted to the vendor is the one intended to be submitted. And yes, errors do occur.

Framework Systems
Framework systems are under development as the means of alleviating the design management problem but they are in their infancy and industry sages are predicting at

least five years before they meet any goals. Further, those developing framework systems disagree about those goals. There are four basic functions of a frame work agreed upon:

integration of design tools provide a common user interface manage the design data and manage the design process.

The integration of design tools includes tools from non-framework vendors. Allowing access to different design tools requires that the interface to those tools be reasonably similar and easy to use. (The Macintosh computers have proven the merit of similar and easy interface to tools and common databases.)

Array Selection as the First Task

Whatever the framework systems end up providing, the basic design flow that exists today will remain intact. The first and most difficult task of array selection will not change, nor will the basic goals of the current design methodology. It is the ease of satisfying those goals that will change. The process of selecting an implementation for a circuit involves two basic decision processes.

First, a decision must be made on the technology that will satisfy the design criteria for power and speed. Second, a selection must be made from the components (arrays, macro, IP, I/O, etc.) available within those technologies.

Even with all the changes made in software tools, these two key items remain unchanged. Choose the process, which defines the technology, and then choose the components, for even with high-level synthesis, the astutue designer can "guide" the software to a better solution. The software (Synopsys, Cadence, Avant! are the big three) is chosen by the designing group with input from the selected foundry as to the product design flow.

Design Options
The choices listed in Table 1-1 are available to the designer for whom off-the-shelf and bit-slice microprogrammable architectures are not good enough: full-custom arrays semicustom arrays and simple-custom (gate) arrays.

Full Custom Arrays

If the bit-slice or off the shelf microprocessor solution is not adequate, the next option may be a customized design. Full customization for an application-specific design is not practical in individual components at the SSI/MSI level. Instead, one or more custom semiconductors can be designed that are specifically for and only for the application.

The customized VLSI chip may be totally designed by the customer - from the design of the components present in the individual cells (resistors, diodes, transistors, etc.) to the interconnect between these components in one cell and other cells. Table 1-1 Design Approach Comparisons FULL CUSTOM multiple layers (18-20+) fastest (maybe) SEMI-CUSTOM 2-3 layers faster (maybe) PREFAB 0 layers fast

smallest (maybe) smaller (maybe) longest design cycle moderate design cycle fastest design cycle no control (fixed architecture)

most control over moderate design controlover design

All mask layers required to implement the full custom design must be generated specific to the application. Prototype and debug must encompass all layers. This approach will provide the smallest silicon and the most optimum solution if the designer is experienced. It can be the longest prototype time. The key is the required expertise of the designer. The number of designers that can successfully design a fully customized array is significantly less than the designers that can successfully design an MSI/LSI PC board. Depending on the manufacturer, a macro or standard cell library may exist that can speed the design time if the cells and macros are suitable for the application. The internal macro interconnects would still run through all mask layers. Design time may be reduced at the cost of some flexibility, but prototype time would remain lengthy. The advantage of the macro library is to help the designer by providing common functions while lessening the experience level required for a successful design.

Semi-Custom Arrays
A compromise between off-the-shelf modules and full custom semiconductors is semicustom design. Semi-custom combines a manufacturer designed base wafer with all components in place (resistors, diodes, transistors, etc.) and a customer-generated interconnect pattern to implement the desired circuit. (Refer to Figure 1-2.) A SEMI-CUSTOM ARRAY CONSISTS OF:

Base Wafer Macro Intra-connects Placement

Interconnects

The interconnect pattern, also called a netlist, is generated from the customer-designed schematic and restricted to the topmost mask layers. Most arrays require two metal layers and a via (through hole) mask layer. Some arrays require three metals and two via layers. Three-layer arrays may use two layers for global interconnect and the third for macro intraconnect, but there are no hard rules. The more layers, the more prototype debug time required. This may be compromised with the significant gain in power management possible with the third layer. The schematic for a semi-custom array-based circuit is built up from a library of macros released library that represent SSI, MSI, and sometimes LSI functions. If a different macro is needed from those in a released library, the manufacturer, for a fee, can usually generate a special custom macro (cell and component dependent). Most manufacturers prefer that the released macros be used. Figure 1-2 Circuit Composition

Semi-custom arrays allow a designer to create at the SSI-MSI level, with familiar functions, without a detailed knowledge of the underlying technology. Semi-custom arrays may themselves contain elements of bit-slice components, allowing both the hardware and the software to be tailored to the application. For example, at least one CMOS array uses the AMD Am2909 sequencer as a macro. If the designer is experienced and familiar with the macro library, the resulting silicon usage may approach that required by the best full custom design. CBA (cell-based arrays) and the now more-popular standard-cell libraries [popular as of 1999] are macro collections. The differences between them involve how they are built in the sub-strata of the base die. CBA designs led the size war for some time; standard cells now produce typically smaller die sizes. Approximate estimates were for 10,000 arraystarts in 2000; spilt 50-50 between these two technologies, the first time standard cells had come on so strong. Metallization layers are the customizable layers in a semi-custom array. Metallization, which sits on top of the base die, currently runs to 6 layers, 4 for interconnect and 2 for power-ground, although this may vary. The number of layers of metalization is expected

to increase. Keep in mind that between each routing metalization layer is a layer of vias, the vertical interconnects.

Simple Semi-custom Devices

At the simplest end of the semi-custom spectrum are gate arrays, providing one level of interconnect to the user for specification with all other connections defined. Programmable devices such as PLAs (programmable logic array), PALs (programmable array logic), field-programmable muxs, sequencers, gate arrays, and other modules are available for limited quantity applications. (PLAs allow both AND and OR gates to be programmed PALs allow only the AND gates to be programmed.) Programmable devices are restrictive in the functionality provided. They are suitable and competitive when there is a match between a module and the current application. Field-programmable devices are to VLSI what the ROM/PROM is to the microprocessor, i.e., they support and enhance the design project. These devices provide board-clean-up functions, incorporating the simple functions that do not fit into a full semi-custom array or that were found necessary to augment in a bit-slice or fixed instruction set design. They are still with us

Selection
The choice between full-custom, semi-custom, fixed or simple gate-level custom is based on several factors. These include: architectural requirements, interface technology requirements, size restrictions, speed (maximum worst-case operating frequency), power limitations, power supply options, manufacturing cycle time, cost, packaging options, and design time. Figure 1-3 characterizes the problem.

Basis for Discussion

The discussion in this text will refer primarily to Applied Micro Circuits Corporation arrays for examples of current technology. These include: Bipolar arrays: the Q5000, and the Q20000 Series; and BiCMOS arrays: the Q14000 and Q24000 Series. However, the design methodology; can be applied to any arrays from any vendor for any array technology and to any future arrays developed by AMCC and the other array vendors.

The design methodology is generic. It is vendor and technology-independent.

WHERE DO YOU START?

Figure 1-3 The Selection Problem

Note:
Later chapters in this text refer to engineering workstations (EWS) and the methodology for their use in the design process. Workstations that are specifically referred to are: the Mentor Graphics System on Apollo and the Valid on SUN. Simulators referenced include Verilog on SUN4 and Lasar 6 on the VAX under VMS. The basic tools required for a design remain the same regardless of the workstation, platform, framework or mainframe used.

Circuit Architecture
A fixed-instruction set microprocessor or sequencer has a predefined architecture and instruction set. A bit-slice solution places some constraints on the designer in terms of architecture but leaves most of the definition to the user by way of the selected interconnections between bit-slice modules and the microprogram control. An SSI/MSI implementation allows the designer the specify in complete, exact detail the architecture desired. The SSI/MSI design can be implemented in full custom or semi-custom VLSI. Bit-slice modules can be emulated on arrays. The ASIC arrays are big enough to support a

complex ALU module but not yet large enough for one array to replace a full microprocessor.

Which Array Technology?

The broad categories of technologies are CMOS, BiPOLAR, BiCMOS, and GaAs. Figure 1-4 provides a family tree of the most common technologies, at least at this moment. Array technology is a subject in itself and the reader is referred elsewhere for detailed discussions on any specific process. Figure 1-4a The Dominant Technologies

Bipolar as used in conjunction with arrays in this text refers to ECL-internal with TTL, ECL 10K, ECL 100K I/O modes, or mixed ECL/TTL interface capability. Not all arrays offer the ability to mix TTL and ECL or to mix ECL 10K and ECL 100K on one chip. Some arrays may limit the types of macros that can be placed on the I/O cells. Design limits imposed by these restrictions are generally based on the array technology. The AMCC BiCMOS has the same interface capability as the bipolar arrays while providing a CMOS internal core. BiCMOS interfaces include CMOS, TTL, ECL 10K and ECL 100K and combinations of all. Not all BiCMOS arrays offer the ability to mix TTL and ECL or ECL 10K and ECL 100K on one chip. Figure 1-4b Relations among Silicon Technologies

Ref: Design of VLSI Gate Array ICs by Ernest E. Hollis

Technology differences for VLSI are primarily speed and power. CMOS is lower speed, lower power. Bipolar at 600MHz or 1.2GHz and up is faster with a high power dissipation (5-7, up to 16 watts for the fastest arrays is not unusual). BiCMOS is intended to be a combination of these two, providing a reasonable speed (about 130MHz and up) at greatly reduced power dissipation. The actual maximum frequency of operation and the power dissipation will vary from series to series even within the technologies. Data sheets for the array series of interest should be reviewed and compared as a first method of estimation for applicability.

Obtain Data Sheets from several vendors

Note: One array series may be lower power at one frequency and higher power at another. Comparisons must be made using equivalent conditions. When the conditions are not specified, ask! All vendors maintain Field-Application Engineers that can explain how measurements were taken or what assumptions were used. Figure 1-4c Relations among Technologies

Size
The physical size limitations imposed on a design can dictate the design approach.

Base Arrays
Base arrays come in a variety of sizes, usually specified in terms of equivalent gates. The arrays discussed herein range from 250 to 28000 gates, depending on the computational approach used. Equivalent gates; allow a relative sizing between arrays of the same technology. The gate used as an equivalent gate for bipolar arrays is the NOR gate, that used for BiCMOS arrays is the NAND gate. Equivalent gate sizing can be misleading. For a CMOS array, one gate is typically one cell. For the Q24000 Series BiCMOS arrays, one internal cell is approximately 4 equivalent gates.

Today''s arrays are custom-designed to the project. The determination of the die size and the number of I/O is computed from initial evaluations based on the specification.

Cells
The actual cells; available on a bipolar array are larger and more complex, and can support a large variety of macros. A Q5000 Series logic cell (internal) can support: a 4:1 MUX, a 1:4 decoder, a scan-set D F/F, an 8-input OR/NOR, three latches or 2 D flip/flops. A 4-bit universal register (4 4:1 MUXs and 4 D flip/flops) requires 4.5 logic cells. A 4-bit carry-look-ahead adder with carry-out requires 5 logic cells. The 4-bit carry-look-ahead adder in the Q14000 Series BiCMOS arrays macro library requires 14 basic cells or 56 gates. The Q20000 Series L-cell is sized based on one Turbo output; per cell and is smaller than a Q5000 cell. A flip/flop that uses 1 cell in the Q5000 Series may use 3 cells in the Q20000 Series. Estimating cell counts requires access to the macro library. Basic sizing information such as cell counts and die sizes; can be obtained from the data sheets. Many circuit modules can be equated to cell counts by the specific array vendor. These estimates can be used for initial circuit sizing.

Array Size - Die Size

A full custom design may or may not be smaller in die size than a semi-custom design. For a heavily populated array, the differences may be insignificant. The comparison must be based on the specific application and the skill of the designer.

Packaging
For arrays, the die size, the number of I/O pads, and the number of power and ground pads used affect available packaging;. A number of standard packages; are usually available for each array and the data sheet for an array series will provide the designer with an initial table of available packages. If less than the maximum number of I/O cells is used, some smaller packages may be usable. The package selection; affects package pin capacitance;, which affects loading delay for output pins;, junction temperature; computations and cooling considerations;, and final cell placement;, which also depends on the pin capacitance, and should be made well before final design completion.

Word Length
The word length necessary for the system, whether a computer, controller, signal processor, etc., is known in advance. This is seen as the width of registers, partitioning of counters, width of adders, and number of simultaneously switching outputs; (SSOs). It affects the partitioning and modularity of the design. The adders; available with a macro library are typically 4-bit adders, cascadable with the carry-look-ahead; macro to build a range of standard adder sizes. With a macro design,

the available MSI macros and SSI logic can be used to provide a range of non-standard word lengths. Counters; are typically 4-bits wide, expandable to 12 or 16 bits in width. Comparators; are modulo 6. Registers; come as 4-bit widths and latches; as 8-bits (octal latch). Larger macros are also under development or custom structures may be possible.

Instruction Set
The instruction set; that the system is to support is another major impact on the design implementation selection. By building a custom or semi-custom array, the hardware can be configured to support any instruction set yet have the advantages of still being a VLSI solution.

Speed
The maximum frequency of operation; specified for the circuit must be compared to that available for the array series or the off-the shelf components. The nature of the design may make it necessary to look at the toggle frequency; of the internal functions. The maximum frequency of operation, of interface as well as internal macros, is very important but it is not the only consideration when evaluating the performance that can be achieved. Due to loading delays, the final performance will depend heavily on the implementation possible with the given macros or possible custom macros, their drive factors; and load limits;.

Achievable speed is a function of both the experience of the designer in general and the macro library in specific.
As an example, three implementations of a test circuit were made with the Q3500 Series and they varied from 145MHz to 233MHz (worst case maximum speed limits). The variance was found to be solely a function of the macros selected. This type of performance variance can be repeated for almost any circuit of any reasonable size. Speed, cell utilization (silicon density) and power can be traded off among the different possible implementations. This diversity is an advantage as well as a design challenge.

Macros - Libraries - Etc.

The existence of an extensive macro library;, or even one that supports the circuit function for the application at hand, can sway a decision as to which product to select. For the arrays of interest, the designer needs to review the existence of a macro library. If the array has a macro library, review the macros available for application to the intended design.

Macro Library
In an array macro library;, macros; already released are available without delay. They represent pre-modeled, pre-simulated, pre-verified logic blocks. Their interconnect patterns are already defined for the various mask levels.

Custom Macros
If custom macros; are needed for a semi-custom array library, they involve 2-3 masks layers. If a custom macro has to be built for addition to a full custom array library, it is a multi-mask level design task.

Silicon Compilers
Silicon compilers provide a translation from a design description to pre-defined macros. They provide support for designers who wish to stay at a higher level in the design process. A silicon compiler can be compared to a software compiler it will speed the design process for the engineer at the cost of some flexibility. Like framework systems, the industry has no set standard to measure or define exactly what a silicon compiler can do. They remain in isolated use, faced with the same resistance that software compilers met on their first introduction.

Other Support
Regardless of the design implementation;, a certain amount of software design support; is required. Error checking;, annotation;, simulation;, testability analysis;, fault-grading;, and vector rules checking; are some of the support areas pre-layout. After placement, there are placement rules checking, bus current checking for those arrays which require it, finalization of overhead current computations (for those arrays with programmable overhead), and finalization of power dissipation computations.

Design-Support Issues
The basic questions involving design support; which must be asked when selecting any array include: 1. ) Which workstations are a prospective library or parts catalog available on? What main-frame? Is the library accessible for a customer-site or must dial-up be used? 2. ) What error checking; at the schematic level is available? Are there engineering rules checks (ERCs) to check on valid names, fan-out loading, population counts, current sums, power dissipation, technology mix-ups, array pad count, and interconnection restriction violations need to be caught before simulation. 3. ) What about Front-, Intermediate- and Back-Annotation;? These are needed for metal length and load evaluation and the impact of these on the timing. The ability of the annotation software to handle rise and fall load factor; differences and metal layer; differences needs to be clearly identified. Is there provision for output capacitive load (system and package pin capacitance).

4. ) Are there support tools; for simulation? Simulation control files, reformatters, and vector checking; are required. Timing verifiers; are important when path matching; is required. Other software that is useful for bit-slice, all arrays and any microprogrammable architecture device is a meta-assembler;. This software allows a program or vector set to be described in a user-defined language (a pseudo-assembler) and compiled to ones and zeros. It provides the designer with the ability to code the vectors in pseudo-English for readability. An example is MICRO2 from Digital Equipment Corporation. Also for simulation, what about automatic test generation; (ATG)? Are designfor-test; (DFT) macros and support software available to allow the use of this tool? 5. ) How does placement; enter into the design sequence? This would be board placement for components or cell placement for a semi- or full-custom design. Does the software offer some assistance to the user in drafting a placement file? What checking software is provided either on the workstation or is accessible by dial-up?

Workstations, Mainframes, Dial-up

When evaluating an array library on a workstation, there must be a match between the operating system, the graphics editor; and simulators and the macro library;. Each installation document for a line of workstations specifies the versions of the vendor software with which that the library is compatible. Check with the vendor summaries published by several technical magazines for an initial review or check with the array vendor for a more updated list of equipment and software compatibility. Most array vendors offer support for several workstations. The workstations are not restricted to semi-custom or single array design support. They offer component libraries for board design through simulation. Multiple-array simulations are possible if the array is correctly modeled and there is enough memory.

Design-Support Issues
Schematic Rules Checking
Each workstation has a modest schematic checking pass that it makes on the way to generating the workstation-specific netlist. The error reports; from these checking routines should be checked and all pertinent errors removed. If a partial circuit is being compiled, there may be interconnect errors; that need to be ignored. The checks are not exhaustive, but later software will assume that these checking routines were successfully passed.

Workstation checks include one-ended nets, undriven page inputs, page outputs with no destination, naming confusion, missing blocks, and an attempt at duplicate name detection. AMCC provides engineering rules checking (AMCCERC;) for commonly made schematic interconnect and design errors including too many cells for the array checked by cell type and macro type, too many fan-out loads, improper connections for 3-state and bidirectional enables, improper characters in names or too long names, improperly connected wire-ORs, dangling pins, grounded outputs, and terminated inputs. It is one of the most complete packages in the industry today. As a part of the AMCCERC package, internal current, worst-case power dissipation for bipolar arrays, fan-out loading tables, simultaneously switching outputs reporting and power-ground checking, an I/O list, a package data list and a detailed population report are generated. Once placement is completed, these reports have a final form that becomes part of the device specification.

Annotation
Front-Annotation; is the estimation of interconnect (pin to pin) delays in an array due to electrical fan-out loading, electrical wire-OR loading and estimated metal loading. The metal load delay estimate; is a statistical estimate based on the net size;. It is available pre-placement. Intermediate-Annotation uses a refined estimation of the metal load delay based on the relative placement of the individual macros in an array. The electrical fan-out loads and electrical wire-OR loads remain the same. Intermediate-Annotation is generated postplacement but pre-routing. Back-Annotation uses the final, actual metal load delay computed from the known metal lengths for the metal layers involved in the interconnect. It is available post-routing. The availability of the annotation software, its ease of use, and the ease of integration into the simulation database is an important concern. Output capacitive load delays; for system capacitive load; and package pin capacitance; affect the overall path delay. The ability to specify these loads and to have their delays included in the simulation database is another item of concern. If this feature is not available, the computation must be manually performed.

Simulation Support
Every simulator has its own unique format requirements; for simulation input files. The stimulus, its switching waveform, the operating condition (military, commercial, nominal or minimum) library, sampling rates; or print on change recording, output file format, and input file format if a binary file can be read. The workstation may offer several methods of simulation and timing verification. The vendor may only accept certain files or file formats;. List and waveform displays; are

available on the three previously listed workstations. Data can be displayed in binary, octal, decimal and hex format.

Reformatters
If a standard simulation vector format; is required by the array vendor or by software to which the simulation results must be submitted as data, some means of reformatting must be available. For arrays, the functional, parametric, and AC test simulation results are generally used as input to test vector generation; software, and the allowed input formats may be restricted.

Example
AMCC accepts only binary results for specific signals (input, output, bidirectional, 3state and bidirectional enable internal signals). Sample size is restricted. No print on change; results are used for functional simulations, only sampled. No waveforms are requested. Since there are different simulation output formats, AMCC customers use a reformatter to translate Dazix, MENTOR, Verilog, Lasar and VALID simulation output files into a generic format. If any other workstation is used, the output of that simulator must also be reformatted. AMCC uses their AMCCSIMFMT; software to transpose output files into an AMCC generic interface format that their test software programs can read.

Rules Checking
Regardless of the implementation selected, the design must be simulated and the parts tested. There may be a number of functional, parametric and AC test simulation vector rules; that must be followed to insure correctness in the test program. The rules are based on tester limitations;, test procedures and test objectives. The rules required by the array vendor must be clearly stated and it is increasingly desirable to have some form of rules check software available to help the designer. AMCC supplies a vector checker, AMCCVRC;, to catch the more blatant vector rule violations such as missing required signals, too many signals switching in one vector causing noise, race conditions, undesired internal signals in the output and uneven sampling steps. Some basic toggle tests are also included.

Submission Assistance
The design submission process for custom and semi-custom arrays requires a number of specific forms, files and validation procedures be followed and the process is increasingly complex. Automation of that procedure is one desirable goal. Automation support is feasible for the I/O signal list;, package pad-pin-post, capacitive load; and I/O toggle frequency; descriptions, design validation; checklists and design submission; checklists, including simulation submission. If no automated support is available, the necessary forms must be reviewed and filled in manually. Errors and incomplete information can lead to schedule delays. (Refer to the framework systems.)

Placement
As a part of the submission process for custom and semi-custom arrays, the designer may wish to submit a desired placement or partial placement. The vendor must supply placement; rules and restrictions for the particular array in the selected package as well as a placement worksheet. The user may be able to choose between a full graphic interface to the placement system or be content to supply the vendor with an ASCII list for placing some or all the macros, and let the vendor complete the placement process. The options and the control over placement become an issue when performance is driven to the limits of the array technology. I/O placement is an issue when an array will emulate an older technology and the PC board array pin out pattern must remain unchanged.

Design-Support Issues
Design Upgrades
A semi-custom array, full array or bit-slice design can be upgraded more easily than an LSI/MSI/SSI component or a fixed-instruction set microprocessor design. For bit-slice, if the design enhancements are known at the time of the original design, allowances can be made through interconnections and functional capabilities that are not accessed until a microprogram accessing these features is incorporated. Many changes can be made with microprogram changes alone. For semi-custom arrays, if the design enhancements are known in advance, the arrays can be partitioned to leave room for future macro additions or the macro functions could even be incorporated. As with bit-slice, the added capability is simply not accessed until required. If the design enhancements (evolution) are not known, but are anticipated to occur, the allowances for expansion may be anticipated. The designer may provide room for the design changes to be incorporated onto the older schematics, with additional vectors to be added to the existing simulations. The design is thus easily revised.

Tradeoffs
The designer must evaluate the all the items discussed in this chapter to make a selection as to the best method of implementation for a specific circuit design. From there, the designer must further evaluate to find the best components available within the chosen category of implementation.

Exercises
1. To select a design approach, the following are questions that may need to be answered:

What architecture does the design require What flexibility can be allowed in the implementation What package types are desired versus what package types are available What operating environment (Commercial, Industrial or Military) What cooling considerations have been made (heat sinks, air flow) What is the required interface to the outside world What is the required I/O mode (ECL, TTL, CMOS, MIXED ECL/TTL) What power supplies are available (+5, -5.2, -4.5,+5 with -4.5 or +5 with -5.2v) How many of the required I/O signals are inputs How many of the required I/O signals are outputs How many of the required I/O signals are bidirectional What type(s) of TTL: Totem pole, open collector or 3-stated What type(s) of ECL: ECL 10K, ECL 100K, on-chip series termination, off-chip series termination, differential, open collector, Darlington, etc. What about CML What about CMOS What are the physical size limitations imposed on the design What word length is required for an adder, ALU, counter, sequencer What instruction set or commands are to be supported How big is the design (equivalent gates) What is the intended maximum frequency of operation including I/O toggle frequency for the circuit, i.e., what are the performance requirements How much design time has been allowed What design support is available How much debug time has been allowed What debug support is available What simulation support is available What simulators What timing verifiers What about testability support Are upgrades to the design planned and if so, how easily can a design be revised What upgrades to the component series are planned What are the possible time schedules for o design review: o design to prototype o prototype to production What are the overall cost limitations

Review these questions. Catalog them as to design-specific, array-specific, component vendor-specific and workstation-specific. What other questions might need to be asked before a design implementation approach (semi-custom, full-custom, fixed components, bit-slice, or gate array) can be selected? 2. Review the latest issues of ASIC News and at least one other ASIC related magazine. a. Locate two articles on framework systems.

b. Locate two articles on HDL and VHDL. c. Locate at least one survey on expected growth of demand for ASIC arrays: bipolar, BiCMOS, CMOS and GaAs.

Update 2000
When I first wrote this book, I had spent a considerable amount of time in the Bit-Slice and ASIC industry. The book reflected the design procedures at that moment. It was a reflection of the class I taught at AMCC and at UCSD for 11.5 years. From there I developed and taught the technical training classes for CBA (cell-based array) designs. Now, even CBA is beginning to fade as standard cells take over a the dominant arraybased technology. As of January 2001, there have been some changes, although not as many as people would like to think. The basic design flow? - It is still with us.

The size of the designs has changed from what could be handled by a human (up to 50,000 gates) to what must be handled by a computer (12 million gates). We are seeing designs that run 4-6 millions gates per ASIC and will be seeing 10-12 million designs shortly. Wafers have gone from 3" to 6-8" and are headed for 12". From primarily bipolar, I now work almost exclusively with CMOS. The process technology has gone from 5 microns to 0.18 deep sub-micron, and everything bipolar designers worried about is now the headache that concerns CMOS designers - namely, that gate delays are practically negligible compared to interconnect delays. DSM (deep sub-micron) refers to this phenomena. By 1998, CBA ASICs still ruled, but by 2000 standard cells had become dominant, producing smaller and faster designs. Libraries still exist but now macro selection is by a synthesis software package and 85% of designs are done with the Synopsys Design Compiler package. Cadence now has a competitive synthesis package. Schematic capture is pretty much an anachronism and design are specified in Verilog or VHDL (RTL). Software tools take the design from RTL (register-transfer logic) through waferverification, with software like Dracula, Vampire), performing ATT (antenna checking), ERCs (electrical rules checking), DRCs (design rule checking). Manual operations are no longer feasible. RAM and ROM onboard an ASIC is no longer unusual. IP (intellectual property) blocks are in common use. Design-Reuse is a buzzword. IP may be multi-layered and fixed (hard IP), or soft IP where a netlist is incorporated and the block may be altered by synthesis steps. Vectors are generated by automatic test vector generation software. Designs are made DFT (design for test) as a routine step in the compile process. DFT is no longer an option. Software can tell you if your design is testable and if it is routable. Place and Route are no longer a last step in the process. Floorplanners are required for any sizable design. Cadence's Gate Ensemble and Silicon Ensemble were the leaders in Place and Route. Synopsys has the Chip Architect

floorplanner. Cadence has the Logical and Physical design planners. Avant! has Planit! for floorplanning tasks. Everybody's floorplanner has to talk to everybody's synthesis tool and they both have to talk to everybody's place & route software. Everybody has to talk to PrimeTime. What AMCC called "intermediate annotation" is what is produced during floorplanning and it's use is not optional.. EDIF became the standard for netlists. There is no more concern about whose netlist went where. EDIF is used to input to floorplanners, and EDIF is produced by the synthesis tools and by the place & route tool. DB has become a standard format. DEF (design exchange format - Cadence) became the standard for input to place & route PDEF 2.0 is the standard output of the floorplanners and is now standard input to place & route software. PDEF 3.0 is on the horizon. SDF 2.0 is used for delay files and can be created by PrimeTime from delay information from most floorplanners and place & route tools. SPICE files are still with us VCS, VSS and related tools perform simulation. GDSII is for building the basedie layers and GDSII is produced by the place & route software PrimeTime is the standard for static timing analysis (85% of design are verified with that software). Designers no longer have to "fit" their designs into a fixed-size chip with a fixed I/O count (cells in the I/O ring). Dies are designed to fit the design. Holes are punched through the layers to accommodate IP blocks (Hard IP blocks) and software exists to "stitch" the IP blocks into the basedie. You may not "diddle" with parametric specifications. If you have a different set of operating conditions, you must go back to the library vendor for new library specifications. The slightest variation can have dire consequences in the results. The axiom that the engineer who knew the library could do better designs than a more experienced engineer who did not, still holds. You may "direct" the use of macros by the synthesis tools. Tcl has become the standard interface scripting language.

In fact, Synopsys alone has approximately 42 different software tools available to help create an ASIC design. Design flow from RTL to wafer fab is the focus of most vendors today.