Computer Networks And Management

Submitted by, M.Sreekrishna, MCS17.

IEEE 1394It is to strength the topology monitoring. It is to normalize topology form with self-ID packets. It is based on postorder traversal algorithm. Applying the algorithms and using Visual C++ and Windows XP DDK, topology Visualization is realized.

The result is constructed accurately and displayed in time.

It is beneficial to implement fault-tolerant management of bus topology.

It designed as a high speed data bus for consumer electronics. Future military vehicle are likely to use IEEE 1394. It is hot-pluggable. The bus has a tree topology, so if a branch node fails, the bus will be partitioned. Here, a dual redundant bus architecture, and a triple redundant bus architecture is used It monitor nodes connection relationships and assess the faulttolerant bus architecture.

It reorganize the previous topology information into a normalized topology Steps involved: A node derives a normalized topology form self-ID packets. The comparison of a saved copy of a normalized topology accurate before the bus reset with the newly derived normalized topology, which determines unique identity of the unchanged nodes.

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 Reset Forced whenever node is attached or removed. Tree Identification Transforms a non-cyclic topology into a tree with a root node at its head Self Identification Assigns physical node number (Node ID), exchange speed capabilities with neighbors, broadcast basic capabilities

After reset, each node only knows if it is a leaf or a branch.

1394 allows loop

Tree identification #2
After Tree ID process, the Root node is determined and each port is labeled as pointing to a child or a parent Root assignment is sticky, will normally persist across a bus reset. 1394 break loops
in tree ID

1394 breaks any loops on beta connections even before Tree ID starts

After the self ID process, each node has a unique physical node number, and the topology has been broadcast.

Suppose nodes #0 and #2 start to arbitrate at the same time, they both send a request to their parent

The parents forward the request to their parent and deny access to their other children

The root grants access to the first request (#0), and the other parent withdraws it's request and passes on the deny.

The winning node #0 changes its request to a data transfer prefix, while the loosing node #2 withdraws its request.

The parent of node 1 sees the data prefix and withdraws the grant, and now all nodes are correctly oriented to repeat the packet data.

A specification Enable consistent definition of the management information required to manage Carrier Ethernet. A Model a new physical topology discovery algorithm which works without complete knowledge of Address forwarding table entries Scope Ethernet (ETH) layer UNI configuration provisioning ETH layer configuration and provisioning ETH layer network connection and fault management (including setup/modification, notification, testing)

Provides a frame work and concepts for managing and monitoring flows across a connectionless network from end to end Provides mechanism to perform: Node Discovery, Establish connectivity, monitor CoS, and detect service impairments.

Many new Military designs are employing high speed data buses Stimulate the widespread adoption of digital displays for high-performance desktop and mobile PCs Transition Minimized Differential Signaling (TMDS).

ATC not only depends on the topology of power network but also on the parameters of components. ATC of inter-connected power system can be described as follows: ATC=TTC-TRM-CBM-ETC where , TTC Total Transfer Capability. TRM Transmission Reliability Margin. CBMCapacity Benefit Margin. ETCExisting Transmission Commitment

Using the analytical formulas we can effectively identify ATC bottlenecks and get important guide information for investment of decision-making and maintenance.

Reason for introducing Extreme Value Theory,

It avoids the difficulty in characterizing end-to-end performance. Defining Service Level Agreements (SLA) between numbers of organizations. Reduces the variable space required for discrete event simulations (DES).

The GIG is designed to improve, 1.Interoperability 2.Information sharing among warfighters 3.Logistics 4.Intelligence 5.All DoD business processes.

Much better human interface Smaller, more rugged connectors with defined usage Hot plugging, no manual configuration Excellent real performance High true data rates Direct map to processor I/O model DMA is simple: CPU memory directly available peripherals.