FPGA Based System Design

1 ENGR. RASHID FARID CHISHTI LECTURER,DEE, FET, IIUI CHISHTI@IIU.EDU.PK WEEK 1

DIGITAL LOGIC DESIGN REVISION

www.iiu.edu.pk

Saturday, July 21, 2012

Review of Logic Design Fundamentals

Combinational Logic

Boolean Equations
Karnaugh Maps Hazards

NAND, NOR Representaion

Combinational Logic
3

Has no memory Output depends only on the present input

x1 x2 Combinational Logic z1 z2

xn

zm

Note: Positive Logic low voltage corresponds to a logic 0, high voltage to a logic 1 Negative Logic low voltage corresponds to a logic 1, high voltage to a logic 0

Boolean Equations
Types of Boolean Equations Canonical Form Sum of Min Terms
F(A,B,C)

= ABC + ABC' + AB'C + AB'C' + A'B'C

Product

of Max Terms
= (A+B+C ) (A+B'+C) (A+B'+C' )

F(A,B,C)

Standard Form
Sum

of Products (SOP)
= A + B'C
= (A+B+C) (A+B')

F(A,B,C)

Product

of Sums (POS)

F(A,B,C)

Min Max Terms

(Canonical Form)

Example: Express the Boolean function F=A+B'C as a sum of min terms and product of max terms
F = = = = = = = = = = = A + B'C A (B + B') + B'C (A + A') AB + AB' + AB'C + A'B'C AB(C + C') + AB'(C + C')+ AB'C + A'B'C ABC + ABC' + AB'C + AB'C'+ AB'C + A'B'C ABC + ABC' + AB'C (1 + 1) + AB'C'+ A'B'C ABC + ABC' + AB'C (1) + AB'C'+ A'B'C ABC + ABC' + AB'C + AB'C' + A'B'C 111 + 110 + 101 + 100 + 001 7 + 6 + 5 + 4 + 1 (1,4,5,6,7) = (0,2,3)

K-maps
Convenient way to simplify logic functions of 2,3, 4, 5, (6)

variables In a Four-variable K-map

each square corresponds to one of the 16 possible minterms 1 = minterm is present; 0 (or blank) = minterm is absent; X = dont care the input can never occur, or the input occurs but the output is not specified adjacent cells differ in only one value => can be combined

Location of minterms

K-maps

Three Variable K-maps

Map for F(x,y,z) = (3,4,6,7)
yz yz x
0 00 01 11 10

1
1 1 1

xz'

After Simplification F = yz + xz'

Four Variable K-maps

K-Map for F(A,B,C,D) = (0,1,2,6,8,9,10)
CD
AB
00 00 01 11 10

B'C'

01

A'CD'

11

10

B'D'

After Simplification F(A,B,C,D)= B'D' + B'C' + A'CD'

Four Variable K-maps

K-Map for F(A,B,C,D) = (0,1,2,5,8,9,10)
CD AB
00 00 01 11 10

CD

1 0 0 1

1 1 0 1

0 0 0 0

1 0 0 1
AB

01

BD'
11

10

After Simplification F'(A,B,C,D)= AB + CD + BD' So F(A,B,C,D)= (A'+B') (C'+D') (B'+D)

Using Dont Care in K-maps

F = yz + w'x'

F = yz + w' z

Five Variable K-maps

F = ACE + A'B'E' + BD'E

Six Variable K-maps

Hazards in Combinational Networks

What are hazards in Combinational Network? Unwanted switching transients at the output (glitches) Example ABC = 111, B changes to 0 Assume each gate has propagation delay of 10 ns
A = 1

B = 1 0

F = 1 0 1 F = AB' + BC C = 1

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A = 1
B = 1 0

F = 101 F = AB' + BC

C = 1

B D

E
F

0 ns

10 ns

20 ns

30 ns

40 ns

50 ns

60 ns

Hazards in Combinational Networks

Occur when different paths from input to output have

different propagation delays Static 1-hazard

a network output momentarily go to the 0 when it should remain a constant 1

Static 0-hazard a network output momentarily go to the 1 when it should remain a constant 0
Dynamic hazard if an output change three or more times, when the output is supposed to change from 0 to 1 (1 to 0)

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Removing Hazard
AB C
0

AB
00 01 11 10

C
0

00

01

11

10

1 1 1 1

1 1 1 1

f AB' BC
B A D E
F = AB' + BC

f AB' BC AC
B A D E

C
A

F=AB'+BC+AC

To avoid hazards: every pair of adjacent 1s should be covered by a 1-term

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Removing Hazard

B
UAHCPE/EE 422/522 AM

A C A

E D G
F=AB'+BC+AC

D
E G F 0 ns 10 ns 20 ns 30 ns 40 ns 50 ns 60 ns

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Hazards in Combinational Circuits

Why do we care about hazards? Combinational networks

dont care the network will function correctly

Synchronous sequential networks dont care - the input signals must be stable within setup and hold time of flip-flops Asynchronous sequential networks hazards can cause the network to enter an incorrect state circuitry that generates the next-state variables must be hazard-free Power consumption is proportional to

the number of transitions

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Removing Static 1- Hazard

F(A,B,C,D) = (0,1,4,5,6,7,14,15) = A'C' + BC

CD
AB
00 00 01 11 10

Cover the cube by adding A'B to eliminate the static 1-hazard

A'C'

01

1
0

1
0

1
1

1
1
BC

11

10

0
F = A'C' + BC + A'B

Removing Static 1- Hazard

In the logic diagram of F = A'C' + BC With a = 0, b = 1, and D = 1, a glitch can occur as c changes from 1 to 0 or visa-versa. So we add the redundant term A'B by overlapping the two groups to eliminates the static 1-Hazard

Removing Static 0- Hazard

F(A,B,C,D) = (0,1,4,5,6,7,14,15) = (A' + C) (B + C')

AC'
CD
AB
00 01 11 10 00

Add AB' to eliminate static-0 hazard Note: AB'D covers too, but is not minimal.

01

1
0

1
0

1
1

1
B'C

11

10

F' = AC' + B'C + AB'

So

F = (A' + C) (B + C') (A' + B)

Dynamic Hazard (Multiple glitches)

Dynamic hazards are a consequence of multiple static hazards

caused by multiply re-convergent paths in a multilevel circuit. Dynamic hazards are not easy to eliminate. Elimination of all static hazards eliminates dynamic hazards. Approach: Transform a multilevel circuit into a two-level circuit and eliminate all of the static hazards.

Dynamic Hazard (Multiple glitches)

The redundant cube eliminates the static 1-hazard and assures that F_dynamic will not depend on the arrival of the effect of the transition in C.

Dynamic Hazard (Multiple glitches)

Designing with NAND and NOR Gates (1)

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Any logic function can be realized using only NAND or

NOR gates Implementation of NAND and NOR gates is easier than that of AND and OR gates (e.g., CMOS)

UAH-CPE/EE 422/522

AM

21/07/2012

NAND Gate
28

NAND Gate
29

NAND Gate
30

NAND Gate
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