MIPS

Instruction Set Design - Goals
Maximize Performance Minimize cost Reduce Design time (time-to-market) minimize memory space (embedded systems) minimize power consumption (mobile systems)
2004 Morgan Kaufmann Publishers
RISC - Reduced Instruction Set Computer
RISC philosophy fixed instruction lengths load-store instruction sets limited number of addressing modes limited number of operations MIPS, Sun SPARC, IBM PowerPC
Instruction sets are measured by how well compilers use them as opposed to how well assembly language programmers use them
CISC (C for complex), e.g., Intel x86
Instruction Set Architecture (MIPS: Microprocessors without Interlocked Pipeline Stages)
Four design principles guide

Simplicity favors regularity Smaller is faster Make the common case fast Good design demands good compromises
Instructions:
Language of the Machine Well be working with the MIPS instruction set architecture similar to other architectures developed since the 1980's Almost 100 million MIPS processors manufactured in 2002 used by NEC, Nintendo, Cisco, Silicon Graphics, Sony,
1400 1300 1200 1100 1000 900 800 700 600 500 400 300 200 100 0 1998 1999 2000 2001 2002 Other SP ARC Hitachi SH PowerPC Motorola 68K MIPS IA-32 ARM
Instruction set: The vocabulary of commands understood by a given architecture.
Stored-Program Concept : The idea that instructions and data of many types can be stored in memory as numbers, leading to the stored program computer.
2.2 Operations of the Computer Hardware
MIPS arithmetic
All instructions have 3 operands Operand order is fixed (destination first) Example: C code: a = b + c
MIPS code:
add a, b, c
(well talk about registers in a bit)
The natural number of operands for an operation like addition is threerequiring every instruction to have exactly three operands, no more and no less, conforms to the philosophy of keeping the hardware simple

FIGURE 2.1 MIPS architecture revealed in section 2.2.
MIPS assembly language

Category Instruction Example Meaning Comments
Arithmetic
add
add a, b, c
a=b+c
Always three operands
subtract
sub a, b, c
a=b-c
Always three operands
f = (g+h) - (i+j); add t0, g, h add t1, i, j sub f, t0, t1
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MIPS arithmetic
Design Principle: simplicity favors regularity. Of course this complicates some things... C code: a = b + c + d;
MIPS code:
add a, b, c add a, a, d
Operands must be registers, only 32 registers provided Each register contains 32 bits Design Principle: Smaller is faster. Why?
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f = (g+h) - (i+j); $s0, $s1, $s2, $s3, $s4

add t0, $s1, $s2 add t1, $s3, $s4 sub $s0, t0, t1
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Assuming variable b is stored in register $s1, c is stored in $s2, and d is stored in $s3 and the result is to be left in $s0, what is the assembler equivalent to the C statement h = (b - c) + d
sub
add
$t0, $s1, $s2

$s0, $t0, $s3
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2.3 Operands of the Computer Hardware
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Data transfer instruction: a command that moves data between memory and registers. Address: A value used to delineate the location of a specific data element within a memory arry.
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Registers vs. Memory

Arithmetic instructions operands must be registers, only 32 registers provided Compiler associates variables with registers What about programs with lots of variables
Control Memory Datapath

Processor
Input
Output
I/O
16

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Memory Organization
Viewed as a large, single-dimension array, with an address. A memory address is an index into the array "Byte addressing" means that the index points to a byte of memory.
0 1 2 3 4 5 6 ...
8 bits of data 8 bits of data 8 bits of data 8 bits of data 8 bits of data 8 bits of data 8 bits of data
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Memory Organization
Bytes are nice, but most data items use larger "words" For MIPS, a word is 32 bits or 4 bytes. 0 32 bits of data 4 32 bits of data Registers hold 32 bits of data 32 bits of data 8 12 32 bits of data ... 232 bytes with byte addresses from 0 to 232-1 230 words with byte addresses 0, 4, 8, ... 232-4 Words are aligned i.e., what are the least 2 significant bits of a word address?
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FIGURE 2.2 Memory addresses and contents of memory at those locations.
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FIGURE 2.3 Actual MIPS memory addresses and contents of memory for those words.
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Compiling with Loads and Stores

Assuming variable b is stored in $s2 and that the base address of array A is in $s3, what is the MIPS assembly code for the C statement A[8] = A[2] - b
... A[3] A[2] A[1] A[0]
... $s3+12 $s3+8 $s3+4 $s3
lw
$t0, 8($s3)
sub
sw
$t0, $t0, $s2

$t0, 32($s3)
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g = h + A[8] lw $t0, 8($s3) add $s1, $s2, $t0
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Instructions
Load and store instructions Example: C code: MIPS code: A[12] = h + A[8]; lw $t0, 32($s3) add $t0, $s2, $t0 sw $t0, 48($s3)
Can refer to registers by name (e.g., $s2, $t2) instead of number Store word has destination last Remember arithmetic operands are registers, not memory! Cant write: add 48($s3), $s2, 32($s3)
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Dealing with Constants

Small constants are used quite frequently (50% of operands in many common programs)
e.g., A = A + 5; B = B + 1; C = C - 18;
Solutions? Why not? Put typical constants in memory and load them
How do we make this work?
How do we Make the common case fast !

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Constant (or Immediate) Operands

Include constants inside arithmetic instructions Much faster than if they have to be loaded from memory (they come in from memory with the instruction itself) MIPS immediate instructions
addi
$s3, $s3, 4
#$s3 = $s3 + 4
There is no subi instruction, can you guess why not?
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MIPS Instructions, so far
Category
Instr
Example
Meaning
Arithmetic
add subtract
add $s1, $s2, $s3 sub $s1, $s2, $s3
$s1 = $s2 + $s3 $s1 = $s2 - $s3
add immediate Data transfer load word store word
addi $s1, $s2, 4 lw $s1, 32($s2)
$s1 = $s2 + 4 $s1 = Memory($s2+32) Memory($s2+32) = $s1
sw $s1, 32($s2)
29

30
FIGURE 2.4 MIPS architecture revealed through section 2.3. MIPS operands
Name
32 registers
Example
$s0, $s1, , $s7 $t 0, $t 1, , $t 7
Comments
Fast locations for data. In MIPS, data must be in registers to perform arithmetic. Registers $s0 - $s7 map to 16-23 and $t0 - $t7 map to 8-15.
230
memory words
Memory[0], Memory[4], , Memory[4294967292]
Accessed only by data transfer instructions in MIPS. MIPS uses byte addresses, so sequential word addresses differ by 4.

Category
Arithmetic
Instruction
add subtract add immediate load word
Example
add $s1, $s2, $s3 sub $s1, $s2, $s3 addi $s1, $s2, 100 lw $s1, 100($s2) sw $s1, 100 ($s2)
Meaning
$s1 = $s2 + $s3 $s1 = $s2 - $s3 $s1 = $s2 + 100 $s1 = Memory [$s2 + 100] Memory [$s2 + 100] = $s1
Comments
Three operands; data in registers Three operands; data in registers Used to add constants Data from memory to register Data from register to memory
Data transfer store word
31
2.4 Representing Instructions in the Computer
32
Binary digit Also called binary bit. One of the two numbers in base 2, 0 or 1, that are the components of information. Machine language: Binary representation used for communication within a computer system. Instruction format: A form of representation of an instruction composed of fields of binary numbers.
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Machine Language
Instructions, like registers and words of data, are also 32 bits long Example: add $t1, $s1, $s2 registers have numbers, $t1=9, $s1=17, $s2=18 Instruction Format: 000000 10001 op rs 10010 rt 01001 rd 00000 shamt 100000 funct
Can you guess what the field names stand for?
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op: Opcode rs: the first register source operand. rt: the second register source operand. rd: the register destination address. shamt: Shift amount. (for shift instructions) funct: Function (function code) ( selects
the specific variant of the operation specified in the opcode field)
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Machine Language
Consider the load-word and store-word instructions, What would the regularity principle have us do? New principle: Good design demands a compromise Introduce a new type of instruction format I-type for data transfer instructions other format was R-type for register Example: lw $t0, 32($s2) 35 op 18 rs 8 rt 32 16 bit number
Where's the compromise?
36

37
FIGURE 2.7 MIPS architecture revealed through section 2.4
MIPS machine language

Name
add
sub addi lw sw Field size R-format I-format R I
Format
R
R I I I
Example
0
0 8 35 43 6 bits op op
Comments
0
0 100 100 100
18
18 18 18 18 5 bits rs rs
19
19 17 17 17 5 bits rt rt
17
17
32
34
add $s1, $s2, $s3

sub $s1, $s2, $s3 addi $s1, $s2, 100 lw $s1, 100($s2) sw $s1, 100 ($s2)
5 bits rd
5 bits shamt address
6 bits funct
ALL MIPS instructions 32 bits Arithmetic instruction format Data transfer format
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2.5
Logical Operations
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FIGURE 2.9 C and JAVA logical operators and their corresponding MIPS instructions.
Logical operations Shift left Shift right Bit-by-bit AND Bit-by-bit OR Bit-by-bit NOT
C operators << >> & | ~
JAVA operators << >>> & | ~
MIPS instructions sll srl and, andi or, ori nor
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FIGURE 2.10 MIPS architecture revealed thus far.
MIPS operands
Name
32 registers
Example
$s0, $s1, , $s7 $t 0, $t 1, , $t 7 Memory[0], Memory[4], , Memory[4294967292]
Comments
Fast locations for data. In MIPS, data must be in registers to perform arithmetic. Registers $s0 - $s7 map to 16-23 and $t0 - $t7 map to 8-15. Accessed only by data transfer instructions in MIPS. MIPS uses byte addresses, so sequential word addresses differ by 4. Memory holds data structures arrays, and spilled registers.
words
230memory
41

Category
Arithmetic
Instruction
add subtract add immediate and or nor
Example
add $s1, $s2, $s3 sub $s1, $s2, $s3 addi $s1, $s2, 100 add $s1, $s2, $s3 or nor $s1, $s2, $s3 $s1, $s2, $s3
Meaning
$s1 = $s2 + $s3 $s1 = $s2 - $s3 $s1 = $s2 + 100 $s1 = $s2 & $s3 $s1 = $s2 | $s3 $s1 = ~($s2 | $s3) $s1 = $s2 & 100 $s1 = $s2 | 100 $s1 = $s2 << 10 $s1 = $s2 >> 10 $s1 = Memory [$s2 + 100] Memory [$s2 + 100] = $s1
Comments
Three operands; Overflow detected Three operands; Overflow detected +constant; overflow detected Three reg. operands; bit-by-bit AND Three reg. operands; bit-by-bit OR Three reg. operands; bit-by-bit NOR Bit-by-bit AND reg with constant Bit-by-bit OR reg with constant Shift left by constant Shift right by constant Word from memory to register Word from register to memory
Logical
and immediate or immediate shift left logical shift right logical
andi $s1, $s2, 100 ori sll srl lw sw $s1, $s2, 100 $s1, $s2, 10 $$s1, $s2, 10 $s1, 100($s2) $s1, 100 ($s2)
Data transfer
load word store word
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2.6 Instructions for Making Decisions
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Conditional branch: An Instruction that requires the comparison of two values and that allows for a subsequent transfer of control to a new address in the program based on the outcome of the comparison. Basic block: A sequence of instructions without branches and without branch targets or branch labels. Jump address table also called jump table. A table of addresses of alternative instruction sequences.
44
Compiling if-then-else into Conditional Branches
if (i==j) f=g+h; else f=g-h; bne $s3, $s4, Else add $s0, $s1, $s2 j Exit Else: sub $s0, $s1, $s2 Exit:
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Control
Decision making instructions alter the control flow, i.e., change the "next" instruction to be executed MIPS conditional branch instructions: bne $t0, $t1, Label beq $t0, $t1, Label Example: if (i==j) h = i + j;
bne $s0, $s1, Label add $s3, $s0, $s1 Label: ....
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Assembling Branches
Instructions:
bne $s0, $s1, Lbl beq $s0, $s1, Lbl #go to Lbl if $s0$s1 #go to Lbl if $s0=$s1
Machine Formats:
op
rs
rt
16 bit number
I format
5 16 17 ???? How is the branch destination address specified? 4 16 17 ????
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Specifying Branch Destinations Could specify the memory address - but that would require a 32 bit field
Could use a base register and add to it the 16-bit offset which register?
PC bne $s0,$s1,Lbl1 add $s3,$s0,$s1 Lbl1: ...
Instruction Address Register (PC = program counter) - its use is automatically implied by branch PC gets updated (PC+4) during the Fetch cycle so that it holds the address of the next instruction
limits the branch distance to -215 to +215-1 instrs from the (instruction 2004 Morgan Kaufmann Publishers 48 after the) branch
Disassembling Branch Destinations

The contents of the updated PC (PC+4) is added to the 16 bit branch offset which is converted into a 32 bit value by concatenating two low-order zeros to make it a word address and then sign-extending those 18 bits The result is written into the PC if the branch condition is true - before the next Fetch cycle
from the low order 16 bits of the branch instruction

16
Fetch PC = PC+4 Exec Decode
sign-extend
offset
00 32 32 Add 32 Add
PC
32
32
branch dst address ?

32
32
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Offset Tradeoffs
Why not just store the word offset in the low order 16 bits? Then the two low order zeros wouldnt have to be concatenated, it would be less confusing,
That would limit the branch distance to -213 to +213-1 instrs from the (instruction after the) branch And concatenating the two zero bits costs us very little in additional hardware and has no impact on the clock cycle time
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Assembling Branches Example

Assembly code
Lbl1:
bne $s0, $s1, Lbl1 add $s3, $s0, $s1 ...
Machine Format of bne:
op
rs
rt
16 bit offset
I format
16
17
0x0001
Remember

After the bne instruction is fetched, the PC is updated so that it is addressing the add instruction (PC = PC + 4). The offset (plus 2 low-order zeros) is sign-extended and added to the (updated) PC 52
Another Instruction for Changing Flow

MIPS also has an unconditional branch instruction or jump instruction: j Example: else beq add j sub ... Lbl #go to Lbl if (i!=j) h=i+j; h=i-j; $s0, $s1, Else $s3, $s0, $s1 Exit $s3, $s0, $s1
Else: Exit:
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Assembling Jumps
Instruction: j Lbl
#go to Lbl
Machine Format:
op
26-bit address
J format
????
How is the jump destination address specified? As an absolute address formed by
concatenating 00 as the 2 low-order bits to make it a word address concatenating the upper 4 bits of the current PC (now PC+4)
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Disassembling Jump Destinations

The low order 26 bits of the jump instr converted into a 32 bit jump destination address by concatenating two low-order zeros to create an 28 bit (word) address and then concatenating the upper 4 bits of the current PC (now PC+4) to create a 32 bit (word) address that is put into the PC prior to the next Fetch cycle
from the low order 26 bits of the jump instruction

26
Fetch PC = PC+4 Exec Decode
00 32 4
PC
32
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Branching Far Away

What if the branch destination is further away than can be captured in 16 bits?
The
assembler comes to the rescue it inserts an unconditional jump to the branch target and inverts the condition
beq $s0, $s1, L1
becomes
bne j $s0, $s1, L2 L1
L2:
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Compiling a while loop in C

while (save[i]==k) i+=1; Loop : sll $t1, $s3,2 add $t1, $t1, $s6 lw $t0, 0($t1) bne $t0, $s5, Exit add $s3, $s3, 1 j Loop Exit:
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Compiling While Loops

Compile the assembly code for the C while loop where i is in $s0, j is in $s1, and k is in $s2 while (i!=k) i=i+j;
Loop: Exit:
beq $s0, $s2, Exit add $s0, $s0, $s1 j Loop . . .
Basic block A sequence of instructions without branches (except at the end) and without branch targets (except at the beginning)
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More Instructions for Making Decisions
We have beq, bne, but what about branch-if-less-than?

New instruction:
slt $t0, $s0, $s1 # # if $s0 < $s1 then # $t0 = 1 # else # $t0 = 0
Machine format: set on less than (slt)
op
rs
rt
rd
funct
R format
16
17
42 = 0x2a
60 2
Yet More Instructions for Making Decisions

Since constant operands are popular in comparisons, also have slti New instruction:
slti $t0, $s0, 10 # # if $s0 < 10 then # $t0 = 1 # else # $t0 = 0
Machine format:
op
rs
rt
16 bit number
I format
16
0x000a
61 2
Other Branch Instructions

Can use slt, beq, bne, and the fixed value of 0 in $zero to create all relative conditions less than blt $s1, $s2, Lbl less than or equal to ble $s1, $s2, Lbl greater than bgt $s1, $s2, Lbl great than or equal to bge $s1, $s2, Lbl As pseudo instructions they are recognized (and expanded) by the assembler The assembler needs a reserved register ($at) so there are policy of use conventions for registers
slt bne
$at, $s1, $s2 #$at set to 1 if $at, $zero, Lbl # $s1 < $s2
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Another unconditional jump
jr reg Jump Register

put the contents of the register in to the PC register.
The book describes using this with a jump table to build a C switch statement.
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Review: MIPS Instructions, so far

Category Instr OpCd Example Meaning
Arithmetic (R & I format)
add subtract add immediate
0 & 20 0 & 22 8 23 2b 4 5 a
add $s1, $s2, $s3 sub $s1, $s2, $s3 addi $s1, $s2, 4 lw $s1, 100($s2)
$s1 = $s2 + $s3 $s1 = $s2 - $s3 $s1 = $s2 + 4 $s1 = Memory($s2+100) Memory($s2+100) = $s1 if ($s1==$s2) go to L if ($s1 !=$s2) go to L if ($s2<100) $s1=1; else $s1=0
Data transfer (I format) Cond. branch (I format)
load word store word br on equal br on not equal set on less than immediate
sw $s1, 100($s2) beq $s1, $s2, L bne $s1, $s2, L slt $s1, $s2, 100
(R format) Uncond. jump
set on less than jump jump register
0 & 2a 2 0 & 08
slti $s1, $s2, $s3 j jr 2500 $t1
if ($s2<$s3) $s1=1; else go to 10000 go to $t1
$s1=0
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FIGURE 2.12 MIPS architecture revealed through section 2.6
MIPS operands
Name
32 registers
Example
$s0, $s1, , $s7 $t 0, $t 1, , $t 7 $zero Memory[0], Memory[4], , Memory[4294967292]
Comments
Fast locations for data. In MIPS, data must be in registers to perform arithmetic. Registers $s0 - $s7 map to 16-23 and $t0 - $t7 map to 8-15. MIPS register $zero always equals 0.
Accessed only by data transfer instructions in MIPS. MIPS uses byte addresses, so sequential word addresses differ by 4. Memory holds data structures arrays, and spilled registers.
words
230memory
66
Byte operations
In C programs we often deal with strings of characters (ASCII characters). Each character is 1 byte. We need instructions that can deal with 1 byte at a time.
68
Load Byte: lb
lb destreg, const(addrreg) Moves a single byte from memory to the rightmost 8 bits of destreg. The other 24 bits of destreg are set to 0
actually the byte is sign extended
Base/Index addressing (just like lw).
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Store Byte: sb
sb srcreg, const(addrreg)
Moves a single byte from the rightmost 8 bits of destreg to memory. Base/Index addressing (just like sw).
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32 bit constants
Sometimes we need to deal with 32 bit constants! We can now load the lower 16 bits with any constant value: addi $s0,$zero,const We need some way to put 16 bits in to the left half of a register.
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Load Upper Immediate: lui
lui destreg, const const is a 16 bit immediate value. The lower 16 bits of destreg are all set to 0! (have to load the upper half first!)
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Subroutines
# # # # main: # multiply 3 x 2 addi $a0,$zero,3 addi $a1,$zero,2 # call the subroutine jal multiply # print out the result move $s0,$v0 li $v0,4 la $a0, msg syscall li $v0,1 move $a0,$s0 syscall li $v0,10 syscall mult subroutine needs some registers so we save $t0 first 2 arguments $a0 and $a1 are multiplied using repeated addition
multiply:
sub $sp,$sp,4 sw $t0,0($sp) # make room for $t0 # put t0 on the stack
# start with $t0 = 0 add $t0,$zero,$zero mult_loop: # loop on a1 beq $a1,$zero,mult_eol # add another $a0 add $t0,$t0,$a0 # decrement $a1 sub $a1,$a1,1 j mult_loop mult_eol: # put the result in $v0 add $v0,$t0,$zero # restore $t0 lw $t0,0($sp) add $sp,$sp,4 # return to caller jr $ra
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Subroutine Issues
How to call a subroutine how to pass parameters how to get the return value How to write a subroutine where to look for parameters saving registers returning a value returning to the caller
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Special Registers
$a0-$a4: argument registers

this is where we put arguments before calling a subroutine.
$v0, $v1: return value registers

where subroutines put return values
$ra: return address register

holds the address the subroutine should jump to when its done.
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Jump and Link Instruction jal address

Puts the address of the next instruction (PC+4) in the $ra register. Jumps to the specific address. Addressing mode is just like the j instruction (26 bit absolute address).
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Returning from the Subroutine
Assuming the subroutine doesnt clobber the $ra register:

when the subroutine is done, it jumps to the address in $ra
jr $ra
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What if the subroutine uses a register?

Accepted convention: $t0, $t1, $t7 are always OK to use. if you call a subroutine and you need the value of $t0 to be the same after the call, you must save it in memory! caller saves $t0 $t7 $s0-$s7 must not be changed by a subroutine. If you need them in your subroutine you need to save the previous value and restore them before returning. callee saves $s0 $s7
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Saving registers and the Stack
Most of the time we use whatever registers we want inside subroutines.

must save and restore $s0-$s7
This happens so often there is a special register and data structure used to support saving and restoring registers.
The Stack
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The Stack
The stack is an area of memory reserved for the purpose of saving registers. The $sp register (stack pointer) holds the address of the top of the stack. The stack grows and shrinks as registers are saved and restored.
80
$sp and Memory

before/after call inside subroutine
$sp
$sp
81
Stack handling code

Suppose your subroutine needs to use 3 registers: $s0, $s1 and $s2:
first make room for saving three words by subtracting 12 from the stack pointer sub $sp,$sp,12 now put copies of the three registers on the stack. sw $s0,0($sp) sw $s1,4($sp) sw $s2,8($sp)
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Stack handling code (cont.)
Before returning, your subroutine should restore the 3 registers: lw $s2,8($sp) lw $s1,4($sp) lw $s0,0($sp)
And put the stack pointer back to its original value:
add $sp,$sp,12
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Why bother?
We write subroutines so that they can be called from any other code.
as far as the caller is concerned, $s0$s7 dont change.
The stack provides a single mechanism that will work no matter who called the subroutine.
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Exercise
Create a multiplication subroutine.

$a0 is multiplied by $a1 and the product is returned in $v0
85
Pseudoinstructions
There are many instructions you can use in MIPS assembly language that dont really exist! They are a convienence for the programmer (or compiler) just a shorthand notation for specifying some operation(s).
86
MIPS move pseudoinstruction

move destreg, sourcereg
There is no move instruction, but the assembler lets us pretend. The assembler can achieve this using add and $zero:
move $s0, $s1 is really add $s0,$s1,$zero
87
FIGURE 2.18 MIPS register conventions.
Name
$zero $v0-$v1 $a0-$a3 $t0-$t7 $s0-$s7 $t8-$t9 $gp $sp
Register number Usage

0 2-3 4-7 8-15 16-23 24-25 28 29 the constant value 0 values for results and expression evaluation arguments temporaries saved more temporaries global pointer (refer text) stack pointer
$fp
$ra
30
31
frame pointer (refer text)

return address
88
FIGURE 2.19 MIPS architecture revealed through section 2.7.
MIPS operands
Name
32 registers
Example
$s0-$s7, $t 0- $t 9, $zero, $a0-a3, $v0-$v1, $gp, $fp, $sp, $ra
Comments
Fast locations for data. In MIPS, data must be in registers to perform arithmetic. MIPS register $zero always equals 0. $gp (28) is the global pointer, $sp (29) is the stack pointer, $fp (30) is the frame pointer, and $ra (31) is the return address.
230memory words
Accessed only by data transfer instructions in MIPS. MIPS uses byte addresses, so sequential word addresses differ by 4. Memory holds data structures, arrays, and spilled registers, such as those saved on procedure calls.
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Category
Arithmetic
subtract load word Data transfer store word and or nor Logical and immediate or immediate shift left logical shift right logical sw $s1, 100 ($s2) Memory [$s2 + 100] = $s1 $s1 = $s2 & $s3 $s1 = $s2 | $s3 $s1 = ~($s2 | $s3) $s1 = $s2 & 100 $s1 = $s2 | 100 $s1 = $s2 << 10 $s1 = $s2 >> 10 Data from register to memory Three reg. operands; bit-by-bit AND Three reg. operands; bit-by-bit OR Three reg. operands; bit-by-bit NOR Bit-by-bit AND reg with constant Bit-by-bit OR reg with constant Shift left by constant Shift right by constant add $s1, $s2, $s3 or nor $s1, $s2, $s3 $s1, $s2, $s3 sub $s1, $s2, $s3 lw $s1, 100($s2) $s1 = $s2 - $s3 $s1 = Memory [$s2 + 100] Three operands; Overflow detected Data from memory to register
Instruction
add
Example
add $s1, $s2, $s3
Meaning
$s1 = $s2 + $s3
Comments
Three operands; Overflow detected
andi $s1, $s2, 100 ori sll srl $s1, $s2, 100 $s1, $s2, 10 $$s1, $s2, 10
branch on equal branch on not equal Condition al branch set on less than set on less than immediate jump Unconditi onal jump jump register jump and link
beq $s1, $s2, L bne $s1, $s2, L slt slt j jr jal $s1, $s2, $s3 $s1, $s2, 100 L $ra L
if ($s1 == $s2) go to L if ($s1 != $s2) go to L if ($s2 < $s3) $s1 = 1; else $s1 = 0 if ($s2 < 100) $s1 = 1; else $s1 = 0 go to L go to $ra $ra = PC + 4; go to L
Equal test and branch Not equal test and branch Compare less than; used with beq, bne Compare less than immediate; used with beq, bne Jump to target address For procedure return For procedure callKaufmann Publishers 2004 Morgan
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MIPS Addressing Mode Summary
1. Register addressing, 2. Base or displacement addressing, 3. Immediate addressing, 4. PC-relative addressing, 5. Pseudodirect addressing,
91
FIGURE 2.24 Illustration of the five MIPS addressing modes.

1. Immediate addressing op rs rt Immediate
2. Register addressing op rs rt rd ... funct Registers Register
3. Base addressing op rs rt Address Memory
Register
Byte
Halfword
Word
4. PC-relative addressing op rs rt Address Memory
PC
Word
5. Pseudodirect addressing op Address Memory
PC
Word
92
FIGURE 2.26 MIPS instruction formats in Chapter 2.
Name Field size R-format I-format J-format op op op rs rs rt rt
Fields 6 bits 5 bits 5 bits 5 bits rd 5 bits shamt 6 bits funct
Comments ALL MIPS instructions 32 bits Arithmetic instruction format Transfer, brance, imm. format jump instruction format
address/immediate target address
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FIGURE 2.27 MIPS assembly language revealed in Chapter 2.
MIPS operands
Name
32 registers
Example
$s0-$s7, $t 0- $t 9, $zero, $a0-a3, $v0-$v1, $gp, $fp, $sp, $ra, $at
Comments
Fast locations for data. In MIPS, data must be in registers to perform arithmetic. MIPS register $zero always equals 0. Register $at is reserved for the assembler to handle large constants.
memory words
Accessed only by data transfer instructions in MIPS. MIPS uses byte addresses, so sequential word addresses differ by 4. Memory holds data structures, arrays, and spilled registers, such as those saved on procedure calls.
94

Category
Instruction
add subtract add immediate load word
Example
add $s1, $s2, $s3 sub $s1, $s2, $s3 addi $s1, $s2, 100 lw $s1, 100($s2)
Meaning
$s1 = $s2 + $s3 $s1 = $s2 - $s3 $s1 = $s2+ 100 $s1 = Memory [$s2 + 100]
Comments
Three operands; Overflow detected Three operands; Overflow detected Used to add constants Word from memory to register
Arithmetic
store word
load half Data transfer store half load byte store byte load upper immed. and
sw
lh sh lb sb lui
$s1, 100 ($s2)

$s1, 100($s2) $s1, 100 ($s2) $s1, 100($s2) $s1, 100 ($s2) $s1, 100
Memory [$s2 + 100] = $s1

$s1 = Memory [$s2 + 100] Memory [$s2 + 100] = $s1 $s1 = Memory [$s2 + 100] Memory [$s2 + 100] = $s1 $s1 = 100 * 2^16 $s1 = $s2 & $s3
Word from register to memory

Halfword memory to register Halfword register to memory Byte from memory to register Byte from register to memory Loads constant in upper 16 bits Three reg. operands; bit-by-bit AND
add $s1, $s2, $s3
or
nor Logical and immediate or immediate shift left logical shift right logical
or
nor
$s1, $s2, $s3

$s1, $s2, $s3
$s1 = $s2 | $s3

$s1 = ~($s2 | $s3) $s1 = $s2 & 100 $s1 = $s2 | 100 $s1 = $s2 << 10 $s1 = $s2 >> 10
Three reg. operands; bit-by-bit OR

Three reg. operands; bit-by-bit NOR Bit-by-bit AND reg with constant Bit-by-bit OR reg with constant Shift left by constant Shift right by constant
andi $s1, $s2, 100 ori sll srl $s1, $s2, 100 $s1, $s2, 10 $$s1, $s2, 10
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Continue..
branch on equal
beq $s1, $s2, 25
if ($s1 == $s2) go to PC+4+100
Equal test; PC-relative branch
Condition al branch
branch on not equal

set on less than set on less than immediate jump
bne $s1, $s2, 25

slt slt j jr jal $s1, $s2, $s3 $s1, $s2, 100 2500 $ra 2500
if ($s1 != $s2) go to L PC+4+100

if ($s2 < $s3) $s1 = 1; else $s1 = 0 if ($s2 < 100) $s1 = 1; else $s1 = 0 go to 10000 go to $ra $ra = PC + 4; go to 10000
Not equal test; PC-relative

Compare less than; for beq, bne Compare less than constant Jump to target address For procedure return For procedure call
Unconditi onal jump
jump register jump and link
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Translating and Starting a Program
97
Pseudoinstruction: A common variation of assembly language instructions often treated as if it were an instruction in its own right. Symbol table: A table that matches names of labels to the addresses of the memory words that instructions occupy. Linker Also called link editor: A systems program that combines independtly assembled machine language programs and resolves all undefined labels into an executable file. Executable file: A functional program in the format of an object file that contains no unresolved references, relocation information, symbol table, or debugging information. Loader: A systems program that places an object program in main memory so that it is ready to execute.
98
FIGURE 2.28 A translation hierarchy for C.
99

MIPS

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Instruction Set Design - Goals

2004 Morgan Kaufmann Publishers

RISC - Reduced Instruction Set Computer

2004 Morgan Kaufmann Publishers

Instruction Set Architecture (MIPS: Microprocessors without Interlocked Pipeline Stages)

Four design principles guide

2004 Morgan Kaufmann Publishers

Instruction set: The vocabulary of commands understood by a given architecture.

2004 Morgan Kaufmann Publishers

2.2 Operations of the Computer Hardware

2004 Morgan Kaufmann Publishers

2004 Morgan Kaufmann Publishers

Four design principles guide

2004 Morgan Kaufmann Publishers

FIGURE 2.1 MIPS architecture revealed in section 2.2.

MIPS assembly language

Always three operands

Always three operands

2004 Morgan Kaufmann Publishers

f = (g+h) - (i+j); add t0, g, h add t1, i, j sub f, t0, t1

2004 Morgan Kaufmann Publishers

2004 Morgan Kaufmann Publishers

f = (g+h) - (i+j); $s0, $s1, $s2, $s3, $s4

$t0, $s1, $s2

2004 Morgan Kaufmann Publishers

2.3 Operands of the Computer Hardware

2004 Morgan Kaufmann Publishers

2004 Morgan Kaufmann Publishers

Registers vs. Memory

Control Memory Datapath

2004 Morgan Kaufmann Publishers

Four design principles guide

2004 Morgan Kaufmann Publishers

2004 Morgan Kaufmann Publishers

2004 Morgan Kaufmann Publishers

FIGURE 2.2 Memory addresses and contents of memory at those locations.

2004 Morgan Kaufmann Publishers

2004 Morgan Kaufmann Publishers

Compiling with Loads and Stores

... A[3] A[2] A[1] A[0]

... $s3+12 $s3+8 $s3+4 $s3

$t0, $t0, $s2

2004 Morgan Kaufmann Publishers

g = h + A[8] lw $t0, 8($s3) add $s1, $s2, $t0

2004 Morgan Kaufmann Publishers

2004 Morgan Kaufmann Publishers

Dealing with Constants

How do we make this work?

How do we Make the common case fast !

Constant (or Immediate) Operands

There is no subi instruction, can you guess why not?

2004 Morgan Kaufmann Publishers

MIPS Instructions, so far

add $s1, $s2, $s3 sub $s1, $s2, $s3

$s1 = $s2 + $s3 $s1 = $s2 - $s3

add immediate Data transfer load word store word

addi $s1, $s2, 4 lw $s1, 32($s2)

$s1 = $s2 + 4 $s1 = Memory($s2+32) Memory($s2+32) = $s1

2004 Morgan Kaufmann Publishers

Four design principles guide

2004 Morgan Kaufmann Publishers

Memory[0], Memory[4], , Memory[4294967292]

MIPS assembly language