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Department of Electronics and Communication: INTEL 8085 Microprocessor
Department of Electronics and Communication: INTEL 8085 Microprocessor
OBJECTIVE
INTRODUCTION ARCHITECTURE
PIN DIAGRAM
INSTRUCTION ADDRESSING MODES APPLICATIONS
TECHNIQUES TO FABRICATE IC s
After the invention of transistors, the integrated circuits appeared in the year of 1950. an entire electronic ckt consist of several transistors, diodes & resisters could be designed on a single chip.
In early 1960, logic gates were commonly available as ICs & the technology of integrating the ckts of a logic gate on a single chip was known as Small Scale Integration (SSI). As semi-conductor technology advanced, more than 100 gates were fabricated on the chip & this was called Medium Scale Integration (MSI). Within a few years it was possible to fabricate more than 1000 gates on a single chip & this was known as Large Scale Integration (LSI). Now a days a Very Large Scale Integration (VLSI) & Super Large Scale Integration (SLSI),
8085 ARCHITECTURE ..
Intel
ACCUMULATOR
TEMPORARY REGISTER
FLAG
ALU
Adar
)
ALU - Arithmetic & logic unit can perform the arithmetic & logical operations. It is a collection of sequential & combinational ckts like adders, comparators, multipliers etc. it can perform arithmetic operations like addition, subtraction & logical operations like AND, OR , EX-OR, compliment operations. The result of these operations is stored in the accumulator. It also provides status of result to the flag register. ACCUMULATOR It is a part of arithmetic & logic section. It is used to store 8 bit data to perform arithmetic & logical operations. The result of arithmetic & logical operations are stored in the accumulator. The accumulator is identified as register A. TEMPORARY REGISTER Temporary register is used by the microprocessor for its internal operations. It is used to hold data or immediate result during an arithmetic & logical operations . It is also a part of the arithmetic & logic section. FLAG REGISTER The flag register is the status of the microprocessor which reflects the result of arithmetic & logic operations. It is a part of arithmetic & logic section. It is a 8 bit register.
FLAG REGISTER
AC
CY
Zero flag
Sign flag
REGISTERS
W & Z are temporary Registers, used for temporary storage
H(8-bit)
STACK POINTER (16-bit)
L (8-bit)
Program counter & stack pointer are special purpose register & are of 16 bits.
8 0 8
Vcc HOLD HLDA CLK OUT RESET I N READY IO/M S1 RD WR ALE S0 A15 A14 A13 A12 A11 A10 A9 A8
PIN DISCRIPTION
HIGH ORDER ADDRESS BUS The 8085 has 8 signal lines A15 A8 which are used as high order address bus. These lines are unidirectional lines. MULTIPLEXED ADDRSS/DATA BUS- The 8 signal lines AD7 AD0 are identified as address/data bus. These are bidirectional lines i.e. data flow from microprocessor to peripherals & vice versa. CONTROL & STATUS SIGNALS There are 2 control signals (RD & WR), 3 status signals (S1,S2,IO/M) & ALE. ALE This is a ADDRESS LATCH ENABLE signal. This signal is used to latch the low order address lines from multiplexed address/data lines & generate a separate set of 8 lines A7 A0. RD It is an active low signal. When this signal is low the selected input output or memory location is to be read . WR It is an active low signal. When this signal is low , the data is to be written on selected memory location or input output device. IO/M This is a status signal used to differentiate between input/output & memory operation. When this signal is low it indicates memory operation, when this signal is high it indicates i/o operation. S0 &S1 These are status signals similar to IO/M . These signals can identify various operations -
IO/M
RD
WR
OPERATION
0
0 1 1
0
1 0 1
1
0 1 0
Memory Read
Memory Write I/O Read I/O Write
S1 0 0 1
S0 0 1 0
Opcode fetch
PIN DISCRIPTION
SERIAL I/O PORTS
Serial Input Data (SID) It is a serial input data line. It is connected to the serial
I/O device. The data on this line is loaded into the most significant bit of the accumulator i.e. D7 bit when RIM instruction is executed. Serial Output Data It is a serial output data line. It is connected to the serial
I/O device. The most significant bit i.e. D7 of the accumulator is transfered on
this line after executing SIM instruction. INTERRUPTS There are 5 hardware interrupts INTERRUPTS PRIORITY
1. TRAP
2. RST 7.5 3. RST 6.5 4. RST 5.5
Highest
5. INTR
Lowest
PIN DISCRIPTION
READY It is used by processor to sense whether a peripheral device is ready
to transfer data or not. If this signal is HIGH , the peripheral is ready. If this
signal is low, the microprocessor enters into the wait state till this signal goes HIGH. HOLD & HOLD ACKNOWLEDGEMENT SIGNAL
PIN DISCRIPTION
RESET IN & RESET OUT SIGNALS
internally divided by two. There fore to operate a system at 3.07 MHz , the
crystal used should have a frequency of 6.14 MHz . CLOCK OUT : It is a clock out signal. This signal can be used as the system clock for the other devices .
eg opcode operand comment MVI A,01 move immediate 01 in register A. 2. REGISTER ADDRESSING MODE - In this mode, the instruction specifies the general purpose register in which the data is located i.e. data to be loaded is stored in register rather than in memory. It results in faster execution. eg opcode MOV ADD operand A,B B comment Move the contents of register B to register A. Add the contents of register B to the contents of accumulator.
ADDRESSING MODES
3. DIRECT ADDRESSING MODE In this mode, the address (where the data is found) is specified directly. eg - opcode STA IN operand 2400H 02 comment store the contents of accumulator to memory location 2400. read data from input port whose address is 02.
4. INDIRECT ADDRESSING MODE - In this mode, the memory address is specified by the contents of register pair. In this the length of the instruction is of one byte. eg - opcode MOV operand A,M comment Move the contents of memory location whose address is in HL pair to accumulator.
5. IMPLIED ADDRESSING MODE There are certain instructions which operated on the contents of accumulator. eg - opcode CMA operand NONE comment The contents of accumulator are complimented.