Architecture Body

The internal details of an entity are

specified by an architecture body using
any of the following modeling styles:
As a set of interconnected components
(to represent structure). Structural style
2. As a set of concurrent assignment
statements (to represent dataflow).
Dataflow style
3. As a set of sequential assignment
statements (to represent behavior).
Behavioral style
4. Any combination of the above three.
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Structural Style of Modeling
Structural architecture
– implements the module as a
composition of subsystems contaning :
• signal declarations, for internal
interconnections
– the entity ports are also treated as
signals
• component instances
– instances of previously declared
entity/architecture pairs
• port maps in component instances
– connect signals to component ports
• wait statementsRavindra Bhat 2
In the structural style of modeling, an
entity is described as a set of
interconnected components.
One can create smaller components and
immediately use them in a bigger
component in a single source file.
It is also called as component statement.
Component name is name of previously
defined entity which is to be used within
the architecture body.
The architecture body is composed of two
parts:
i) The declarativeRavindra
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(before the 3
All the components that you propose to
use in the design have to be declared in
the architecture declaration zone, i.e.
between the architecture and the begin
keywords.
Component declarations are present in the
declarative part of the architecture body.
These declarations specify the interface of
components that are used in the
architecture body.
The component name need not be
identical to the entity name in the library.
Syntax of component declaration is as
follows:
Component <entity name> port (<port
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In the architecture body, i.e. after “begin”,
the components are instantiated. . The
instantiation defines the component id-
number and its port map.
The id-number gives a unique
identification to the instance.
The declared components are instantiated
in the statement part of the architecture
body using component instantiation
statements.
The port map defines the connection
between the component port signals and
the external signals i.e. it describes how
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the component is wired to other entities.
The component instantiation statement
may be thought of as a concurrent
procedure call.
The procedure gets invoked whenever an
event occurs on one or more of the input
signals of the component.
The association between external signals
to internal signals of the component can
be done either by a positional
association statement or by a named
association statement.

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 Syntax of positional association
In a positional association, the outer circuit
signals are associated to the component
port signals serially.
CompId : EntityName port map(Sig1, Sig2,
….);
Where Sig1, Sig2 etc are the names of the
outer signals (schematic signals) that are
connected to the port pins of the entity.
For example, consider that the 4 input XOR
gate declared is being used to generate
even parity for a 4-bit vector “a”. IC1:
XOR3 port map (a(0), a(1), a(2), a(3),
ParityOut);
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 Syntax of named association:
In a named association, you have to
specify the association between internal
and external signals explicitly. The order is
immaterial.
The syntax is:
CompId : EntityName port
map(PortSig1=>Sig1, PortSig2=>Sig2,
….);
The XOR3 component as example can be
instantiated using named association as
follows:
IC1: XOR3 port map (O=>ParityOut,
i0=>a(0), i3=>a(3), i2=>a(2), i1=>a(1)); 8
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Such a model for the HALF_ADDER entity

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The name of the architecture body is
HA_STRUCTURE. The entity declaration for
HALF_ADDER specifies the interface ports for
this architecture body.
The components XOR2 and AND2 may either be
predefined components in a library, or if they
do not exist, they may later be bound to other
components in a library.
X1 and A1 are the component labels for these
component instantiations.
The first component instantiation statement,
labeled X1, shows that signals A and B (the
input ports of the HALF_ADDER), are connected
to the X and Y input ports of a XOR2
component, while output
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port Z of this 10
Similarly, in the second component
instantiation statement, signals A and B
are connected to ports L and M of the
AND2 component, while port N is
connected to the CARRY port of the
HALF_ADDER.
The structural representation for the
HALF_ADDER does not say anything about
its functionality.
Separate entity models would be
described for the components XOR2 and
AND2, each having its own entity
declaration and architecture
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11
Example

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Ravindra Bhat 13
Dataflow Style of Modeling
In this modeling style, the flow of data
through the entity is expressed primarily
using concurrent signal assignment
statements.
This description consists of concurrent
assignment statements that specify the flow
of data through various gates, registers or
buses in the system.
We have discussed realization of simple gates
using unconditional signal assignments
More complex logic blocks can be described
using conditional and selected signal
assignments.
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Synchronous Sequential circuits can be
A conditional assignment selects one of the
several values based on the conditions
specified. The syntax of a concurrent
conditional statement is as follows.
Signal name<=Expression1 when condition1
else
Expression2 when condition2
else
Expression_N when condition_N
else
Expression_N+1;
During the execution of the statement, the
conditions are evaluated
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In a signal assignment statement, the
symbol “<=” implies an assignment of a
value to a signal. The value of the
expression on the right-hand-side of the
statement is computed and is assigned to
the signal on the left-hand-side, called the
target signal.
A concurrent signal assignment statement
is executed only when any signal used in
the expression on the right-hand-side has
an event on it, that is, the value for the
signal changes.
The concurrent selected signal assignment
statement is similar to the CASE statement16
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The choices are not evaluated in a
sequence like the conditional statement.
All possible values of the selecting object
must be specified and they must be
mutually exclusive.
Any choice which is not explicitly specified
may be covered by the “others” clause.
Syntax:
With control_object select
Target_object <= expression1 when
value1,
Expression2 when
value2,
expressionN when
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Examples

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Ravindra Bhat 19
Behavioral Style of Modeling
The behavioral style of modeling specifies
the behavior of an entity as a set of
statements that are executed sequentially
in the specified order.
In behavioral modeling, sequential blocks
like process, procedures and functions are
heavily used.
This set of sequential statements, that are
specified inside a process statement, do
not explicitly specify the structure of the
entity but merely specifies its
functionality.
A process statement is a concurrent
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A process statement, too, has a
declarative part (between the keywords
process and begin), and a statement part
(between the keywords begin and end
process).
The statements appearing within the
statement part are sequential statements
and are executed sequentially.
The list of signals specified within the
parenthesis after the keyword process
constitutes a sensitivity list and the
process statement is invoked whenever
there is an event on any signal in this list.
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The variable declaration (starts with the
keyword variable) declares variables.
A variable is different from a signal in that
it is always assigned a value
instantaneously and the assignment
operator used is the “ := ” compound
symbol.
A signal is assigned a value always after a
certain delay (user-specified or the default
delta delay), and the assignment operator
used to assign a value to a signal is the “
<= ” compound symbol.
Also, variables canRavindra
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be declared within22
 Signal assignment statements appearing
within a process are called sequential
signal assignment statements.
Sequential signal assignment statements,
including variable assignment statements,
are executed sequentially independent of
whether an event occurs on any signals in
its right-hand-side expression or not.
It is possible to use case or loop
statements within a process.
The syntax of a “case” statement is as
follows.
case EXPRESSION is Ravindra Bhat 23
Example

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The loop statement is used to repeatedly
execute a set of sequential statements. It
has 3 variations as shown below.
--Syntax 1 (Simple loop):
[LABEL]: loop
Statement(s);
End loop [LABEL];
This is an endless loop and therefore, the
statement body must have an appropriate
“next”, “exit” or “return” statement
somewhere to make it meaningful.

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--Syntax 2 (While loop):
[LABEL]: while CONDITION loop
Statement(s);
End loop [LABEL];
The statement body is repeatedly
executed as long as the CONDITION is
true. However, an additional exit path may
be provided through an “exit” statement.
--Syntax 3 (For loop):
[LABEL]: for LOOP_VAR_NAME in RANGE
loop
Statement(s);
End loop [LABEL];
the loop variable takes all values specified
in the range and the
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An explicit wait statement can also be
used to suspend a process. It can be used
to wait for a certain amount of time or to
wait until a certain condition becomes
true, or to wait until an event occurs on
one or more signals.

This process does not have a sensitivity

list since explicit wait statements are
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RTL description
In Register Transfer Level (RTL)
description, the transformation of input
into output is described as a timed
sequence of processing steps according to
an algorithm.
Since the algorithm executes over a
number of time steps, intermediate results
of one step have to be stored in some
registers so that they can be used in the
next step.
The output of the processing elements can
be routed back to any desired register.
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Test Bench
For testing complex entities, we need long
test sequences, which should be
generated by a program. Sometimes we
need to generate handshake responses. In
such cases we use VHDL itself for
generating stimulus and capturing the
response. Such an arrangement is called a
TEST BENCH.

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The test bench is written as an overall
entity in which, the DUT (Device Under
Test) is described as a “component”. The
stimulus is generated by one process and
the response is captured by another
process.
In simple cases, we can do away with the
response capture process and observe the
waveform straightaway in the simulator.
In synchronous designs, we are mostly
interested in the status of various signals
at the rising edge of the clock. In such
case, the responseRavindra
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process can be30
Mixed Style of Modeling
It is possible to mix the three modeling
styles that we have seen so far in a single
architecture body. That is, within an
architecture body, we could use
component instantiation statements (that
represent structure), concurrent signal
assignment statements (that represent
dataflow), and process statements (that
represent behavior).
For example full-adder is represented
using one component instantiation
statement, one process statement and one
concurrent signal Ravindra
assignment
Bhat statement. 31
 Structural

Behavioral

Dataflow

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All of these statements are concurrent
statements, and therefore, their order of
appearance within the architecture body is
not important. Note that a process
statement itself is a concurrent statement;
however, statements within a process
statement are always executed
sequentially.
S1 is a signal locally declared within the
architecture body and is used to pass the
value from the output of the component
X1 to the expression for signal SUM.

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A 1-bit full-adder

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