UART IMPLEMENTATION ON FPGA

By Smarak Acharya Krishnabir Ghosh Nishanth K Vinuth M

1MV07EC100 1MV07EC121 1MV07EC061 1MV07EC113

Introduction
What is Serial Communication?

Why Serial Communication over Parallel Communication ?

Serial Communication Techniques

Asynchronous Communication

Synchronous Communication

Synchronous Vs Asynchronous
o When a system is receiving bits on a line, how does it know when does a bit end and the other start.
0 00 0 1 1 1 1 0 000 1 1

o Advantages and Disadvantages

UART
A Universal Asynchronous Receiver/Transmitter (UART) is a type of asynchronous receiver/ transmitter , a piece of computer hardware that translate data between parallel and serial form.

Features of UART
Serial Transmission in full duplex mode. Used in conjunction with communication standards such as EIA RS232, RS422 or RS 485. Transmits data in frames. Data format and transmission speeds are configurable. Used to connect two devices with different clock speeds such as a PC and an I/O device.

UART : Working
Receiver : Serial data to Parallel data Transmitter : Parallel data to Serial data
Parallel Data
Serial Channel Transmitter Receiver

Parallel Data

Transmit Buffer

Receive Buffer

UART Frame

Start Bit Parity bit Stop Bit Data Bits Overrun Error Parity Error Framing Error

Always 0 As per parity selected Always 1 5-8

Frame Based

RS232
RS-232 (Recommended Standard 232) Standards: bit 1 represented by -3~-25V bit 0 represented by +3~+25V MAX232 converts the TTL logic levels (+5V and 5V) to the RS232 voltage levels and vice versa

UART: Hardware Implementation

Functional Diagram

Transmitter Operation

Transmitter Flow

Receiver Operation

Receiver Flow

Start Bit Detection

Xilinx Spartan 3

Design Implementation:
translate map place and route

Device Programming:
create a bit file to program fpga generate jtag file to download to the device use iMPACT to program the device

UART: Simulation

Functional Diagram

Operation
Similar to standard UART Additional signaling operations:
Handshaking signals:
Transmitter: TXRDY, XRDYT Receiver: XRDYR, RXRDY

Interrupt:
Transmitter: RETRAN Receiver: NACK

Transmitter Flow

Normal Transmitter Flow

Retransmit Flow

Receiver Flow

Normal Receiver Flow

Receiver Flow in case of Error

Simulation Diagrams

Receiver: 16 bit data with Two Stop bits and Parity Inhibited (No Errors)

Receiver: 16 bit data with Two stop bits (Parity Error)

Transmitter: 16 bit data Two Stop Bits and Parity Inhibited (No Errors)

APPLICATIONS
Serial Communication. Software Loading. Software Debugging. Connection from PC to Peripheral Devices such as printers. Device Testing.

CONCLUSION