PhD Progress Report 6th Monthly (July-Dec.

2012) Presentation on

VLSI IMPLEMENTATION OF CONVOLUTION AND DSP ALGORITHM USING VEDIC MATHEMATICS

Guided By:
Dr. R. S. Meena Associate Professor Electronics Engineering Department

Presented By:
Rajesh Bathija Research Scholar, Electronics Engineering Department

University College of Engineering, Rajasthan Technical University, Kota (Raj.)

Content
What is Vedic Mathematics and Why it is so popular? What is Aim of this Thesis work? What is the work done up-to now? Discussion of work submitted to International Journal of Computer Application (IJCA), New York Future planning
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Vedic Mathematics

Sthapatya

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Awarded the title "" by the Madras Sanskrit Association in July, 1899 at the age of 16.

In

at Nagpur, 1953,

The Chief Justice of India, Justice B.P. Sinha served as its President. Dr. C. D. Deshmukh, the ex-Finance Minister of India and ex-Chairman of the University Grants Commission served as its VicePresident. Shri Arvind N. Mafatlala , in 1965 a Chair of Vedic Studies at BHU,
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(March, 1884 February, 1960) was the Sankaracharya of the Govardhan Peeth, Puri Jaganath during 19251960. He is particularly known for his book Vedic Mathematics.

 Vedic mathematics covers Arithmetic,

Geometry (plane, co-ordinate), Trigonometry, Quadratic Equations, Factorization and Calculus.

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16 Sutras & 13 Sub-Sutras

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Journal Publication

(0975 8887) Volume 59 No.6, December 2012 Impact Factor: 0.814

Co-Authors
a) Dr. R.S. Meena, (Asso. Professor- ECE) UCE, RTU, KOTA b) Dr. S. Sarkar (Ex-Prof. IIT Roorkee) Visiting Professor-Jadhavpur University, Kolkata c) Mr. Rajesh Sahu, (Asst. Prof.) TINJRIT, Udaipur
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 Urdhva-tiryagbhyam Sutra of Vedic Mathematics Chosen 2014 Technology Node is Chosen which may be 16nm. 16nm Technology file taken from PTM website. CMOS topology of VLSI is chosen Comparison done with Booth Multiplier and Dr. K.S. Gurumurthy, M.S Prahalad Fast and Power Efficient 1616 Array of Array Multiplier using Vedic Multiplication Paper (1) Design
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P0= (A0 and B0) P1= (A0 and B1) xor (B0 and A1) P2= (A1and B1) and (A0 and B0) P3= (A1and B1)

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Urdhva-tiryagbhyam

This the general formula applicable to all cases of

multiplication.
2x2 Multiplier Process 3x3 Multiplier Process

46 X43 1978
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103 X 105 1 0, 8 1 5

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 Power dissipation 23.2 W Propagation delay 1.51 nsec.

62 transistors
2-Bit multiplier using Urdhva Tiryakbhyam Sutra & its symbol
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Input Output waveforms of 2x2 Bit Vedic multiplier

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4-Bit multiplier using Urdhva Tiryakbhyam Sutra & its symbol

Power dissipation 0.18 mW Propagation delay 1.71 nsec. 618 transistors

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Power dissipation 0.035mW Propagation delay 1.72 nsec MOS Transistors 3222

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 No of transistors can be minimized for example 4 transistor topology of XOR Gate can be utilized to build the other cell like Half Adder, CLA and so on Also in place of CMOS topology, Domino logic topology can be utilized.

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Month

Work to be Accomplished

Jan 2013
Fab 2013 March 2013 April 2013

Improved 16x16 bit multiplier with FPGA implementation Linear convolution using 16x16 bit multiplier
Circular convolution using 16x16 bit multiplier Implementation of FFT using circular convolution

May 2013
June 2013

Implementation of FFT using circular convolution

Linear convolution using FFT

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Prakash Narchi, Siddalingesh S Kerur, Jayashree C Nidagundi, Harish M Kittur and Girish V A. Implementation of Vedic Multiplier for Digital Signal Processing. IJCA Proceedings on International Conference on VLSI, Communications and Instrumentation (ICVCI) (16):15, 2011. Published by Foundation of Computer Science Sumit Vaidya and Deepak Dandekar. Delay-power perfor-mance comparison of multipliers in VLSI circuit design. International Journal of Computer Networks & Communications (IJCNC), Vol.2, No.4, July 2010. Dr. K.S. Gurumurthy, M.S Prahalad Fast and Power Efficient 1616 Array of Array Multiplier using Vedic Multiplication, M. Ramalatha, K. Deena Dayalan, P. Dharani, S. Deborah Priya, High Speed Energy Efficient ALU Design using Vedic Multiplication Techniques , ACTEA 2009 Abhijit Asati and Chandrashekhar A High-Speed, Hier-archical 1616 Array of Array Multiplier Design, IMPACT 2009. Kevin Biswas, "Multiplexer Based Array Multipliers," A Ph.D. Dissertation, University of Windsor, Electrical and Computer Engineering, Apr. 2005. Himanshu Thapliyal and Hamid R. Arabnia, "A time area power efficient multiplier and square architecture based on ancient Indian Vedic mathematics, www.vedicmathsindia.org. Vishal Verma and Himanshu Thapliyal , High Speed Efficient N X N Bit Multiplier Based On Ancient Indian Vedic Mathematics, Proceedings International Conference On VLSI, Las Vegas, June 2003

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