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Computer Organization - Flip Flops
Computer Organization - Flip Flops
Objectives:
1 Define sequential logic circuit.
4 Identify various types of flip-flops. 5 Build SR, JK, T and D flip flop using logic gates. 6 Draw the symbol and truth table of SR, JK, T and D flip
flop.
Difference between
Sequential
logic circuit
S C
Q'
Combinational
logic circuit
Combinational logic is an interconnection of
logic gates to generate a specificities logic function where the inputs result in an immediate output, having no memory or storage capabilities.
Flip-Flop
3 Describe flip - flop.
Flip-Flop
"Flip-flop" is the common name given to two-state
devices which offer basic memory for sequential logic operations.
Flip-Flop
Flip-flop are basic storage/memory elements. Flip-flop are essentially 1-bit storage devices. Types of flip-flops are:
1. SR Flip-flop 2. JK Flip-flop 3. D Flip-flop 4. T Flip-flop Application of flip-flop: 1. Counter 4. Logic controller 2. Register 5. Frequency Divider 3. Memory
SR Flip-Flop
4 Identify various types of flip-flops. 5 Build SR, JK, T and D flip flop using logic gates. 6 Draw the symbol and truth table of SR, JK, T and D flip flop.
SR Flip-Flop
Q'
The simplest binary storage device. SR Flip-flop have 2 inputs (SET & RESET) and 2
outputs (Q & Q).
NOTE: Q & Q are compliments of each other
SR Flip-Flop Symbol:
NOR gate
Symbol
SR Flip-Flop Symbol:
NAND gate
Symbol
Q Q'
(Active HIGH)
S' 1 0 1 0
R' 1 1 0 0
Q NC 1 0 1
Q' NC 0 1 1 No change. Latch remained in present state. Latch SET. Latch RESET. Invalid condition.
S R
SR Flip-flop
Q Q'
(Active LOW)
IQ Test!
What is the mode of operation of the SR flip-flop (set, reset or hold)? What is the output at Q from the SR flip-flop (active LOW inputs)?
L H
High ?
Mode of operation = Set ?
H H
? High
Mode of operation = Hold ?
H L
? Low
Mode of operation = ? Reset
SR Flip-Flop
4 Identify various types of flip-flops. 5 Build SR, JK, T and D flip flop using logic gates. 6 Draw the symbol and truth table of SR, JK, T and D flip flop.
Clock
Clock
Flip-flops: synchronous bistable devices Output changes state at a specified point on a
triggering input called the clock.
SR Flip-Flop
The Clocked SR Flip Flop like SR flip-flop but with
extra third input of a standard clock pulse.
Clock
Combination gate
Symbol
Q'
CLK*
CLK
CLK' CLK*
CLK
CLK' CLK*
Positive-going transition
Negative-going transition
(rising edge)
(falling edge)
D Flip-Flop
4 Identify various types of flip-flops. 5 Build SR, JK, T and D flip flop using logic gates. 6 Draw the symbol and truth table of SR, JK, T and D flip flop.
D C
Q'
D flip-flop: single input D (data) D=HIGH a SET state D=LOW a RESET state Q follows D at the clock edge. D flip-flop formed by add NOT gate between SR input.
S C Q
D 1 0 CLK Q(t+1) 1 0 Comments Set Reset
Q'
D Flip-Flop Symbol:
D CLK Q'
Combination gate
Symbol
CLK
CLK
JK Flip-Flop
4 Identify various types of flip-flops. 5 Build SR, JK, T and D flip flop using logic gates. 6 Draw the symbol and truth table of SR, JK, T and D flip flop.
JK Flip-Flop
steering NAND gates.
J C K
Q
Q'
J-K flip-flop: Q and Q' are feedback to the pulse No invalid state. Include a toggle state.
J=HIGH (and K=LOW) a SET state K=HIGH (and J=LOW) a RESET state
JK Flip-Flop Symbol:
J Q CLK Q' K
Combination gate
Symbol
Q 0 0 0 0 1 1 1 1
J K 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1
Q(t+1) 0 0 1 1 1 0 1 0
T Flip-Flop
4 Identify various types of flip-flops. 5 Build SR, JK, T and D flip flop using logic gates. 6 Draw the symbol and truth table of SR, JK, T and D flip flop.
T
CLK
J C K
Q Q'
Q T
Q
Q(t+1) 0 1 1 0
0 0 1 1
0 1 0 1
T 0 1
CLK
T Flip-Flop Symbol:
T CLK Q'
Combination gate
Symbol
T Flip-Flop
QA
QB