ECE 301 Digital Electronics

Sequential Logic Circuits: FSM Design

(Lecture #18)

FSM Design: Procedure

Understand specifications Derive state diagram Create state table

Perform state minimization (if necessary)

Encode states (state assignment) Create state-assigned table Select type of Flip-Flop to use Determine Flip-Flop input equations and FSM output equation(s) Draw logic diagram
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FSM Design

Moore Machines

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FSM Design (Moore)

Example:
Design a FSM that detects a sequence of three or more consecutive ones on an input bit stream. The FSM should output a 1 when the sequence is detected, and a 0 otherwise.
A circuit that detects the occurrence of a particular pattern on its input is referred to as a sequence detector.

ECE 301 - Digital Electronics

FSM Design: Example (Moore)

Input:

011101011011101

Output:

000100000000100

ECE 301 - Digital Electronics

FSM Design: Example (Moore)

State Diagram

ECE 301 - Digital Electronics

FSM Design: Example (Moore)

QA

QB

QA+

QB+

State Table
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FSM Design: Example (Moore)

The choice of Flip-Flop determines the complexity of the combinational logic required in the design of the state machine.

Each type of Flip-Flop has a unique characteristic equation.

SR Flip-Flop

JK Flip-Flop

Q+ = S + R'.Q

Q+ = J.Q' + K'.Q

D Flip-Flop

T Flip-Flop

Q+ = D

Q+ = T '.Q + T.Q'

ECE 301 - Digital Electronics

FSM Design (Moore)

Synthesis using D Flip-Flops

(Q+ = D)

ECE 301 - Digital Electronics

FSM Design: Example (Moore)

Flip-Flop Input

QA

QB

Q A+

QB+

DA

DB

Q+ = D
next state flip-flop input

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FSM Design: Example (Moore)

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FSM Design: Example (Moore)

QA

QB Q'B

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FSM Design (Moore)

Synthesis using JK Flip-Flops

(Q+ = J.Q' + K'.Q)

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FSM Design: Example (Moore)

Excitation Table

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FSM Design: Example (Moore)

QA QB QA+ QB+

Q+ = J.Q' + K'.Q
next state flip-flop inputs

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FSM Design: Example (Moore)

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FSM Design: Example (Moore)

QA

Q'A

QB

Q'B

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FSM Design (Moore)

Example:
Design a Finite State Machine (FSM) that meets the following specifications:
1. The circuit has one input, w, and one output, z. 2. All changes in the circuit occur on the positive edge of the clock. 3. The output z is equal to 1 if the pattern 101 is detected on the input w. Otherwise, the value of z is equal to 0. Overlapping sequences should not be detected.
This is another example of a sequence detector.
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FSM Design: Example (Moore)

Input (w): 0 0 0 1 0 1 0 1 1 0 1 1 0 1 1

Output (z): 0 0 0 0 0 1 0 0 0 0 1 0 0 1 0

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FSM Design: Example (Moore)

Start State

State Diagram
End State

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FSM Design (Moore)

Example:
Design a Finite State Machine (FSM) that meets the following specifications:
1. The circuit has one input, w, and one output, z. 2. All changes in the circuit occur on the positive edge of the clock. 3. The output z is equal to 1 if the pattern 101 is detected on the input w. Otherwise, the value of z is equal to 0. Overlapping sequences should be detected.
This is another example of a sequence detector.
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FSM Design: Example (Moore)

Input (w): 0 0 0 1 0 1 0 1 1 0 1 1 0 1 1

Output (z): 0 0 0 0 0 1 0 1 0 0 1 0 0 1 0

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FSM Design: Example (Moore)

Start State

State Diagram
End State

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FSM Design (Moore)

Example:
Design a Finite State Machine (FSM) that meets the following specifications:
1. The circuit has one input, w, and one output, z. 2. All changes in the circuit occur on the positive edge of the clock. 3. The output z is equal to 1 if the pattern 110 or the pattern 010 is detected on the input w. Otherwise, the value of z is equal to 0. Overlapping sequences should be detected.
This is example of a sequence detector that can detect 2 sequences.
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FSM Design: Example (Moore)

Input (w): 0 1 0 0 1 1 0 1 0 1 1 1 0 1 1

Output (z): 0 0 1 0 0 0 1 0 1 0 0 0 1 0 0

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FSM Design: Example (Moore)

State Diagram

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Acknowledgments

The slides used in this lecture were taken, with permission, from those provided by Pearson Prentice Hall for Digital Design (4th Edition). They are the property of and are copyrighted by Pearson Education.

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