Download as ppt, pdf, or txt
Download as ppt, pdf, or txt
You are on page 1of 17

Microcontrollers & Embedded Systems

The 8051 Microcontroller ALP AND CP


Sudipta Mahapatra, Ph.D. Department of E & ECE IIT Kharagpur

Module-2 : The 8051 ALP


8051 ALP; Programming model, Instruction set, Addressing modes; 8051 programming in C.

Book: 1. The 8051 Microcontroller and Embedded Systems Using Assembly and C, Mazidi M. A.. 2. Microcontrollers Principles and Applications, Ajit Pal Figures have been taken from Lectures slides on Microcontrollers prepared by Chung-Ping Young, Home Automation, Networking, and Entertainment Lab Dept. of Computer Science and Information Engineering National Cheng Kung University, TAIWAN
2

Data Representation
Sign-magnitude +25= 0 0011001 -25= 1 0011001 Ones complement +25= 0 0011001 -25= 1 1100110 Twos complement +25= 0 0011001 -25= 1 1100111

Sign extension
+25= 00011001 -25= 11100111 0000000000011001 1111111111100111
3

8051 Instructions
1-byte Instruction: CPL, RLC, SWAP, ADD 2-byte Instruction: OpCode Immediate or I/O addr. ADD A, #DATA 3-byte Instruction OpCode addr., addr. MOV mem_addr.1, mem_addr. 2

8051 RAM Locations


128 bytes: Locations 00H-1FH: Register banks and stack 20H-2FH: Bit addressable portion 30H-7FH: As RAM locations

Addressing Modes
Inherent: CPL, RLC, RRC Immediate: MOV A, #26H; MOV DPTR, #4521H MOV P1, #55H Register: MOV A, R7; MOV R0, A Direct: MOV A, 56H; MOV 7FH, R4// The address generally in the range 30H-7FH. Register Indirect: Internal RAM: MOV A, @Ri , i=0,1, SP; External RAM: MOVX A, @R1; MOVX @DPTR, A Indexed (Based): MOVC A, @A+DPTR, MOVC A, @A+PC // C-code Relative: SJMP rel ; PC=PC+2+rel // rel-a signed 8-bit offset Stack: PUSH 0E0H, POP 04H //not PUSH A, POP R4
6

Instruction Set
Data transfer: General purpose, ACC-specific, Addr.-obj Arithmetic: ADD, ADDC, MUL AB, DIV AB Logic: CLR A, CLR A.7, SETB C, RL Control Transfer: ACALL (abs. call), LCALL, RET, AJMP (abs. jump), LJMP, SJMP JMP @a+DPTR; PC=A+DPTR JZ, JNZ, CJNE, DJNZ RET, RETI Bit manipulation Instructions: SETD bit, CLR bit Note: For 8051 instruction set, go to the site:
http://www.keil.com/support/man/docs/is51/is51_instructionees.htm
7

Instructions affecting the flag bits

PSW Register

Auxiliary carry Carry

Overflow

Pseudo codes
ORG Origin EQU Equate DB Define byte: How is it different from EQU? END End of source program

10

Example

11

Example

12

Example

13

Delay Generation
Clock Frequency=11.0592 MHz Time for 1 machine cycle=12*10-6/11.0592 s = 1.085 s.

2 230

// 1 m/c // 2 m/c

Time Delay=(1+230*2)*1.085 s=500 s Maximum Delay=?

14

Problem
1. Write a program to add two 16-bit numbers ABC6H and 2345H. Place the lower byte of the result in R5 and the upper byte in R6. 2. Write a program to add two multi-byte numbers stored in RAM starting from locations 30H and 40H. Size of data is in memory location 50H. Store the result starting from 60H. 3. Write a program in 8051 assembly language to generate delay using a nested loop. 4. Write an 8051 assembly language program to convert 1-byte binary data to 3-digit packed BCD data.

5. Write a program to calculate the checksum of 50 bytes of data stored in RAM locations starting from 30H. Store the result in register R3.
15

Problem
6. Searching 7. Sorting

16

Typical Steps in Coding

17

You might also like