Physical Design of ICs

by MUNISH VERMA, Astt. Prof. Dept of ECE, H.C.T.M, KAITHAL

VLSI Design Cycle

System Specification

Functional Design

X=(AB*CD)+(A+D)+(A(B+C))
Y=(A(B+C))+AC+D+A(BC+D)) Logic Design

Circuit Design

VLSI Design Cycle

Physical Design

Fabrication

Packaging

Y-Chart

Physical Design
Physical design (or layout phase) is the process of determining the physical location of active devices and interconnecting them inside the boundary of a VLSI chip (i.e., an integrated circuit).
The physical design cycle consists of

1. Partitioning
2. Floorplanning and Placement

3. Routing
4. Layout Optimization & verification
5

Layout Methodologies
Partitioning is the task of dividing a circuit into smaller parts.

Floorplanning is the determination of the approximate location of each module in a rectangular chip area.

Layout Methodologies
Placement, when each module is fixed, that is, has fixed shape and fixed terminals, is the determination of the best position for each module

Global routing decomposes a large routing problem into small, manageable problems for detailed routing.
7

Layout Methodologies
Detailed routing follows the global routing to effectively realize interconnections in VLSI circuits.
Layout optimization is a postprocessing step . In this stage the layout is optimized, for example, by compacting the area

Layout verification is the testing of a layout to determine if it satisfies design and layout rules .
8

Layout Rules & Circuit Abstraction

A circuit is laid out according to a set of layout rules (or geometric design rules). The layout rules, being in the form of minimum allowable values for certain widths, separations, and overlaps, reflect the constraints imposed by the current technology . R1. Wire width : Each wire in layer Li, (1 i v) has a minimum width wi. wi > wi-1

Layout Rules & Circuit Abstraction

R2. Wire separation : Two wires in layer Li have a minimum separation of si R3. Contact rule : To connect two wires in layers Li and Lj (i < j) a contact (via) must be established . The two wires must overlap for ej x ej units and the contact cut must be aj x aj units.

10

Other Definitions
The chip area is the smallest rectangle (IC packages are rectangular in shape) enclosing a legal layout of the circuit. A plane figure is called a tile if the plane can be covered by copies of the figure without gaps and overlaps (the covering is then called a tessellation). A square tessellation is one whose tiles are squares. The dual of the tessellation is called a (square) grid-graph.
11

 A circuit C = {M,N} consists of a collection M = {M1, . . . , Mm} of modules-each module being a collection of active devices-and a set N ={N1, . . . , Nn} of nets. Each net specifies a subset of points on the boundary of the modules to be interconnected. A circuit graph GC is a hypergraph associated with C, where vertices correspond to the modules and hyperedges correspond to the nets . A solution to the grid layout problem consists of embedding each module Mi, (1 < i < m) of the circuit on the grid using a finite collection of tiles and interconnecting the terminals of each net by means of wires in the region outside the modules .
12

13

Cell Generation
In VLSI design, a logic function is implemented by means of a circuit consisting of one or more basic cells. The set of cells form a library that can be used in the design phase. Cell generation techniques are classified as random generation or regular style. A random generation technique is obtained by placing the basic components and interconnecting them. That is, there is no regular connection pattern. It is difficult to create a library of such cells because of their complexity. In contrast, in a regular style the interconnection technique follows a regular pattern.
14

1. Programmable Logic Arrays

15

2. Transistor Chaining
Traversing a set of transistors in a cell dictates a linear ordering. Transistor chaining is the problem of traversing the transistors in an optimal manner. In CMOS technology, PMOS and NMOS sides are dual of each other. If two transistors are placed side by side and the source or drain of one is to be connected to the source or drain of the other, then no separation (or space) is needed between the two transistors; otherwise, the two transistors need to be separated. Thus an optimal traversal corresponds to a minimum separation layout.
16

17

18

3. Weinberger Arrays and Gate Matrices

Weinberger Arrays was one of the first methods for regular-style layout. The idea is to have a set of columns and rows, each row corresponding to a gate signal and the columns responsible for realization of internal signals. Gate matrix layout was first introduced by Lopez and Law as a systematic approach to VLSI layout. One of the objectives in the gate matrix layout problem is to find a layout that uses the minimum number of rows by permuting columns. The structure of the gate matrix layout is as follows:
19

cntd

20

cntd
In a gate matrix layout, a vertical polysilicon wire corresponding to a net is placed in every column. The number of columns is fixed. All transistors using the same gate signal are constructed along the same column. Transistors placed in adjacent columns of the same row are connected using shared diffusion. Transistors separated by one or more polysilicon columns are connected by metal lines. Connections to power and ground are in the second metal layer.
21

Layout Environments
Full Custom
Designer designs all circuitry & interconnection paths

Semi Custom
Library of pre-designed cells is available

Universal
Designer programs the interconnections e.g. PLA, FPGA Designer chooses the appropriate ones & places them Can be designed faster Area efficiency is sacrificed
22

No Restrictions

Restrictions imposed on the organization of cells

Time consuming Good Area utilization

Can be designed faster Area efficiency is sacrificed

Layout of Standard Cell

The layout of standard cells consists of rows of cells. Here each cell is a simple circuit element such as a flip-flop or a logic gate. The cells are stored in a cell library and usually need not be designed. All masks need to be fabricated for a standard cell design. Since each standard cell chip involves a new set of masks, the probability of failure is increased as compared to other design styles, and designers need to take care of nonfunctional aspects of chip design such as design rule check, latchup, power distribution, and heat distribution. 23

Gate Arrays & Sea-of-Gates

In a gate array, each cell is an array of transistors. Each cell is capable of implementing a simple gate or a latch by interconnecting a set of transistors. The cells are arranged in rows to allow spaces for routing channels. In sea-of-gates architecture, the whole substrate is filled with transistors. All transistors in gate arrays are prefabricated. The entire gate array substrate is prefabricated up to contact layer. The patterns of metals 1 and 2 define the cell functions and routing. Thus only a fraction of masks needs to be designed. This reduces the probability of failure. Also, since the early processing steps are prefabricated, processing time is shortened.
24

FPGAs
All the circuit elements of a FPGA are prefabricated. In a PLA, only the connections are programmable. However in a FPGA, not only are the connections programmable, the cells are also programmable to achieve different functions. Each cell of a FPGA typically contains flip-flops, multiplexors, and programmable functional gates. The gates can usually realize any function of a small set of inputs. It may also contain testing circuitry for fabrication. This is an advantage over the standard cells and gate arrays, where testing circuitry must be incorporated into the functional circuitry and the designer has to take into consideration the extra testing circuitry. The cells may be organized in one-dimensional or twodimensional manner. Several types of routing resources are available. There are global wires that connect to every cell to provide global communication. Shorter wire segments are used for local signal communication.
25

26

Packaging
These chips must be supported by an equally fast and reliable packaging technology. Packaging supplies chips with signals and powers, and removes the heat generated by circuitry. Packaging determines the overall speed, cost & reliability of high-speed systems. Dual In-line Packaging (DIP). A DIP has a small number of pins. Pin Grid Arrays (PGA) have more pins that are distributed around the packages.
27

cntd
Multichip module (MCM) technology In MCM technique, several s/c chips, interconnected in a high density substrate, are placed into a single package Compared with single chip packages or surface mount packages, MCMs can reduce circuit board area by five to ten times and improve system performance by 20% or more. Chips are placed and bonded on a surface at the top layer (called the chip layer). Below the chip layer, a set of pin redistribution layers is provided for distributing chip I/O pins for signal distribution 28 layers.