CPLD

Ni dung
Tng quan v FPLD
Lch s Cc tha hip (tradeoffs)

CPLD
M t tng qut Cu trc c bn

Nh cung cp thit b c th
Xilinx Altera

Lot Xilinx XC9500 Bi tp CPLD

H thng phn cp thc hin Logic

Logic

Standard Logic

ASIC
Programmable Logic Devices

Hm nay tp trung

(FPLDs)

Gate Arrays

Cell-Based ICs

Full Custom ICs

SPLDs (e.g., PALs)

CPLDs

FPGAs

T vit tt SPLD = Simple Programmable Logic Device PAL = Programmable Array Logic CPLD = Complex PLD FPGA = Field Programmable Gate Array ASIC = Application Specific IC

Cc ti nguyn thng gp Configurable Logic Blocks (CLB)

Memory Look-Up Table (LUT) AND-OR planes Simple gates

Input / Output Blocks (IOB)

Bidirectional, latches, inverters, pullup/pulldowns

Interconnect hoc Routing

Local, internal feedback, and global

Cc thit b logic lp trnh c

Thnh phn chc nng c nh ngha bi ngi s dng theo chng trnh iu khin Cc cell logic c kt ni vi nhau bng cch lp trnh u im:
Thit k linh hot thay i bng cch lp trnh li, d dng thay i thit k Gim thi gian sn xut nguyn mu Quy m tch hp ln (trn 100,000 cng) Tng tin cy, t ri ro ti chnh Thit b nh hn, chi ph khi ng thp

Dung lng FPLD

Cc cng tng ng cp mt cch lng lo n s cng NAND hai ng vo. th ny hng dn la chn mt thit b cho mt ng dng theo dung lng logic cn thit. Mi loi FPLD vn ph hp hn cho mt s ng dng hn cc loi khc.

Cc tha hip cng ngh s

Thc hin cng ngh no?

Kinh t so vi cc yu t k thut
Mt vi slide k tip so snh kinh t v cc yu t k thut kt hp vi nhng cng ngh ny
Cc thnh phn chun

SSI/MSI

SPLD

CPLD FPGA

Gate Array

Std. Cell

Full Custom

Cc cng ngh bn c ch (semicustom)

7

So snh thc hin

Bng di y a ra mt so snh cc cng ngh thc hin chnh da trn 4 yu t then cht

SSI/MSI

SPLD

FPGA

Gate Array

Standard Cell

Full Custom

Gates/Component

5 - 100

50 - 5K

100 - 10K

500 - 100K

10K - 500K

100K - 10M

Cost/Gate High NRE Cost ($) 1-2K 2-10K 5-50K 10-100K Low 50K-5M

Development time (weeks)

1-2

1-2

2-20

5-50

20-200

So snh thc hin

Circuit Cost As A Function Of Volume

Cost
Discrete

Full custom

Volume
9

S pht trin ca cc cng ngh

CPLD v FPGA tip tc tin trin song song
1960
standard components

SSI

1970

MSI LSI VLSI

semicustom components

Gate Array 1980 Standard Cells

Simple PLD

1990

CPLD

FPGA

2000
parallel development

Today
10

Ba loi FPLD
Simple Programmable Logic Device (SPLD)
Thit b LSI t hn 1000 cng logic

Complex Programmable Logic Device (CPLD)

Thit b VLSI Dung lng logic cao hn SPLD

Field Programmable Gate Array (FPGA)

Thit b VLSI Dung lng logic cao hn CPLD
Programmable Logic Devices (FPLDs)

SPLDs (e.g., PALs)

CPLDs

FPGAs

11

Ba loi FPLD
Simple Programmable Logic Device (SPLD)
PLA hoc PAL nh tuyn bn trong c nh, thi gian tr lan truyn tt nh

Complex Programmable Logic Device (CPLD)

Nhiu SPLD trn mt chip n Lp trnh kt ni

Field Programmable Gate Array (FPGA)

Mt mng cc khi logic S lng cng ln, ngi dng c th la chn kt ni, thi gian tr ph thuc vo thit k v nh tuyn T l flip-flop cao so vi cc ngun ti nguyn logic
Programmable Logic Devices (FPLDs)

SPLDs (e.g., PALs)

CPLDs

FPGAs

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SPLD
SPLD = Simple PLD Cc loi cu trc SPLD ph bin
Programmable Logic Array, PLA Programmable Array Logic, PAL (Vantis) General Array Logic, GAL (Lattice) Khc

Cc cu trc khc nhau

AND so vi thc hin OR Kh nng lp trnh (vd., EE) Khi logic c bn
SPLDs (e.g., PALs)

Programmable Logic Devices (FPLDs)

CPLDs

FPGAs

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SPLD
Chng ta c ci nhn cn cnh vi SPLD PLA-ging nh SPLD c m t bn tri
Logic Functions

Thit b PAL v GAL a ra mt gii php tt hn

Sums

SPLD thay th tt cho cc thit b SSI v MSI

c bit l lp trnh li c
Programmable Logic Devices (FPLDs)

Product Terms
SPLDs (e.g., PALs) CPLDs FPGAs

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SPLD
Lp trnh logic thng thng
PAL, PLA, GAL Cc linh kin chun nh GAL22V10 v PAL16R4 c sn t cc nh cung cp

Cc cell logic lp trnh mc gii hn (ty chn lp trnh cc cell I/O, c th c c nh bi cc cng AND/OR), mng nh tuyn b hn ch Mt thp nht trong s cc thit b lp trnh c, tuy nhin, nng sut vn hnh c th rt cao SPLD gn nh thay th logic TTL, nhng thit b m phng php thc hin logic chim u th SPLDs
Programmable Logic Devices (FPLDs)

(e.g., PALs)

CPLDs

FPGAs

15

Lm th no m rng cu trc SPLD?

Tng s lng ng vo v ng ra trong mt PLD thng thng?
V d., 16V8 20V8 22V10 Ti sao khng 32V16 128V64 ?

Cc vn :
n ln s lng ng vo v ng ra cn n2 din tch chip qu tn km Logic tr nn chm hn khi s lng ng vo mng AND tng ln
Programmable Logic Devices (FPLDs)

SPLDs (e.g., PALs)

CPLDs

FPGAs

16

Lm th no m rng cu trc SPLD?

Gii php:
Nhiu SPLD vi mt lin kt lp trnh c tng i nh Ni chung nh hn mt PLD ln C th s dng phn mm fitter phn chia cc khi PLD nh hn

Programmable Logic Devices (FPLDs)

CPLD Architecture
SPLDs (e.g., PALs) CPLDs FPGAs

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CPLD
PAL v GAL ch c c trong cc kch thc nh
Tng ng vi mt vi trm cng logic

i vi cc mch logic ln hn, PLD phc tp hay CPLD c th c s dng. CPLD tng ng vi mt vi PAL/GAL
c lin kt bi cc lin kt lp trnh c Tt c trong mt mch tch hp (IC)

CPLD c th c thay th bi hng ngn, hoc thm ch hng trm ngn cc cng logic ring l
Mt tch hp c tng cao
Programmable Logic Devices (FPLDs)

SPLDs (e.g., PALs)

CPLDs

FPGAs

18

Complex PLD
Mt vi loi CPLD c lp trnh s dng b lp trnh PAL, nhng phng php ny tr nn khng thun tin i vi cc thit b c hng trm chn. Mt phng php lp trnh th hai l hn thit b trn board mch in, sau np chng trnh vi mt lung d liu ni tip t my tnh c nhn. CPLD cha mt mch in gii m lung d liu v cu hnh cho CPLD thc hin hm logic ring bit ca n.
Programmable Logic Devices (FPLDs)

SPLDs (e.g., PALs)

CPLDs

FPGAs

19

Complex PLD
Mi nh sn xut c mt tn c quyn cho h thng lp trnh CPLD V d, Lattice gi n l "in-system programming" Tuy nhin, nhng h thng c quyn ny ang bt u loi b tin n mt chun gi l Joint Test Action Group (JTAG)

Programmable Logic Devices (FPLDs)

SPLDs (e.g., PALs)

CPLDs

FPGAs

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Complex PLD so vi FPGA

CPLD
Interconnect style Architecture and timing Software compile times In-system performance Power consumption Applications addressed Continuous Predictable Short Fast High Combinational and registered logic

FPGA
Segmented Unpredictable Long Moderate Moderate Registered logic only Source: Altera
SPLDs (e.g., PALs) CPLDs FPGAs
Programmable Logic Devices (FPLDs)

21

Cu trc CPLD
Cu trc CPLD n gin S lng kh nh PLD (v d., 36V18) trn mt chip duy nht Lin kt lp trnh c gia cc PLD S lng ln cc khi I/O S lng ln cc chn

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Cu trc CPLD
Cu trc tng qut ca complex PLD Mng lin kt lp trnh c (PIA)
C kh nng kt ni bt k u vo hay u ra LAB ny n bt k LAB khc

Cc khi mng logic (LAB: Logic Array Blocks)

SPLD phc tp cu trc ging nhau

Cc khi ng vo/ng ra
SPLDs (e.g., PALs)

Programmable Logic Devices (FPLDs)

CPLDs

FPGAs

23

Cu trc CPLD
Mi SPLD ging nhau trong CPLD c th c lp trnh nh vi mt PAL hay GAL Nhiu khi SPLD ging nhau (v d, LAB) c bao gm trong mt CPLD LAB c th c kt ni vi nhau xy dng cc h thng logic ln hn
Programmable Logic Devices (FPLDs)

Feedback Outputs

CPLD Architecture

SPLDs (e.g., PALs)

CPLDs

FPGAs

24

CPLD
S cu thnh Complex PLD
in hnh bao gm 2-64 SPLD Kt ni vi nhau s dng logic phc tp Bao gm cc macrocell Bao gm cc khi input/output

Tit kim khi thit k cc h thng ln Tc chuyn mch nhanh

Programmable Logic Devices (FPLDs)

SPLDs (e.g., PALs)

CPLDs

FPGAs

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CPLD
Complex PLD c cc mng PLD trn mt chip, vi mt ma trn lin kt kt ni chng li vi nhau. Thi gian thc hin c th d on nhiu hn so vi FPGA bi v cu trc kt ni n gin hn. Mt thng thng nh hn hu ht FPGA (mc d CPLD tinh vi s c v mt ging nh FPGA r nht).
Nng sut vn hnh ca CPLD thng l tt hn FPGA, nhng ph thuc vo nh cung cp, s lng cc cell trong CPLD
SPLDs (e.g., PALs)

Programmable Logic Devices (FPLDs)

CPLDs

FPGAs

26

CPLD
S khi bn phi cho CPLD Cypress Semiconductor (Ultra37128) m t cu trc tng qut ca CPLD

Programmable Logic Devices (FPLDs)

SPLDs (e.g., PALs)

CPLDs

FPGAs

27

H Cypress Ultra 37000

CMOS CPLD lp trnh c trn h thng
Giao din JTAG c th cu hnh li c Thay i thit k khng lm thay i s chn Thay i thit k khng gy ra thay i thi gian

Mt cao
32 n 512 macrocell 32 n 264 chn I/O Nm ng vo chuyn dng bao gm bn chn ng h

28

H Cypress Ultra 37000

Cc c tnh ca thit b h Ultra 37000

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CPLD
Complex Programmable Logic Devices
Cha t 10-1000 macrocell Mi macrocell tng ng vi khong 20 cng H tr ln n 200 chn I/O

Cc ngun ti nguyn quan trng trong mt CPLD l lin kt lp trnh c

S tha hip gia khng gian cho macrocell v khng gian kt ni Thit k cn thn s gii hn cc kt ni gia cc macrocell
Programmable Logic Devices (FPLDs)

SPLDs (e.g., PALs)

CPLDs

FPGAs

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Cu trc CPLD
phc tp ca CPLD l gia FPGA v SPLD

LAB Logic Array Block / dng PAL PIA Programmable Interconnect Array

31

Cu trc CPLD
V d khi mng logic

Hm ph (vd., g, h) cc ng vo s hng OR

2:1 Mux

D-FF

K t cc ng vo (vd., a, b, c)

PLA-ging nh mng AND

32

Mng lin kt lp trnh c

Bao gm cc kt ni chy khp CPLD kt ni cc macrocell trong mi LAB PIA ny cng kt ni cc cng AND v cc thnh phn khc ca macrocell

33

Nh cung cp CPLD/FPGA
Nh cung cp chnh

34

Cc h CPLD
Cc khi PLD ring l ging nhau (Xilinx FB) c lp li trong cc thnh vin h khc nhau
S khi PLD khc nhau S chn I/O khc nhau

Xilinx XC9500 CPLD Series

35

Cc v CPLD tiu biu

CPLD c to ra bng cch s dng 2 n 64 SPLD Cc v s dng 44 chn n trn 200 chn (hoc hn)

36

Cc v CPLD tiu biu

QFP = Quad Flat Package
QFP l mt v IC vi cc chn m rng t bn pha. N c s dng ch yu gn b mt, khng lp vo

TQFP = Thin Quad Flat Package PQFP = Plastic Quad Flat Package VQFP = Very small Quad Flat Package PLCC = Plastic Leaded Chip Carrier
Mt dng v lin quan n QFP Tng t nhng c chn vi khong cch ln hn, cong ln bn di mt thn dy hn n gin ha vic lp vo

37

Cc dng v CPLD
CSP = Chip Scale Package
V IC vi mt din tch khng ln hn 1.2 ln so vi khun (die)

BGA = Ball Grid Array

Mt loi v dn b mt c s dng cho cc IC Cc chn c thay th bi cc bng hn dnh bn di v Thit b c t trn mt PCB mang cc pad ng theo mt mu ph hp vi cc bng hn Vic lp rp sau c un nng lm tan chy cc bng hn

38

Cc h CPLD
Nhiu CPLD c t chn I/O hn macrocell
Cc macrocell c chn vi cung cp cc s hng logic cn thit bn trong nhng cc ng ra ny khng c kt ni bn ngoi Kch thc v IC cho bit s chn I/O nhng khng phi l tng s macrocell Cc h CPLD tiu biu c cc thit b vi cc ngun ti nguyn khc nhau trong cng mt v IC

39

Xilinx CPLD
Thng bo chng cho trong ngun ti nguyn sn c trong mt gi ring.

40

Datasheet CPLD XC9572

CPLD XC9572 t Xilinx 7.5 ns thi gian tr logic t chn n chn trn tt c cc chn 72 macrocell vi 1,600 cng s dng c Ln n 72 chn I/O Bn khi chc nng 36V18 C sn dng 44-chn PLCC, 84-chn PLCC, 100chn PQFP v 100-chn TQFP
41

V CPLD XC9572
S chn XC9572 dng v PLCC 84 chn v hnh nh dng v TQFP 100 chn
84-chn PLCC (chn 1) 100-chn TQFP

42

S thnh phn CPLD XC9572

S thnh phn ca thit b CPLD Xilinx bao gm cc thng tin nh sau:

43

S khi CPLD XC9500

H XC9500 CPLD cung cp lp trnh trn h thng tin tin v kim tra cc kh nng cho hiu sut cao, tch hp logic mc ch chung. Tt c cc thit b lp trnh c trn h thng vi ti thiu 10.000 chng trnh /chu k xa.

44

Cc khi chc nng h 9500

18 macrocell trn FB 36 ng vo trn FB (thch thc phn vng, cng l l do kch thc nh gn ca FB) Cc ng ra Macrocell c th i n cc cell I/O hoc tr v ma trn chuyn mch c nh tuyn n y hoc FB khc

45

Macrocell lot 9500

18 macrocell trn Khi Chc Nng (Function Block)
iu khin Set Lp trnh o ngc hoc XOR s hng tch Ln n 5 s hng tch Xung clock ton cc hoc xung clock s hng tch iu khin Reset

iu khin OE
46

Lot 9500 s hng tch phn chia

Chia s cc thut ng t bn trn v bn di
Cc thit b li lp trnh c

47

H XC9500
Mt khi I/O bao gm cc b m u vo, b m u ra, b a hp iu khin u ra v iu khin t iu khin Slew rate c s dng lm nhn cnh ln v cnh xung ca xung ra. iu khin ni t c s dng lm cho cc chn ng vo/ng ra (I/O) cng ni t (gim nhiu) Mi chn ng vo/ng ra c th mang mt dng in 24 mA.

48

Khi I/O lot 9500

OE Multiplexer (OE MUX) iu khin mt ng ra cho php hoc ngng. N c iu khin bi tn hiu t macrocell hoc tn hiu t chn GTS (Global Three-State control). C 4 chn GTS trong XC95216 v XC95288 hai trong cc lot khc.

49

Datasheet CPLD XC95108

XC95108 chia s cc c tnh ca tt c cc thit b lot XC9500 khc 108 macrocell vi 2400 cng s dng c Ln n 108 chn I/O Su khi chc nng 36V18 10,000 chng trnh/chu k xa C sn loi 84-chn PLCC, 100-chn PQFP, 100-chn TQFP v 160-chn PQFP

50

Datasheet CPLD XC95108

S khi XC95108 tng t nh tt c cc thit b khc trong h XC9500

51

Ma trn chuyn mch ca XC95108

Could be anything from a limited set of multiplexers to a full crossbar
B a hp nh, nhanh, nhng kh lp rp Thanh ngang (Crossbar ) d lp rp nhng ln v chm

52