Design a MIPS 32-bit Single-Cycle CPU

Instructor: Prof. Ho Viet Viet

TA: Nguyen Van Hieu Group 6: Luong Tran Nhat Trung Le Minh Hoang Le Hong Thanng

I. Table of Content

Block diagram Extend module Mux RegDst module Shift Left 2 module CheckZero module Mux4Addrto1 module Simulation

Block Diagram
Traditional

After improvements

Control Signal Module

Extend module
We need a unit to sign-extend the 16-bit offset field in the instruction to a 32bit signed value. In our case, if zero-sign is 0, we will extend zero for whatever sign; and if it is 1, we will extend the sign with 1, or 0

Below is the simulation of this module

Mux RegDst module

This multiplexor is used to choose instr [20-16] (rt), or instr [15-11] (rd).

In the above simulation, you can see that with RegDst = 1, the output is input 1. With RegDst = 0, the output is input 0

Shift Left 2 Addr, and Shift Left 2 module

This module is used for the jump target address, which is obtained by shifting the lower 26 biys of the jump instruction left 2 bits, effectively adding 00 as the low-order bits, and then concatenating the upper 4 bits of PC+4 as the high-order bits, thus yielding a 32-bit address. Also, this module is used for bne in shifting left sign_extend (imm16) <<2

CheckZero module
This module is used to check if the result of a certain operation is zero or not. If the output is 1, the result is zero; otherwise, it is not zero. Breakthrough : instead of putting the ZeroFlag module inside ALU like we did in Lab 2, we make this task faster by putting outside. Specifically, we check the inputs first. If they are equal, Zero is 1. If they are not, Zero is 0 Below is the simulation of this module

Mux4Addrto1 module
This module is used to combine all muxes on the right upper. Below is to show the improvement specifically

Simulation