Professional Documents
Culture Documents
Congestion Driven Placement ICM03 Final
Congestion Driven Placement ICM03 Final
Shawki Areibi and Zhen Yang School of Engineering, University of Guelph, Ontario, Canada
December 2003 (sareibi@uoguelph.ca, zyang@uoguelph.ca)
Outline
Introduction
Background
Motivation
Congestion Optimization
Experimental Results
Summary & Conclusions
ICM 2003, Cairo
Introduction
The interconnect has become a critical determiner of circuit performance in the deep sub-micron regime. Circuit placement is starting to play an important role in todays high performance chip designs. In addition to wire length optimization, the issue of reducing excessive congestion in local regions such that the router can finish the routing successfully is becoming another important problem.
ICM 2003, Cairo
VLSI Design
Specification Architectural design
Physical Design
Partitioning
Logic design
Circuit design Physical design
Placement
Routing Test/Fabrication
Layout Style
Layout Styles
Full Custom
Standard Cell
Macro Cell
Gate Array
FPGA
Advantages:
High productivity More efficient space Well-suited for automated design
Objectives
Make the size of each component within prescribed ranges Minimize the number of connections between the components.
8
1 5
In2
In1
In3
1 7 3
In6
5 8 6
In 4 Out1
2
7 3 6 4
Out1
In5
4
In8
In7
Circuit Layout
Global Routing
Objectives
Minimize the total wire length and critical path delay.
10
Circuit Layout
Determine the location of modules. Connect the modules inside the boundary of a VLSI chip. Typical Objectives Minimize the chip area Minimize the interconnect delay
W O R L D H E L L O
10
determines the physical layout of a chip. Gate delay - The quality of the attainable routing is 0.1 1.0um 0.5um 0.25um highly determined by the placement.
Minimum Feature Size
11
Placement Techniques
Placement Algorithms Constructive Placement
Numerical Optimizatio n
Genetic Placement
Partitioning Placement
Force-directed Placement
12
Produce
Produce
a good final
placement
13
Multi-Level Clustering
1. Bottom-up procedure (clustering) 2. Top-down procedure (de-clustering)
clusters formed from cells in previous level Level n . . . . Level 1 initial placement iterative improvement
cluster
de-cluster
14
Congestion
Global Bin Global Bin Edge
Integrated Technique
Post-processing Technique
Quadratic Placment
Simulated Annealing
Congestion Optimization
Module Description & Netlist Routing Estimation Congested Region Identification Congested Region Expanding
Initial Placement
Iterative Improvement
Congestion Reduction
Routing Estimation
Bounding Box Routing Estimation.
Based on the probability of having a wire within a global bin covered by the bounding box of net K:
bin(0,2)
For each yellow bin, the Horizontal Routing Demand of net K is:1/3 Total Horizontal Routing Demand of net K :2
Net K
bin(0,0) bin(2,0)
A global bin is congested if one of its four global edges is congested. A maximum number of congested bins in one congested region is set to prevent forming too large congested regions.
Bin(i,j)
Congested Reg_3 Congested Reg_2 Congested Reg_1
ICM 2003, Cairo
Neighborhood bins
Test Circuits
Circuit Fract cells 125 Pads 24 Nets 147 Pins 876 Rows 6
Small
Prim1
Struct Ind1
752
1888 2271 2907 6417
81
64 814 107 97
904
1920 2478 3029 5742
5526
5471 8513 18407 26947
16
21 16 28 46
Medium
Prim2 Bio
Ind2
12142
21854 25114
495
64 64
13419
22124 25384
125555
82601 82751
72
80 86
Large
Avq.s Avq.l
Experimental Results
Test Circuit Statistics (for flat approach)
Circuit Fract Prim1 Struct Ind1 Prim2 Bio Ind2 Ind3 Avq.s Avq.l cells 125 752 1888 2271 2907 6417 12142 15059 21854 25114 Nets 147 904 1920 2478 3029 5742 13419 21940 22124 25384 Grids 6x9 16x21 21x32 15x54 28x49 46x60 72x76 54x111 80x114 86x120 #c/bin 2.3 2.2 2.8 2.8 2.1 2.3 2.2 2.5 2.4 2.2 V/H Cap 6/6 11/10 8/7 19/7 16/13 11/10 17/20 27/20 12/10 12/10
ICM 2003, Cairo
0.0E+00
Ind1 Prim2
Bio
Average Congestion imp: 51% Average Wire length Increase: 3% Average CPU Time Increase: 30%
ICM 2003, Cairo
Ind1
Prim2
Bio
Ind2
Avq.s
Avq.l
Ind1
Prim2
Bio
Ind2
Avq.s
Avq.l
Results Analysis
Incorporating a post processing technique into the hierarchical placement may not be an effective way to reduce the congestion due to the interplay between the wire length placement algorithm and congestion reduction technique. The wire length minimization should be performed on clustering levels, while the congestion optimization should be only turned on at the flat level.
Wirelength Comparison
hierarchical placement.
A post-processing technique can reduce the congestion of flat placement largely by 51% on average with a slight increase of wire length. For hierarchical congestion-driven placement, it seems to be more beneficial to incorporate the congestion reduction phase at the flat level rather than within the levels of
hierarchy.
The congestion improvement achieved by performing congestion optimization at the flat level is 37% on average.
ICM 2003, Cairo
(channel capacities:2) Unroutable Layout Longer Wire length Channel Density: 2 (track: 2)
H
ICM 2003, Cairo