A SEMINAR ON LOW POWER AND AREA EFFICIENT CARRY SELECT ADDER

BY

ROHITH GOURISHETTY 2451-12-744-001

Objective To design a Carry Select Adder(CSLA) with a optimum utilization of area and power

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Low Power & Area Efficient CSLA

Agenda
Introduction Carry Select Adder Delay and Area Evaluation Principle Behind Modification Modified CSLA Delay and Area Evaluation Implementation Results Conclusion
Low Power & Area Efficient CSLA 3

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Introduction
Efficient design implementation of any ASIC requires an appropriate style which meet the design goals
Area Power Speed

Multi-dimensional Trade off

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Low Power & Area Efficient CSLA

Carry Select Adder

Ripple carry adder & MUX

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Regular CSLA

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Low Power & Area Efficient CSLA

Delay and Power Evaluation

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Contd

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Regular CSLA

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Principle Behind Modification

Binary to Excess-1 Convertor

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CSLA with BEC

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Modified CSLA

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Delay and Power Evaluation of modified CSLA

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Comparison

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Implementation Results
Typical ASIC flow Using 0.18u Technology for regular and modified CSLA

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Graphical Analysis

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Conclusion
Area No. of Reduction Bits (%) 8 9.7 16 15 32 16.7 64 17.4 Power Delay Power Area Delay Reduction Overhead Delay Product(%) (%) (%) Product(%) 7.6 14 5.2 2.9 10.56 9.8 1.76 6.7 13.63 6.7 8.18 11 15.46 3.76 12.28 14.4

Despite with a little delay overhead a optimized carry select adder has been designed

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References
Bibliography
IEEE 2012 paper on Low Power & Area Efficient CSLA by B Ram Kumar & H M Kittur J M Rabaey Digital Integrated Circuits

Webography http://en.wikipedia.org/wiki/Ca rry-select_adder http://ieeexplore.ieee.org/xpl /login.jsp?tp=&arnumber=540 7919&url=http%3A%2F%2Fiee explore.ieee.org%2Fxpls%2Fab s_all.jsp%3Farnumber%3D540 7919

IJCE 2012 paper on VLSI Realization Of Fast Carry Adder in Binary Excess by Santhosh Kannan and Bhanumathi

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