A SONOS Flash Memory and U3VNOR Array Structure

Presented By: Prabha Shankar Sinha Regd.No.-12040058 Branch-ETC (M.Tech 2nd sem) Communication System Engineering

OUTLINE

Introduction Flash Memory

4-Bit SONOS
Scaling Issues in SONOS Unique 3-D Vertical NOR Array Fabrication Process of the U3VNOR Cell Operation of the U3VNOR Simulation Models and Result Analysis Conclusion

INTRODUCTION
Semiconductor

memory is an indispensable component of modern electronic systems. Explosive growth of non-volatile flash memory application with increase of portable consumer devices. Low cost, low power, high density and high reliability are main issues in flash memory market. Memory mainly described by two terms i.e. Retention and Endurance.

IC memory classification
Volatile memories
Lose data when power down

Non-volatile memories
Keep data without power supply

SRAM

DRAM

ROM

PROM EPROM EEPROM FLASH EEPROM

Flash memory
Flash

memory cell-basically a MOSFET cell-has a floating gate /charge trapping layersandwiched between two oxide layers. Flash memory stores information in an array of memory cells made from floating-gate transistor. Each memory cell resembles a standard MOSFET except the transistor has two gates instead of one. The Floating gate(FG) is interposed between the control gate(CG) and the MOSFET channel.

Contd.
Due

to isolation of FG, any electrons placed on it are trapped there and will not discharge for many years.

Operation

When the FG holds a charge , modifies the threshold voltage (VT) of the cell (more voltage has to be applied to the CG to make the channel conduct).
Programming Erasing

Contd.

n-channel MOSFET illustrating channel hot electron injection(CHEI) :

Contd.
MOS

transistor: 1 fixed threshold voltage. Flash memory cell: VT can be changed by program/erase.
MOS transistor Id Id Floating gate transistor

programming erasing

Vgs VT

Vgs

Contd.

For read-out, a intermediate voltage is applied to the CG, and the MOSFET channel's conductivity tested , which is influenced by the FG. The current flow through the MOSFET channel is sensed and forms a binary code, reproducing the stored data.

Contd.
To

obtain the same channel charge, the programmed gate needs a higher control-gate voltage than the unprogrammed gate.

Contd.
Some of the advantages of flash memory : It can achieve the high chip density. It consist of minimum one transistor. It possesses multibit per storage property. Its fabrication process is compatible with current CMOS process. Some problems associated with flash memory : Scaling issues Equivalent gate stack thickness. Operation voltage of more than 10 volts. Does not offer arbitrary random-access. Charge Leakage.

SONOS
SONOS

- "Silicon-Oxide-Nitride-Oxide-Silicon" Multi-bit storage in a 3-D integration is achieved in SONOS flash memory which offer higher density and lower cost. It uses silicon nitride (Si3N4) instead of polysilicon for the charge storage material. SONOS promises lower programming voltages and higher program/erase cycle thereby increasing endurance .

Contd.
Figure

shows the structure of a SONOS flash memory cell.

Operation
Program

Read

Erase

Comparison with standard Flash

Offers

higher quality storage. A single shorting defect only disturbs a localized patch of charge. Requires a very thin layer of insulator in order to work, making the gate area smaller than flash. The voltage needed to bias the gate during writing is much smaller than in traditional flash. The number of write cycles much more than flash. SONOS' better scalability will result in higher capacity devices at lower costs.

4-Bit SONOS

Figure shows the structure of a 4-bit SONOS .

Scaling Issues
Fin

width - Paired Cell Interference (PCI) becomes more severe. Problems such as redistribution of injected charges, second-bit effect, and short-channel effect comes into picture. As the fin width is thinned, doping junction engineering becomes more difficult. Another limitation that makes it impossible to scale down to 20 nm is that there is a leakage current between N+ regions at the bottom of the pillar.

Contd.
Figure

shows the Leakage current of SONOS.

Unique 3-D Vertical NOR

We proposed a new NOR architecture memory array using vertical double-gate 4-bit SONOS devices shown in Figure.

Fig. 3. 3-D depiction of the U3VNOR array structure.

FABRICATION PROCESS OF THE U3VNOR

21

Contd.

22

Contd.

23

CELL OPERATION OF THE U3VNOR

Fig.6. Equivalent Ckt. Of U3VNOR

Operation Voltage Scheme of selected bit

Contd.

Simulation Models and Result

To evaluate the cell operation of the U3VNOR, 3-D and 2-D numerical simulation (ATLAS) from SILVACO was utilized. Figure and Table present a birds eye view and critical dimensions of the U3VNOR used in simulation.

27

Operation Simulation Result

Most important point is to verify the memory operation of U3VNOR. Fig. 9 & Fig.10 shows the simulation result of program and erase operation respectively.

Fig.9

Fig.10

Companies actively developing Flash memory

Freescale

ST

Microelectronics Philips Renesas Samsung Toshiba Atmel Spansion Intel

Conclusion
The

U3VNOR will be one of the promising structures for a scaled multibit flash memory. It is a highly scaled flash memory architecture having the smallest unit bit size. It is possible to solve all problems such as shortchannel effect, redistribution of injected charges, and second-bit effect without limitation of scaling. This technology has unbeatable endurance and retention. Flash memory as a replacement for hard disks.

Reference
K. Kim and G. Jeong, Memory technologies in the nano-era: Challenges and opportunities, in Proc. ISSCC, 2005, pp. 576577. C.-Y. Lu, T.-C. Lu, and R. Liu, Non-volatile memory technologyToday and tomorrow, in Proc. 13th IPFA, 2006, pp. 1823. B. Eitan, P. Pavan, I. Bloom, E. Aloni, A. Frommer, and David, NROM:Anovel localized trapping, 2-bit nonvolatile memory cell, IEEE Electron Device Lett., vol. 21, no. 6, pp. 543545, Jun. 2000.

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