16 bit CPU design using actel FPGA/dsPIC microcontroller

Carried at Ultraa Chipp Technologies Limited

By, Rakhesh Kusagur Mtech 3rd Sem USN:5WI11LVS18 VTU-RC UTL
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project on AA project on:

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Contains:
Introduction

Block diagram of the processor

The design flow Literature survey Hardware configuration Software configuration Conclusion Future work References
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INTRODUCTION
The processor or Central Processing Unit (CPU) is

the heart of the computer. In computer architecture, 16-bit integers, memory addresses, or other data units are those that are at most 16 bits (2 octets) wide. Also, 16-bit CPU and ALU architectures are those that are based on registers, address buses, or data buses of that size. 4Processors are divided into 3 categories: 8-bit, 16-bit and 32-bit processor(performance, cost, power and programmability). 8bit processors: 32 bit
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Contd..

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Block diagram of processor

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The design flow

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Design method of proposed 16 bit processor

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Literature survey
1st single chip microprocessor was the 4bit device.

Intels 4004 introduced in 1971.

Then intels 8bit microprocessor 8008.

Then intels 16bit microprocessor pentium-III.

The first 32 bit microprocessors are also came into market

in 1970s-motorola-68000.

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Contd.
The advance of Moores law has completely

outmoded 4-bit microcontrollers in favour of 8-bit processors that are far easier to program, which shortens time to market.
16-bit processors that first appeared in the late

1970s promised better system performance for a little more silicon.

However, the 16-bit processors address spaces
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were still mostly limited to the same 64kbyte VTU-RC UNITED TECHNOLOGIES LTD programming models. available in the 8-bit 4/21/2013 8:14 AM

 The right microprocessor is the one that gets your

product to market on time, on budget, with all the desired features, and for the lowest cost. Large memor requires large memory.

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Why 16 Bit processor?

Cost of memory

Cost of actual processsor.

Above two are counterbalanced by limited memory and register addressing. All major 32-bit processors now have 16-bit subsets of their instruction sets to reduce the instruction-memory footprint. Ex: Tensilicas 32-bit processors employ a 24/16bit instruction set. Despite claims that 16-bit processors require only half as much silicon as 32-bit processors.
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Hardware system configuration

Processor -FPGA-actel-060

or dsPIC microcontroller
Power supply LCD Interface-

500mA 12v transformer 16x2 Max-232

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Softaware system configuration

Operating system Language Simulator-

Windows XP Verilog or Embedded C Xilinx ISE version 10.1

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Conclusion
We have to test our processor architecture by running

addition,subtraction, booth multiplication, and restoring division programs created using Xilinx Software. Simulation has to be carried out. We have to compare the simulated output results with the expected results. From synthesis report, the minimum clock period(upto 550MHz) that can be achieved in this proposed architecture has to be noted down. All units have to be tested to verify their functionality. Finally, the performance of the processor has to be tested for addition, subtraction, booth multiplication, and restoring division programs to verify their functionality.
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Future enhancement
In order to obtain a more sophisticated

architecture we can add some advanced techniques like: -pipelining -interrupt handler and -input/output controllers. Design of systems like : -Real-time communication system -Intelligent control and -Biometric systems
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References
[1] J.L. Hennessy, D.A.Patterson, Computer Architecture: A Quantitative

Approach, Second Edition, Morgan Kaufmann and Harcourt India, 2000.

[2] J.L. Hennessy, D.A.Patterson, Computer Organization and Design:

The Hardware/Software Kaufmann, 2003. Interface, Second Edition, Morgan

[3] J.F. Wakerly, Digital Design: Principles and Practices, Third Edition,

Prentice-Hall, 2000.
[4] A. S. Tanenbaum, Structured Computer Organization, Fourth Edition,

Prentice-Hall, 2000.
[5] Yatin Trivedi and others, Verilog HDL, IC, 2000.
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[6] Mauriss M Mano, Digital Design, Third Edition, Perason Edition,

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 [7] Narayanan Iyer, Mohammad Abdallah, S.Maiyuran, Vivek Garg,

S.Spangler,

Katmai Features POR, Intel internal document.

[8] Joe Wolf, Programming Methods for the Pentium III Processors

Streaming SIMD Extensions Environment, Using the VtuneTM Performance Enhancement

Intel Technology Journal, Q2, 1999.

[9] Paul Zagacki, Deep Buch, Emile Hsieh, Hsien-Hsin Lee, Daniel

Melaku, Vladimir Pentkovski, Architecture of a 3D Software Stack for Peak Pentium III Processor Performance, Intel Technology Journal, Q2, 1999.
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Thank You

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