Professional Documents
Culture Documents
Micro Controller 8051 - New
Micro Controller 8051 - New
Micro Controller 8051 - New
Microprocessors course
Microprocessor Microcontroller
• CPU is stand-alone, RAM, • CPU, RAM, ROM, I/O and
ROM, I/O, timer are separate timer are all on a single chip
• designer can decide on the • fix amount of on-chip ROM,
amount of ROM, RAM and RAM, I/O ports
I/O ports. • for applications in which cost,
• expansive power and space are critical
• versatility • single-purpose
• general-purpose
CPU
Bus Serial
4 I/O Ports
OSC Control Port
P0 P1 P2 P3 TxD RxD
Address/Data
• Vcc ( pin 40 ):
– Vcc provides supply voltage to the chip.
– The voltage source is +5V.
• GND ( pin 20 ): ground
• XTAL1 and XTAL2 ( pins 19,18 ):
– These 2 pins provide external clock.
– Way 1 : using a quartz crystal oscillator
– Way 2 : using a TTL oscillator
– Example shows the relationship between XTAL and the
machine cycle.
C2
XTAL2
30pF
C1
XTAL1
30pF
GND
N XTAL2
C
• Using a TTL oscillator
EXTERNAL
• XTAL2 is unconnected. OSCILLATOR
SIGNAL XTAL1
GND
Solution:
10 uF 31
EA/VPP
30 pF X1
19
11.0592 MHz
8.2 K
X2
18
30 pF
9 RST
Vcc
31
EA/VPP
X1
10 uF 30 pF
X2
RST
9
8.2 K
R0
DPTR DPH DPL
R1
R2 PC PC
R3
R5
R6
R7
4k 8k 32k
0000H 0000H 0000H
0FFFH
DS5000-32
1FFFH
8751
AT89C51
8752
AT89C52 7FFFH
7FH
30H
2FH
Bit-Addressable RAM
20H
1FH Register Bank 3
18H
17H
Register Bank 2
10H
0FH Stack) Register Bank 1)
08H
07H
Register Bank 0
00H
30H
0 0 0 00H-07H
0 1 1 08H-0FH
1 0 2 10H-17H
1 1 3 18H-1FH
Example :
Num EQU 30
…
MOV R0,Num
MOV DPTR,#data1
…
ORG 100H
data1: db “IRAN”
MOV DPTR, A
MOV Rm, Rn
In other word, the content of register R0 or R1 is sources or target in MOV, ADD and SUBB
insructions.
Example:
Write a program to copy a block of 10 bytes from RAM location sterting at 37h to RAM
location starting at 59h.
Solution:
MOV R0,#37h ; source pointer
MOV R1,#59h ; dest pointer
MOV R2,#10 ; counter
L1: MOV A,@R0
MOV @R1,A
INC R0
INC R1 jump
DJNZ R2,L1
SJMP
ACALL,AJMP
LCALL,LJMP
MOVC A,@A+DPTR
A= content of address A +DPTR from ROM
Note:
Because the data elements are stored in the program
(code ) space ROM of the 8051, it uses the instruction
MOVC instead of MOV. The “C” means code.
Sunday, April 12, 2009 Munish Vashishath
Some Simple Instructions
MOV dest,source ; dest = source
MOV DPTR,#7634H
MOV DPL,#34H
MOV DPH,#76H
Note 1:
MOV A,#72H ≠ MOV A,72H
After instruction “MOV A,72H ” the content of 72’th byte of RAM will replace in Accumulator.
8086 8051
MOV AL,72H MOV A,#72H
MOV AL,’r’ MOV A,#’r’
MOV BX,72H
MOV AL,[BX] MOV A,72H
Note 2:
MOV A,R3 ≡ MOV A,3
SETB C ;CY=1
SUBB A,R5 ;A=A-R5-1
SETB C ;CY=1
ADC A,R5 ;A=A+R5+1
SETB C ; CY=1
SETB P0.0 ;bit 0 from port 0 =1
SETB P3.7 ;bit 7 from port 3 =1
SETB ACC.2 ;bit 2 from ACCUMULATOR =1
SETB 05 ;set high D5 of RAM loc. 20h
INC R7
DEC A
DEC 40H ; [40]=[40]-1
EXAMPLE:
RR A
RR:
RRC: C
RL:
RLC: C
Sunday, April 12, 2009 Munish Vashishath
ANL - ORL – XRL
Bitwise Logical Operations:
AND, OR, XOR
EXAMPLE:
MOV R5,#89H
ANL R5,#08H
30H
JZ Jump if A=0
JNZ Jump if A/=0
DJNZ Decrement and jump if A/=0
CJNE A,byte Jump if A/=byte
CJNE reg,#data Jump if byte/=#data
JC Jump if CY=1
JNC Jump if CY=0
JB Jump if bit=1
JNB Jump if bit=0
JBC Jump if bit=1 and clear bit
Solution:
MOV A,#0
MOV R2,#10
AGAIN: ADD A,#03
DJNZ R2,AGAIN ;repeat until R2=0 (10 times)
MOV R5,A
AJMP(absolute jump)
In this 2-byte instruction, It allows a jump to any memory
location within the 2k block of program memory.
SJMP(short jump)
In this 2-byte instruction. The relative address range of 00-
FFH is divided into forward and backward jumps, that is ,
within -128 to +127 bytes of memory relative to the address of
the current PC.
Note: X can be 0 or 1
Solution:
MOV R0,#37h ; source pointer
MOV R1,#59h ; dest pointer
MOV R2,#10 ; counter
L1: MOV A,@R0
MOV @R1,A
INC R0
INC R1
DJNZ R2,L1
END OH
PROGRAM
Myfile.hex
Sunday, April 12, 2009 Munish Vashishath
Example:
MOV A,#88H
ADD A,#93H
88 10001000
+93 +10010011
---- --------------
Example:
11B 00011011
MOV A,#9CH
CY=1 AC=0 P=0
ADD A,#64H
9C 10011100
Example: +64 +01100100
MOV A,#38H ---- --------------
ADD A,#2FH 100 00000000
CY=1 AC=1 P=0
38 00111000
+2F +00101111
---- --------------
67 01100111
CY=0 AC=1 P=1
END
Notice the NULL character ,0, as end of string and how we use the JZ instruction to
detect that.
END
P2 P1 to
Set LCD
Timer 0 TH0
TL0
TH0 TL0
Timer 0
TH1 TL1
Timer 1
Sunday, April 12, 2009 Munish Vashishath
TCON Register:
(MSB) (LSB)
TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0
Timer 1 Timer0 for Interrupt
Sunday, April 12, 2009 Munish Vashishath
TCON Register (2/2)
• TF (timer flag, control flag)
– TF0 for timer/counter 0; TF1 for timer/counter 1.
– TF is like a carry. Originally, TF=0. When TH-TL roll over
to 0000 from FFFFH, the TF is set to 1.
• TF=0 : not reach
• TF=1: reach
• If we enable interrupt, TF=1 will trigger ISR.
(MSB) (LSB)
TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0
Timer 1 Timer0 for Interrupt
Counter C/T = 1
T1/0 Input Pin
TR0/1
Gate
timer 1 timer 0
TMOD= 0000 0010 Timer 1 is not used.
Timer 0, mode 2,
C/T = 0 to use XTAL clock source (timer)
gate = 0 to use internal (software)
start and stop method.
• EA : Global enable/disable.
• --- : Undefined.
• ET2 :Enable Timer 2 interrupt (Reserved for Future Use).
• ES :Enable Serial port interrupt.
• ET1 :Enable Timer 1 overflow interrupt.
• EX1 :Enable External 1 interrupt.
• ET0 : Enable Timer 0 overflow interrupt.
• EX0 : Enable External 0 interrupt.
• --- : Undefined.
• --- : Undefined.
• PT2 : Reserved for Future Use
• PS : Priority of Serial port interrupt. Set/cleared by program
• PT1 : Priority of timer1 overflow interrupt. Set/cleared by program
• PX1 : Priority of external interrupt1. Set/cleared by program
• PT0 : Priority of timer 0 overflow interrupt. Set/cleared by program
• PX0 : Priority of external interrupt0. Set/cleared by program
TB1
Read pin P0.x
Output Input
Tri-state control
(active high)
L L H H Low
H H Highimpedance
(open-circuit)
TB1
Read pin
TB1
Read pin
MOV A,#55H
BACK: MOV P1,A
ACALL DELAY
CPL A
SJMP BACK
– Let P1 toggle.
– You can write to P1 directly.
1 1 P1.X pin
Internal CPU bus D Q
P1.X
0 M1
Write to latch Clk Q
TB1
Read pin
3. Read pin=1 Read latch=0
Write to latch=1
8051 IC
Sunday, April 12, 2009 Munish Vashishath
Reading “Low” at Input Pin
TB1
Read pin
3. Read pin=1 Read latch=0
Write to latch=1
8051 IC
Sunday, April 12, 2009 Munish Vashishath
Port 1 as Input ( Read from Port )
• In order to make P1 an input, the port must be programmed by writing 1 to
all the bit.
0 1 P1.X pin
Internal CPU bus D Q
1 P1.X
0
Write to latch Clk Q M1
3. write result to latch Read
pin=0 Read latch=0
Write to latch=1
TB1
Read pin
8051 IC
Sunday, April 12, 2009 Munish Vashishath
Read-modify-write Feature
• Read-modify-write Instructions
– Table C-6
• This features combines 3 actions in a single
instruction :
1. CPU reads the latch of the port
2. CPU perform the operation
3. Modifying the latch
4. Writing to the pin
– Note that 8 pins of P1 work independently.
Sunday, April 12, 2009 Munish Vashishath
Port 1 as Input ( Read from latch )
Read latch
TB2
TB1
Read pin P1.x
Vcc
10 K
P0.0
DS5000 P0.1
Port 0
P0.2
8751 P0.3
8951 P0.4
P0.5
P0.6
P0.7
D0
D7
EA
P2.0 A8
P2.7 A15
8051
Sunday, April 12, 2009 Munish Vashishath ROM
Reading ROM (1/2)
2. 74373 latches the
1. Send address to
PSEN address and send to
ROM OE
ALE ROM
G 74LS373 OC
P0.0 A0
D
P0.7 A7
Address
D0
D7
EA
P2.0 A8
P2.7 A12
8051 ROM
Sunday, April 12, 2009 Munish Vashishath
Reading ROM (2/2)
2. 74373 latches the
address and send to
PSEN ROM OE
ALE 74LS373 OC
G
P0.0 A0
D
P0.7 Address A7
D0
D7
EA 3. ROM send the
instruction back
P2.0 A8
P2.7 A12
8051
Sunday, April 12, 2009 Munish Vashishath ROM
ALE Pin
• The ALE pin is used for de-multiplexing the
address and data by connecting to the G pin of
the 74LS373 latch.
– When ALE=0, P0 provides data D0-D7.
– When ALE=1, P0 provides address A0-A7.
– The reason is to allow P0 to multiplex address and
data.