Components

Chapter 4: The Embedded Computing Platform
Computer as Components
Embedded Systems Laboratory Dept. of Computer Science & Engineering National Sun Yat-Sen University
Presenter: Chung-Fu Kao
Chapter view
CPU bus, I/O devices, and interfacing The CPU system as a framework for understanding design methodology Development environments and debugging
An alarm clock design
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Typical PC hardware platform
CPU
memory CPU bus bus interface device high-speed bus low-speed bus device
intr ctrl
DMA controller
timers
bus interface
3
Introduction
Computer platform
Microprocessors I/O devices Memory
How to interconnect microprocessors and devices using the CPU bus

device keyboard display memory
CPU
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device
device
The Embedded Computing System C.-F. Kao
The CPU bus
Wire vs. bus

Wire: a 1-bit line between two devices
wire
bus
Bus: a collection of wires with a protocol

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Bus protocol
The simplest bus protocol is the four-cycle handshake
enq 1 3
data
ack
Action
time
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Typical bus signals
Clock
provides synchronization to the bus components
R/W
true when bus is reading
Address
a n1-bit bundle
Data
a n2-bit bundle
Data ready
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A typical microprocessor bus
the CPU can read/write devices or memory, bus devices of memory cannot initiate a transfer
Device 1 Device 1
CPU
memory
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clock R/W data rdy address data
Timing diagrams
one A rising
zero
falling
10 ns stable
changing
Timing constraint C
time
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A simple transfer example
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Transfer with wait states
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State diagrams for the bus read transaction
Get data
Done
Send data
Release ack
See ack
(start here)
Address
ack
(start here)
Address
Wait
Wait
CPU
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Device
Bus read state diagram

Get data Done
one data send/receive per transfer cycle
See ack
(start here)
Address
How to speedup the transfer ? Wait

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Burst transfer
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Bus architectures: Tri-state design
1-bit tri-state design data_out data_in
enable
tri_out
System tri-state bus

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Bus architectures: Multiplexing design

Master(s)
AREQx1 AREQx2 AREQx3
AGNTx1 AGNTx2
Data (W) MUX Address MUX Control MUX
Data (R) MUX
BTRAN[1:0] BA[31:0 BWRITE BSIZE[1:0] BPROT[1:0]
DSEL 1 DSEL 2 DSEL n BWAIT
BLOK BWAIT BnRES/ BCLK
ASB Arbiter
AGNTx3
Response MUX
ASB Decoder
BERROR
select
BnRES/ BCLK
BLAST
Select-1 Select-2
Address bus Data bus Control (write, transfer type, size)

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[31:28]
Decoder
Slave(s)
Response (wait, last, error)
End of Chapter 4.2.1

I/O techniques
Programmed I/O
data are exchanged between CPU and I/O
CPU must wait until the I/O operation is complete
Interrupt-driven I/O
CPU can continues to execute other instructions
before I/O operation has completed
Direct Memory Access (DMA)

CPU does not involve the I/O transfer
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DMA: Direct Memory Access
The DMA controller includes 3 registers

a starting address register
a length register a status register
Data count
Data register Address register
Cycle stealing
DMA REQ DMA ACK INTR Read Write
Control Logic
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Possible DMA configuration

CPU
module
DMA
I/O
. . .
I/O
MEM
(a) Single-Bus, Detached DMA
CPU
module
DMA I/O
module
DMA
MEM
I/O
I/O
(b) Single-Bus, Integrated DMA-I/O System bus CPU DMA MEM I/O bus I/O
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module
I/O
The Embedded Computing System C.-F. Kao (c) I/O bus
I/O
Bus example: ARM bus
ARM supports an on-chip bus: AMBA

Advanced Microcontroller Bus Architecture
Arbiter BIU: Bus Interface Unit Other APB slaves Slave BIU APB Bridge On-chip RAM Slave BIU
CPU
Master BIU
AHB/ASB BUS
Master N Master BIU
Timer
Slave BIU
APB BUS Interrupt Controller
Decoder
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LED
Slave BIU
AMBA features
Pipelining
only AHB or ASB
Burst transfers
1, 4, 8, 16-beat transfer
Split transactions
release the current transfer
Multiple bus masters
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Bus components devices

Arbiter
BIU: Bus Interface Unit
CPU
Master BIU
AHB/ASB BUS
Master N Master BIU APB Bridge On-chip RAM Slave BIU
Other APB slaves Slave BIU

APB BUS Interrupt Controller
Timer
Slave BIU
Decoder
LED
Slave BIU
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Memory device organization
The most basic way to characterize a memory is by its capacity A 4-Mbit memory aspect ratio :
as a 1M x 4-bit array, MAX of 2
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addresses 22 as a 4M x 1-bit array, MAX of 2 different addresses
different
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Random-Access Memories (RAMs)
There are two major categories of RAM:

static RAM (SRAM)
dynamic RAM (DRAM)
The differences between SRAM and DRAM

SRAM is faster than DRAM SRAM consumes more power than DRAM more DRAM can be put on a single chip DRAM values must be periodically refreshed
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SRAM

SRAM doesnt need CLOCK signal Block diagram 15

address chip select
SRAM
8 8
output enable
write enable
32K x 8
Data_out
Timing diagram
CS R/W Adrs Data
Data_in
From SRAM
From CPU
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DRAM
Single transistor and capacitor per bit

address chip select output enable
15
DRAM
Data_out
write enable Data_in 8
CPU address bus is split into a row and a column address NO clock Refreshed
CAS-before-RAS refresh
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Other DRAMs
FPM DRAM
fast page mode switch (burst)
EDO DRAM
extended data out
SDRAM
synchronous DRAM
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Read-Only Memories (ROMs)

Read only, cannot write any data to ROMs ROMs can store data without any power ROM size
height: n input line, consists 2 addressable
n
entries width: the number of bits in each addressable entry
A ROM can encode a collection of logic functions directly from the truth table
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ROMs

Mask ROM Programmable ROM (PROM)

write once
Erasable Programmable ROM (EPROM)

can be erased using UV light and then
reprogrammed
Electrically Erasable Programmable ROM

using high voltages for erasure and
reprogramming
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Flash ROM
I/O devices

Timers / counters A/D and D/A converters Keyboards LEDs Displays Touchscreens
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Timers and counters
Very similar:
a timer is incremented by a periodic signal
a counter is incremented by an asynchronous,
occasional signal
Rollover causes interrupt
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Watchdog timer
Watchdog timer is periodically reset by system timer If watchdog is not reset, it generates an interrupt to reset the host (CPU) reset
time-out
CPU
Watchdog Timer
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A/D and D/A converters
Analog/digital (A/D) or digital/analog (D/A) converters (ADC/DAC) To interface non-digital devices to embedded systems A typical A/D interface has two major digital inputs
a data port a clock input
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DAC
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ADC
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Keyboards
Switch de-bouncing
Encoded keyboard
An array of switches is read by an encoder
row
36
LEDs
Light-emitting diodes (LEDs)

+
+5 V
Anode (+) Cathode (-)
37
Displays
Common use: 7-segment LCD display
Other high-resolution displays

cathode ray tube (CRT)
liquid crystal display (LCD) passive matrix active matrix
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Touchscreens
Includes input and output device Input device is a two-dimensional voltmeter
X
39
Touchscreen position sensing
Push
ADC conductive sheets
voltage
spacer ball
40
end of chapter 4.5
Design with microprocessors
System architecture Hardware design
The PC as a platform
Debugging Manufacturing testing
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System architecture Hardware
Hardware elements
CPU
bus memory I/O devices: networking, sensors, etc.
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System architecture Software
Functional description must be broken into pieces:

conceptual organization performance testability maintenance
Consider the H/W-S/W trade-off

using DMA to move data rather than a
programmed loop
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Hardware design

Hardware: evaluation board Software:

cross compiler:
compiles code on host for target system.
cross debugger:
displays target state, allows target system to be controlled.
target system host system serial line
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Evaluation board
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The PC as a platform
Advantages:
cheap and easy to get
rich and familiar software environment
Disadvantages:
requires a lot of hardware resources not well-adapted to real-time high power consumption
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Typical PC hardware platform
CPU
memory CPU bus bus interface device high-speed bus low-speed bus device
intr ctrl
DMA controller
timers
bus interface
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Typical busses
ISA (Industry Standard Architecture)

original IBM PC bus, low-speed by todays
standard.
PCI (Peripheral Component Interconnect)

standard for high-speed interfacing 33 or 66 MHz.
USB (Universal Serial Bus), IEEE 1394 (Firewire)

relatively low-cost serial interface with high speed.
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Software elements
IBM PC uses BIOS (Basic I/O System) to implement low-level functions:

boot-up minimal device drivers
BIOS has become a generic term for the lowestlevel system software
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Debugging embedded systems
Challenges:
target system may be hard to observe
target may be hard to control may be hard to generate realistic inputs setup sequence may be complex
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Software debuggers
A monitor program residing on the target provides basic debugger functions Debugger should have a minimal footprint in memory User program must be careful not to destroy debugger program, but , should be able to recover from some damage caused by user code
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Breakpoints
A breakpoint allows the user to stop execution, examine system state, and change state Replace the breakpointed instruction with a subroutine call to the monitor program
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ARM breakpoints
0x400 0x404 0x408 0x40c
MUL r4,r6,r6 ADD r2,r2,r4 ADD r0,r0,#1 B loop
0x400 0x404 0x408 0x40c
MUL r4,r6,r6 ADD r2,r2,r4 ADD r0,r0,#1 BL bkpoint
uninstrumented code
code with breakpoint
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Breakpoint handler actions

Save registers Allow user to examine machine Before returning, restore system state
safest way to execute the instruction is to replace
it and execute in place put another breakpoint after the replaced breakpoint to allow restoring the original breakpoint (pp. 222-223)
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In-circuit emulators
A microprocessor in-circuit emulator is a specially-instrumented microprocessor Allows you to stop execution, examine CPU state, modify registers
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Logic analyzers
A logic analyzer is an array of low-grade oscilloscopes:
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Manufacturing testing
Goal: ensure that manufacturing produces defect-free copies of the design Can test by comparing unit being tested to the expected behavior
but running tests is expensive
Maximize confidence while minimizing testing cost
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Testing concepts
Yield: proportion of manufactured systems that work

proper manufacturing maximizes yield proper testing accurately estimates yield
Field return: defective unit that leaves the factory.
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Faults
Manufacturing problems can be caused by many thing Fault model: model that predicts effects of a particular type of fault Fault coverage: proportion of possible faults found by a set of test
having a fault model allows us to determine fault
coverage
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Software vs. hardware testing
When testing code, we have no fault model

we verify the implementation, not the
manufacturing simple tests work well to verify software manufacturing
Hardware requires manufacturing tests in addition to implementation verification
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Hardware fault models
Stuck-at 0/1 fault model:

output of gate is always 0/1
01
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Combinational testing

Every gate can be stuck-at-0, stuck-at-1 Usually test for single stuck-at-faults
one fault at a time multiple faults can mask each other
We can generate a test for a gate by:

controlling the gates input
observing the gates output through other gates
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Sequential testing
A state machine is combinational logic + registers Sequential testing is considerably harder

a single stuck-at fault affects the machine on
every cycle fault behavior on one cycle can be masked by same fault on other cycles
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Scan chains
A scannable register operates in two modes:

normal
scan forms an element in a shift register
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Scan chain cell
Input pin
Scan output
EXTEST INTEST
SEL
MUX
scan
SEL
Input signal to logic
MUX
Shift clock
BSR
Update clock
PDR
Scan input
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Boundary scan
IEEE Std. 1149.1 JTAG boundary scan

Serial data in
Serial data out

Serial test interconnect
66
System interconnect
Embedded ICE
Microprocessor Core
mode external debug clock
address
data
Interface
breakpoint
ICE
Breakpoint Scan Register
BDU
Bypass Register
Select Unit Instruction Register Decode Logic
MUX
TDO
TDI
TMS TCK
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TAP Controller

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Chapter 4: The Embedded Computing Platform

Presenter: Chung-Fu Kao

An alarm clock design

Typical PC hardware platform

How to interconnect microprocessors and devices using the CPU bus

The Embedded Computing System C.-F. Kao

The CPU bus

Wire vs. bus

Bus: a collection of wires with a protocol

The simplest bus protocol is the four-cycle handshake

Typical bus signals

A typical microprocessor bus

clock R/W data rdy address data

A simple transfer example

Transfer with wait states

State diagrams for the bus read transaction

Bus read state diagram

How to speedup the transfer ? Wait

Bus architectures: Tri-state design

1-bit tri-state design data_out data_in

System tri-state bus

Bus architectures: Multiplexing design

AREQx1 AREQx2 AREQx3

Data (W) MUX Address MUX Control MUX

Data (R) MUX

BTRAN[1:0] BA[31:0 BWRITE BSIZE[1:0] BPROT[1:0]

DSEL 1 DSEL 2 DSEL n BWAIT

BLOK BWAIT BnRES/ BCLK

Address bus Data bus Control (write, transfer type, size)

End of Chapter 4.2.1

before I/O operation has completed

Direct Memory Access (DMA)

DMA: Direct Memory Access

The DMA controller includes 3 registers

DMA REQ DMA ACK INTR Read Write

Possible DMA configuration

(a) Single-Bus, Detached DMA

Bus example: ARM bus

ARM supports an on-chip bus: AMBA

Master N Master BIU

APB BUS Interrupt Controller

Multiple bus masters

Bus components devices

Master N Master BIU APB Bridge On-chip RAM Slave BIU

Other APB slaves Slave BIU

Memory device organization

addresses 22 as a 4M x 1-bit array, MAX of 2 different addresses

Random-Access Memories (RAMs)

There are two major categories of RAM:

The differences between SRAM and DRAM

SRAM doesnt need CLOCK signal Block diagram 15

Single transistor and capacitor per bit

write enable Data_in 8

Read-Only Memories (ROMs)

entries width: the number of bits in each addressable entry

Mask ROM Programmable ROM (PROM)

Erasable Programmable ROM (EPROM)

Electrically Erasable Programmable ROM

Timers and counters

Rollover causes interrupt

A/D and D/A converters

Light-emitting diodes (LEDs)

Anode (+) Cathode (-)

Common use: 7-segment LCD display