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Chapter 4 Memory Element
Chapter 4 Memory Element
MEMORY SYSTEM
Main Memory
Functions : Is a memory that hold the instruction and data while program is running for storing data so the CPU/MPU and other direct memory access devices can call up to fetch or store data for processing. It is very much like some part of our brain, that stores short term and long term memory.
RAM vs ROM
RAM Random Access Memory ROM Read Only Memory
Non-volatile type of memory essentially it is a piece of permanently written information stored as memory
ROM is generally slower memory access than RAM
RAM vs ROM
RAM ROM
Because of ROMs ability to store data even when power is removed, it is considered to be non-volatile memory
ROM
Firmware (Program instruction used frequently)
Types of ROM
Read Only Memory (ROM)
Actual ROM chips are programmed when they are made and can never be changed. Program stored in a ROM
Boot time code, BIOS (basic input/output system) graphics cards, disk controllers.
Types of ROM
Erasable programmable ROM (EPROM) Have a transparent window that allows ultraviolet light to penetrate the semiconductor material inside The ultraviolet light gives electrons additional energy allowing them to tunnel through the insulating layers. Thus, the capacitors are discharged. Each cell within the memory chip now represents a binary 1 and the chip can be reprogrammed
Electrically Erasable PROM (EEPROM) Dont need ultraviolet light to erase the contents, only electrical signals
Types of ROM
Electrically Erasable PROM (EAPROM) EEPROM is also known as EAPROM the EA being an abbreviation for Electrically Alterable. The major benefit to EE or EAPROM is that the chips do not have to be removed from the circuit to change their program.
Flash ROM
Also called flash memory A special type of EEPROM that can be erased and reprogrammed in blocks instead of one byte at a time
SRAM vs DRAM
Static RAM Dynamic RAM
SRAM vs DRAM
Static RAM Dynamic RAM
Static RAM is random access memory that retains data bits in its memory as long as power is being supplied
SRAM does not have to be periodically refreshed. Static RAM does not need refreshing because it operates on the principle of moving current that is switched in one of two directions rather than a storage cell that holds a charge in place Static RAM provides faster access to data and is more expensive than DRAM DRAM is dynamic in that, it needs to have its storage cells refreshed or given a new electronic charge every few milliseconds. DRAM stores each bit in a storage cell consisting of a capacitor and a transistor. Capacitors tend to lose their charge rather quickly; thus, the need for recharging
SRAM vs DRAM
Static RAM Dynamic RAM
SRAM is used for a computers cache memory and as part of the random access memory digital-to-analog converter on a video card
Dynamic random access memory (DRAM is the most common kind of random access memory RAM) for personal computers and workstations
SRAM vs DRAM
Static RAM Dynamic RAM
DRAM use MOS capacitors. Because of the capacitive nature of the storage element, dynamic RAMs require less space per chip, per bit, and thus have larger densities DRAM employ MOS capacitors that retain their charges (stored information) for short periods of time
SRAM draw more power per bit Because SRAM must saturate transistors within the flip-flop to retain the stored binary information, and saturated transistors dissipate maximum power
SRAM vs DRAM
Static RAM Dynamic RAM
Disadvantages : 1. From the usage of MOS capacitor as the storage element. Left alone, the capacitor will eventually discharge, thus losing the stored binary information. For this reason the DRAM must constantly refreshed to avoid data loss. During a refresh operation, all of the capacitors within the dynamic DRAM are recharged 2. The refresh operation takes time to complete, and the DRAM is unavailable for use by the processor during this time
SRAM vs DRAM
Static RAM Dynamic RAM
SRAM require no refresh, they are available to the CPU 100 percent of the time
Disadvantages : Older DRAMs required that all storage elements inside the chip ware refreshed every 2 ms. Newer DRAMs have an extended 4ms refresh time, but the overall refresh operation ties up an average of 3 percent of the total available DRAM time, which implies that the CPU only has access to the DRAM 97 percent of the time
SRAM vs DRAM
Static RAM Dynamic RAM
SRAM vs DRAM
SRAM does not need to be refreshed Faster transistors inside would continue to hold the data as long as the power supply is not cut off SRAM modules are also much simpler needs a lot more transistors for every bit of data - 6 Expensive DRAM requires the data to be refreshed periodically in order to retain the data slower and less desirable The additional circuitry and timing needed to introduce the refresh DRAM modules are complicated needs a transistor and a capacitor for every bit of data lower price
memory chip is normally recognized by its memory capacity. Which has 2 main elements : i) Address Size ii) Data Size 32 x 4 4K x 8 2K x 8 (Address Size) (Data Size) memory chip has many pins with specific function of each pin or group of pins : i) Address ii) Data iii) Chip Capacity * 1 Kbyte = 1024 Bits iv) The Control lines/pins - Control R/W - Memory Enable (ME) v) Pins Layout of memory chip
Exercise :
A memory chip with capacity of 5K x 8, determine :
a) numbers of data lines b)numbers of address lines c) capacity in Bits, Byte, Kbyte d) draw the pins layout block diagram
Bus Buffering
Standard buses control bus, data bus, and address bus Why buffer needed? So that many gates can be connected to them instead of the few that can be directly driven by the unbuffered address or data line
Bus Buffering
The output of logic circuits has limited capability of how many next stage circuits it can drive, a.k.a., fanout of the circuit
If the output is overloaded with more circuits than the designed fanout, the circuit may not function properly due to slowing down
Bus Buffering
Buffer the bus signals of CPU using high-current buffer before connecting to external memories E.g., the address bus line of 68000 can only drive 3.2mA current, the output line of a high-current buffer, 74LS244 can drive 24mA current
READ
READ
READ
READ
READ
READ
READ
READ
WRITE
Example
512kWords (1024 kB) of RAM needs to be interfaced to a 68k-based system, The base address is $400000. Design the decoder circuit.
* Controlled by UDS
* Controlled by LDS
log 10 y x log 10 2
2 x 512 ,000
x log10 2 log10 512 ,000
log10 512 ,000 5.7093 x 18 .97 19 log 10 2 0.3010 *Always round to higher.
A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
X X X X X X X X X X X X X X X X X X X
1 4
A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
1
4
0
0
0
0
0
0
0
0
0
0
Replace all dont cares and A0 with ones. This determines the upper limit of the memory chip address.
A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
1 4
A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
1 4
1 F
1 F
1 F
1 F
1 F
A23
A23 A22 A21 A20
A22
1 4
A21
A20 AS
NAND
CS
Actual Implementation
EVEN ODD
A1 A19
D8 D15
A1 A19
CS E
WE
WE CS
MAD
A23 A22 A21 A20 AS
NAND
UDS CS
R/W
LDS
D0 D7
512kB RAM
512kB RAM
$400000 $4FFFFF
unused $FFFFFF
2kB ROM
2kB ROM
AS
MAD
UDS SELRAM CS A1 A11 E D8 D15 A1 A11 CS E LDS
*Not all address lines used: A12 for MAD A1 A11 for addressing
2kB RAM
2kB RAM
MAD circuit
More complex circuit, since need to use all address lines. When the M68k system is large and requires a lot of memory. Easy to upgrade, extra memory can be added with little modifications to original decoder.
When to use
Upgrade
Step 1 : Identify how many chips we need to address and the capacity of each chip. For instance .....
PROM-1
PROM-2 PROM-3
0800
1000 1800
0FFF
17FF 1FFF
Step 2 : Determine the chip Address Range. As shown in the memory mapping section, for the fixed data size of 8 bits, each chip (same capacity) has the same location size of : 2K = = = 2 x 1024 204810 80016
PROM-0 PROM-1
PROM-2
PROM-3
A12 0 0 0 0 1 1 1 1
A11 0 0 1 1 0 0 1 1
A10 0 1 0 1 0 1 0 1
A9 0 1 0 1 0 1 0 1
A8 0 1 0 1 0 1 0 1
A7 0 1 0 1 0 1 0 1
A6 0 1 0 1 0 1 0 1
A5 0 1 0 1 0 1 0 1
A4 0 1 0 1 0 1 0 1
A3 0 1 0 1 0 1 0 1
A2 0 1 0 1 0 1 0 1
A1 0 1 0 1 0 1 0 1
A0 0 1 0 1 0 1 0 1
Step 4 cont :
From the above table : (a) Since all chip has similar START / END address bits for address lines : A10 A0; Thus A10 A0 are the common lines to all chips. (b) Address line that changes : A12 A11 To simplify the above table, We group the common lines in hex digit instead of bits. Two LSD are common, Whereas the two MSD will distracted into bits. The simplified table will be as follows :
PROM-0 PROM-1 PROM-2 PROM-3 0000 07FF 0800 0FFF 1000 17FF 1800 1FFF A12 0 0 0 0 1 1 1 1 A11 0 0 1 1 0 0 1 1 A10 0 1 0 1 0 1 0 1 A9 0 1 0 1 0 1 0 1 A8 0 1 0 1 0 1 0 1 A7 A0 00 FF 00 FF 00 FF 00 FF
0 A12 A11
o o
C B A
0 1 2 74LS138 3 4 5 6 7
o o
PROM 0 : 0000H 07FFH PROM 1 : 0800H 0FFFH PROM 2 : 1000H 07FFH PROM 3 : 1800H 18FFH
o
o o o o o
EXERCISE
Memory Chip PROM 0 PROM 1 PROM 2 PROM 3 Capacity of Chip 2K x 8 6K x 8 4K x 8 8K x 8