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Trailokya Nath
Trailokya Nath
OUTLINE
.
Educational background
. A glimpse of the research carried out during MTECH programme . Area of interest during PHD . Teaching subjects . Long term goals
EDUCATION
Indian Institute Technology,BHU,Varanasi,India Master of Technology (M.Tech), CGPA: 8.4/10 (Honours)
Specialization DTI (Digital Techniques & Instrumentation), July 2011. Krupajala Engineering College, Bhubaneswar, B.P.U.T, Orissa, India Bachelor of Engineering (B.Tech), Aggregate: 79.4% (Honours)
WORK EXPERIENCE
Currently working as Asst.Prof in Electronics & Comm. Dept. at NIT kurukshetra,Haryana since June 2012. Worked as Asst.Prof in Electronics & Comm. Dept. at Mewar University, Chittorgarh during June 2011 to June 2012. Conducted Lab sessions of Fault tolerance Design course (1st year M.Tech) under the guidance of Prof. Anand Mohan, IIT,BHU, Summer 2009-10. Conducted Lab sessions of Embedded System Design course (2nd year M.Tech) under the guidance of Prof. Anand Mohan, IIT,BHU, Winter 2010-11. Worked as a Visiting Faculty at IETE, Varanasi during February '11 to May '11.
Fault Diagnosis of Comparator Module & Global structure of the proposed scheme
FAULT CONSIDERED
Single event effects
Single Event Transient(SET)
Single Event Upset(SEU)
SET latched in a
sequential logic unit considered an SEU
Number of neutrons that pass through each square centimeter of surface every second (the neutron flux)
vol. 40, No. 2, pp 120
cumulative number of memory upsets after a given number of hours in the air.
Data were taken from a research paper by Taber and Normand (1993), and published in the IEEE Transactions on Nuclear Science,
Digital designs synthesized in SRAM-based FPGAs are sensitive to upsets in the FPGA customization cells.
Design
E1 E2 E1 E3 E2 E3
clk
E1 E2 E1 E3 E2 E3
Upset = bit-flip
clk
fault
M M M M
10101011100001101010
Fault injection
validation technique of the Dependability of Fault Tolerant Systems Fault injection techniques classified in three main categories: .Hardware implemented fault injection . Software implemented fault injection . Simulated fault injection By loading an incorrect partial bitstream to the FPGA First method directly modifies a correct partial bitstream second method modifies the source VHDL file then synthesized to provide a faulty bitstream.
change the model by adding saboteurs or using mutants of the model components
Fault type
Stuck-at 0 Stuck-at 1 Bit-flip Open-line
Mutants:
A component which replaces another component. While inactive, it works like the original component, but when activated, it behaves like the component in presence of faults. It is relatively easy to implement this replacement technique by using the VHDL configuration mechanism .
Bitstream Modification
Percentage of time a fault is inserted in the system per the No. of bits matched
A survivable system is one that continues to perform identified set of critical functions under operationally threatening conditions.
cosmic radiations, lightening, global system faults like power supply and clock failures etc. Survivable systems differ from fault tolerant system in respect of continuance of critical functionality. systems are being implemented on (FPGAs) due to hardware reconfigurability and low implementation cost. Environment subject to high radiation, Particles cause portions of the reprogrammable circuitry to change states.
SURVIVABLE DESIGN
System Design Incorporating Survivability Attributes for capability of a system to complete its missions in a timely manner, in the face of adverse conditions
Survivability
Value
time
Teaching subjects