LISA-Machine Description Language and Generic Machine Model for SW/HW Co- Design

-Vojn Zivojnovic Stefen Pees Heinrich Meyr

Introduction
L-chart Instruction Set Architecture Language(LISA) Improved work over HDL (Verilog,VHDL) and Machine Model Languages( Ptolemy,PIXIE,Sable, MARIL,VLIW ) Generic machine model to cover difference between standard ISA Models and description languages.

Advantages of LISA
Abstract Reduce Complexity Improve runtime over other HDL and Machine Model Languages Common solution for Processor Architecture

Characteristics of LISA

Application Domain:
Real time Software design ( Word Length analysis, memory optimization, Speed, DSP/Embedded system ,HW/SW co verification, architecture explorations)

Processor Class:
DSP and micro controllers of low or medium complexity with pipeline and RISC processors

Model Accuracy:
Selectable instructions, clock/phase accurate timing,bit accurate register transfer, exact pipeline with wait and interrupts

State visibility:
Complete state visibility at selected control steps

Operation Sequencer:
Partitioned into basic scheduled units Transition function Ft change machine state Transition take place in control step at t Precedence and Resource constraint determine next function

Operation Sequencing
Reservation Table Two dimensional representation of resource allocation in the resource time A mark in a table indicating corresponding Processor resource etc. bus,functional units Gantt chart-Uniquely specify operations Instruction scheduling Reservation table give details Clock accurately model Covert Time axis into precedence axis

Gannts Chart Sequencing&LISA Style

01 (R1) | 02(R2) | 03(R3) | 04(R4),05(R5) | 06(R6)

Vertical Lines : Precedence Commas: Parallelism Parenthesized: Resources

Gannts Concept for Hazards

Data & Control Hazard

Access storage has to specified for Read or Write Access storage has to be acknowledged before operation Hazard: IF | ID (!w=R0) | IA | IE(w=R0)| %Inst set #1 IF | ID(r=R0)| IA | IE %Inst set #2 Solution IF | ID(!w=R0)|IA |IE(w=R0) | IF | NOP | NOP | ID(ro=R0) | IE

Continued

Stall (wait state by memory or cache)

Resource Reservation for external events

Flushing (permits)
Descriptor of Operation k:03

Dynamic scheduling to avoid Hazard

Rearrange instructions set

Example: LISA description of TMS320C54X

Kill descriptor for {BC ADD,LD}

Conclusion:

LISA enable fast and comfortable solution for embedded & processors Supports design, verification and co design environments L-charts supports data hazards and pipeline flushing,interlocking bypassing Model use ASAP to obey Time & Resource Constraints