Operation amplifier

Symbol
Example
Characteristics
Structure
Operation
Applications

p 741
Symbol
Example
Characteristics
Characters of circuits depend on outside circuit
structure, not the opamp itself
Gain A
V
: very high, ideally
Zin: very large, ideally
Zout: very small, ideally 0
Current entering the amp at either terminal:
extremely small, ideally 0
Voltage out (when voltages into each other are
equal): small, ideally 0
Bandwidth: broad, ideally infinite
Characteristics
Input: 2 inputs (positive and negative)
Single-ended input: 1 input to signal source, 1 input to
ground
Double-ended input: 2 different signal sources or 1 signal
source apply between 2 inputs
Output: 1 or 2 outputs, typically 1 output
Mode gain:
Differential-mode gain A
dm
- large

Common-mode gain A
cm
- small

Common-mode rejection ratio CMRR=G=A
dm
/A
cm
, usually
about 10
3
-10
5
Structure
Requirement:
Gain: large
Offset: small
Currents: small
Input impedance: large
Output impedance: small
Input: symmetric
Structure
Input stage
Intermediate stage
Level shifting stage
Output stage

Example: 741 at the end of chapter

Applications
Basic and advance applications
Basic applications:
Inverting, non-inverting amplifier
Uni-gain circuit
Addition and subtraction circuits
Integration and differential circuits
Multi-stages circuit
Applications
Advance applications
Current-controlled voltage source
Voltage-controlled current source
DC voltmeter
AC voltmeter
Driver circuit
Active filters
NIC
.etc.
Non-inverting fixed-gain amplifier
Prove:
V- = V+ = V
1

I- = I+ = 0
=>I
R1
= I
rf
= V
1
/R
1
=>A = 1+R
f
/R
1


Non-inverting fixed-gain amplifier
A = 1+R
f
/R
1
=101
V
o
=101V
i
Inverting fixed-gain amplifier
Prove:
V- = V+ = 0
I- = I+ = 0
=>I
R1
= I
rf
= V
1
/R
1
=>A = -R
f
/R
1


Voltage addition

V
o
= -V
1
R
f
/R
1
-V
2
R
f
/R
2

V
3
R
f
/R
3

If V
1
=V
2
=V
3
then:
A= -R
f
/R
1
-R
f
/R
2
R
f
/R
3
Voltage subtraction
V
out1
= -R
f
/R
1
V
1

V
out
= -R
f
/R
2
V
2
- R
f
/R
2
V
out1
= -R
f
/R
2
V
2
+ R
f
/R
2
V
1
= -R
f
/R
2
(V
1

V
2
)
Voltage subtraction with 1 amp
Prove:
V-=V+=V
1
*R
3
/(R
1
+R
3
)
I- = I+ = 0
=>I
R2
= I
R4
= (V
2
-
V
1
*R
3
/(R
1
+R
3
))/R
2
=>Vo=V
1
*R
3
/(R
1
+R
3
)*
(R
2
+R
4
)/R
2
V
2
*R
4
/R
2


Uni-gain (buffer) amplifier
Provide required input and output resistant stage
Provide multiple identical output signals
Voltage-controlled voltage source
V
o
=(-R
f
/R
1
)V
1
V
o
=(1+R
f
/R
1
)V
1
Voltage-controlled current source
I
o
=V
1
/R
1
Current-controlled voltage source
V
o
=-I
1
R
L
Current-controlled current source
I
o
=I
1
(R
2
+R
1
)/R
2
Integration circuit
V
o
=(V
i
/RC)
0

T
V
i
(t)dt+V
o
ut(t=0)
Differential circuit
V
o
=-RC dV
i
/dt
Filter
Low pass filter
High pass filter
Band pass filter
1
st
order low pass filter
Cutoff frequency: f
OH
=1/(2R
1
C
1
)
Voltage gain below cutoff freq: A
v
=1+R
f
/R
G
2
nd
order low pass filter
Cutoff frequency: f
OH
=1/(2R
1
C
1
)
Voltage gain below cutoff freq: A
v
=1+R
f
/R
G
1
st
and 2
nd
order high pass
filter
Cutoff frequency: f
OL
=1/(2R
1
C
1
)
Voltage gain above cutoff freq: A
v
=1+R
f
/R
G
Band pass filter
Multi-stages gain
A = A
1
*A
2
*A
3

741 application-Light activated alerter
12V battery monitor
Homework
Chapter 14: 1, 4, 9, 10, 12, 15, 17, 18
Chapter 15: 1, 6, 8, 11, 14, 16, 17
OpAmp 741
Maximum ratings
Inside structure
Maximum ratings
OpAmp 741 inside structure
Biasing Currents
Input Stage
Second Stage
Output Stage
Short Circuit Protection
Inside structure: Schematic
Q2
Q19
Vo
R11
50k
Q21
Q12
R10
40k
Q10
R9
50k
Q5
H
I
R8
100
Cc
30p
Q6
R5
39k
Q13a
Q9
R2
1k
Q1
R3
50k
R7
27k
Q16
Q14
Q20
Q8
Q13b
Q23 Q3
Vin+
Q22
Q24
Q15
R1
1k
Q7
Q17
Q18
L
O
Q4
R6
27k
Vin-
R4
5k
Q11
Biasing Current Sources
Generates reference
bias current through R
5
The opAmp reference
current is:
I
ref
=[V
CC
-V
EB12
-V
BE11
-(-V
EE
)]/R
5
For V
CC
=V
EE
=15V and
V
BE11
=V
BE12
=0.7V, we
have I
REF
=0.73mA
Q10
Q9
Q12
R5
39k
R4
5k
Q11
Q8
Input Stage
The differential pair,
Q1 and Q2 provide
the main input
Transistors Q5-Q7
provide an active
load for the input
Q6
Q3
Q1
Q7
Q5
R1
1k
Vin- Vin+
Q4
R3
50k
R2
1k
Q2
Input Stage:
DC Analysis - 1
Assuming that Q10 and Q11 are matched,
we can write the equation from the Widlar
current source:
V
T
ln
I
REF
I
C10
|

\
|
|
.
I
C10
R
4

Using trial and error, we can solve for

I
C10
, and we get: I
C10
=19A
Input Stage: DC Analysis -2
From symmetry
we see that
I
C1
=I
C2
=I, and if
the npn | is large,
then I
E3
=I
E4
=I

Analysis
continues:

Input Stage: DC Analysis -3
Analysis of the active load:
Second (Intermediate) Stage
Transistor Q16 acts as
an emitter-follower
giving this stage a high
input resistance
Capacitor Cc provides
frequency
compensation using the
Miller compensation
technique
Q13b
R9
50k
Q13a
Q16
Q17
Cc
30p
R8
100
Second Stage:
DC Analysis
Neglecting the base current of Q23, I
C17
is
equal to the current supplied by Q13b
I
C13b
=0.75I
REF
where |
P
>> 1
Thus: I
C13b
=550uA=I
C17
Then we can also write:
V
BE17
V
T
ln
I
C17
I
S
|

\
|
|
.
618mV
I
C16
I
E16
I
B17
I
E17
R
8
V
BE17
+
R
9
+ 16.2A
Output Stage
Provides the
opAmp with a low
output resistance
Class AB output
stage provides
fairly high current
load capabilities
without hindering
power dissipation
in the IC
Q15
Q18
Q23
Q21
Q14
Vo
Q19
R7
27k
R6
27k
Q20
R10
40k
Output Stage:
DC Analysis
Q13a delivers a current of 0.25I
REF
, so we
can say: I
C23
=I
E23
=0.25I
REF
=180A
Assuming V
BE18
= 0.6V, then I
R10
=15A,
I
E18
=180-15=165A and I
C18
=I
E18
=165A
I
C19
=I
E19
=I
B18
+I
R10
=15.8A
Short Circuit Protection
These transistors are normally off
They only conduct in the event that a large current is drawn
from the output terminal (i.e. a short circuit)
R11
50k
Q24
Q22