AN EFFICIENT VLSI ARCHITECTURE FOR LOW POWER MSIC TPG

Guided by K.Malarvizhi M.E., Assistant Professor , (ECE Dept). Presented by S.Velkani Reg.No:951012401016 II-M.E/Applied Electronics

Introduction
Test pattern generator (TPG) for built-in selftest. We cant able to check the circuit manually, so we are going for BIST. In previous methods, switching activity is high It consumes more power. In this project switching activity is reduced, so power consumption is low and achieve target fault coverage.

OBJECTIVE

Design of Test pattern generator (TPG) for builtin self-test. This method generates multiple single input change vector using Johnson counter and a scalable SIC counter with target fault coverage.

LITERATURE SURVEY
1.DS-LFSR: A BIST TPG for Low Switching Activity

A test pattern generator (TPG) for built-in self-test (BIST), to reduce switching activity. It consists of two linear feedback shift registers (LFSRs), a slow LFSR and a normal-speed LFSR.
DISADVANTAGES: Area overhead because of two LFSRs

2.LT-RTPG: A New Test-Per-Scan BIST TPG for Low Switching Activity

LT-RTPG is composed of a linear feedback shift register (LFSR), a -input AND gate, and a T flipflop. Switching activity is reduced by decreases the number of transitions that occur during scan shifting DISADVANTAGES: There may be some undetected errors.

3.3-Bit-Swapping LFSR Bit-swapping LFSR (BS-LFSR), is composed of an LFSR and a 2 1 multiplexer. It reduces the number of transitions that occur at the scan-chain input during scan shift operation by 50% compared to conventional LFSR. DISADVANTAGES: Area overhead

4.Low power BIST

The proposed BIST is comprised of two TPGs: an LTRTPG and a 3-weight WRBIST. The multiplexer drives the input of scan chain, selects a test pattern source between the LT-RTPG and the 3weight WRBIST.

DISADVANTAGES Little area overhead.

Proposed method

To design an MSIC TPG (Multiple Single Input Change Test Pattern Generator) using Johnson counter and SIC counter. Testing done in two condition Test per clock scheme Test per scan scheme .

TEST PER CLOCK SCHEME BLOCK DIAGRAM

CLK2 JOHNSON COUNTER

CUT CLOCK AND CONTROL CIRCUIT XOR OPERATION

CLK1

SEED GENERATOR

1) The seed generator generates a new seed by clocking CLK1 one time. 2) The Johnson counter generates a new vector by clocking CLK2 one time. 3) Repeat 2 until 2l Johnson vectors are generated. 4) Repeat 13 until the expected fault coverage or test length is achieved.

Reconfigurable Johnson counter

1)

Initialization: When RJ_Mode=1 and Init=0, the reconfigurable Johnson counter will be initialized to all zero .

2)Circular shift register mode: When RJ_Mode=1 and Init=1 each stage of the Johnson counter generate a L l Johnson codeword.

3) Normal mode: When RJ_Mode=0, the reconfigurable Johnson counter will generate 2l unique SIC vectors.

Truth Table
TRUTH TABLE

State

Q0

Q1

Q2

Scalable SIC Counter

When the maximal scan chain length l is much larger than the scan chain number M, SIC counter is used

1) SE = 0, the count from the adder is stored to the k-bit sub tractor. 2) If SE = 1 then the content in k-bit sub tractor are decrease towards 0.

TEST PER SCAN SCHEME

JOHNSON COUNTER

SCANCHAIN1

CLOCK AND CONTROL CIRCUIT

XOR OPERATION

SCANCHAIN2

MISR (Multiple Input Signature Register)

SCANCHAINN

SEED GENERATOR COMBINATION AL LOGIC

The inputs of the XOR gates come from the seed generator and the SIC counter, and their outputs are applied to M scan chain. The test vector are applied to the CUTs . The test procedure is as follows.

ADVANTAGES Minimum transitions Uniqueness of patterns Uniform distribution of patterns

Low hardware overhead

SIMULATION OUTPUT
Johnson counter

SIC COUNTER

TEST PER CLOCK

Area analysis:

Device Utilization Summary (estimated values) Logic Utilization Used Available Utilization

[-]

Number of Slices
Number of Slice Flip Flops Number of 4 input LUTs Number of bonded IOBs Number of GCLKs

41
17 66 66 2

960
1920 1920 66 24

4%
0% 3% 100% 8%

Conclusion & future enhancement

TPG was designed using Johnson counter and SIC counter to generate a minimum transition sequences. SIC vector are applied as a test vector to detect the fault in the testing circuit. Thus fault are detected in the circuit and achieve target fault coverage with low power and area. In future Enhancement, The k bit adder, k bit subtract or type is not mentioned in the SIC counter, so we can use the area efficient carry select adder, which one is power efficient.

REFERENCES
1,Test Patterns of Multiple SIC Vectors: Theory and Application in BIST Schemes 2,Y. Zorian, A distributed BIST control scheme for complex VLSI devices, in 11th Annu. IEEE VLSI Test Symp. Dig. Papers, Apr. 1993, pp. 49. 3,P. Girard, Survey of low-power testing of VLSI circuits, IEEE Design Test Comput., vol. 19, no. 3, pp. 8090, MayJun. 2002. 4,A. Abu-Issa and S. Quigley, Bit-swapping LFSR and scan-chain ordering: A novel technique for peak- and average-power reduction in scan-based BIST, IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 28, no. 5, pp. 755759, May 2009. 5, P. Girard, L. Guiller, C. Landrault, S. Pravossoudovitch, J. Figueras, S. Manich, P. Teixeira, and M. Santos, Low-energy BIST design:Impact of the LFSR TPG parameters on the weighted switching activity,in Proc. IEEE Int. Symp. Circuits Syst., vol. 1. Jul. 1999, pp.110113.