1

Super Buffer Design

Driving Large Capacitive Loads


prepared
by
Mr. KOTHANDAPANI R
ME-VLSI DESIGN






Given a large capacitance load C
load
How many stages are needed to minimize the delay?
How to size the inverters?
2
Supper Buffer
C
load
o
1
o
2
o
N
1

C
g
C
d oC
g
o
2
C
g
oC
d
o
2
C
d
o
N
C
g o
N
C
d
C
load
Equiv INV

N: number of inverter stages
o: optimal stage scale factor

where
C
g
: the input capacitance of the first stage inverter.
C
d
: the drain capacitance of the first stage inverter.
Each inverter is scaled up by a factor of o per stage.
C
load
= o
N+1
C
g

All inverters have identical delay of
t
0
(C
d
+oC
g
)/(C
d
+C
g
) which t
0
is per gate delay for
Equiv INV in ring oscillator circuit with load
capacitance = C
g
+C
d
3




Consider N stages, each inverter has same delay
t
0
(C
d
+oC
g
)/(C
d
+C
g
).
Therefore,


( )
|
|
.
|

\
|
+
+
+ =
C C
C C
N
g d
g d
total
o
t t 0
1
4
o
1
o
2
o
N
1

C
g
C
d oC
g
o
2
C
g
oC
d
o
2
C
d
o
N
C
g o
N
C
d
C
load
Equiv INV

t
d
t
d
t
d
t
d
Goal: Choose o and N to minimize t
total.

By C
load
= o
N+1
C
g,
we have


Plug the above equation into t
total
, we get



To minimize t
total
:
|
|
.
|

\
|
+
+
|
|
.
|

\
|
=
C
C
C C
C
C
d g
g d
g
load
total
o
t
o
t 0
ln
ln
( )
o ln
ln
1
|
|
.
|

\
|
= +
C
C
N
g
load
5
( )
0
ln
1
ln
1
ln
2
0
=
(
(
(

|
|
.
|

\
|
+
+
|
|
.
|

\
|
+
+

|
|
.
|

\
|
=
c
c
C
C
C
C
C
C C
C
C
d g
g
d g
g d
g
load total
o
o
o
o
t
o
t
( )
C
C
g
d
opt opt
= 1
ln o o
For the special case C
d
=0 ln(o
opt
)=0 o
opt
= e. However, in
reality the drain parasitics cannot be ignored.
Example: For C
d
=0.5 fF, C
g
=1 fF, determine o
opt
and N for C
load
=
50 pF.
o
opt
(ln o
opt
-1) = 0.5 o
opt
= 3.18






The Super Buffer Design which minimizes t
total
for C
load
= 50 pF is
N=7 Equiv INV stages, and o
opt
= 3.18
( )
( ) | |
( ) | |
36 . 6
1 18 . 3 ln /
10 1
/
10 50
ln
1
ln
/ / ln
ln
/ ln
1
14 12
=


=
=
= +

o
o
opt g load
opt
g load
C C
N
C C
N
6
Oscillation period T is equal to
T=t
PHL1
+t
PLH1
+t
PHL2
+t
PLH2
+t
PHL3
+t
PLL3

=2t
p
+2t
p
+2t
p

=32t
p
=6t
p
For arbitrary odd number (n) of cascade-connected
invertes, we have
f=1/T=1/(2nt
p
)
Also, we can write
t
p
=1/(2nf )
7
V
1
C
load,1
C
load,2
C
load,3
V
2
V
3
1

2

3

8

PHL2
V
out
V
OH
V
50%
t

V
OL

PLH3

PHL1

PLH2

PHL3

PLH1
V
2
V
1
V
3
V
2
V
1
V
3
T

9
Figure 8.8 CMOS inverter circuit
High speed design can be obtain from
studying the characteristic delay through
inverter
n p
L
W
r
L
W
|
.
|

\
|
= |
.
|

\
|
1
'
'
> = =
p
n
p
n
k
k
r

) (
1
T DD
p n
V V
R R R

= = =
|
] 1 [ ) (
/ t t
DD out
e V t V

=
t /
) (
t
DD out
e V t V

=
) (
L FET out
C C R RC + = = t
L s
C t t o + =
0
) (
1
T DD
V V
R

=
|
o
) (
Gp Gn ox
Gp Gn in
A A C
C C C
+ =
+ =
Gn
n ox
p n ox in
C r
LW C r
W W L C C
) 1 (
) )( 1 (
) (
+ =
+ =
+ =
) 2 / (
DD M
V V =
(8.42)
(8.43)
(8.44)
(8.50) (8.45)
(8.48)
(8.49)
(8.46)
(8.47)
(8.51)
(p-network pre-charge function)
(n-network dis-charge function)
(assume t
s
= t
r
= t
f
)
10
Figure 8.9, since the load capacitance is the same
as the gates own input capacitance , we call this a
unit load value
in L
C C =
1
in s
C t t o + =
0 1
| | S = '
S
R
R = '
S
o
o = '
L s
C
S
t t
|
.
|

\
|
+ =
o
0
n n
SW W = '
in in
SC C = '
(unit load) (8.52)
(switching time)
(When C
L
>> C
in
, using S > 1)
(new switching time)
(8.53)
(8.54)
(8.55)
(8.52)
(8.53)
(8.54)
(8.55)
(When C
L
=S C
in
, using S > 1)
Figure 8.9 Concept of a unit load
Figure 8.10 Driving a large
input capacitance gate
11
In figure 8.11. To drive the large load capacitance,
let the 1-th be the unit gate

Figure 8.11 Inverter chain
analysis
N N
| | | | | < < < < <
1 3 2 1
...
1 2
| | S =
2 3
| | S =
j j
S| | =
+1
1 2
| | S =
1
2
2 3
| | | S S = =
1
3
3 4
| | | S = =
1
) 1 (
| |

=
j
j
S
1
) 1 (
C S C
j
j

=
) 1 (
=
j
j
S
R
R
1 +
=
j j j
C R t
Figure 8.12 Characteristics of a
typical stage in the chain
(8.60)
(8.61)
(8.62)
(8.63)
(8.64)
(8.65)
(8.66)
(8.67)
ce tan c transcondu device
ce tan resis FET R
e tanc capaci input C
=
=
=
1
1
1
|
(1-th stage parameters)
(assume C
j+1
>> C
FET,j
)
12
L N N N
N N d
C R R R C R C R C R + + + + + =
+ + + + + =

1 4 3 3 2 2 1
1 3 2 1
...
... t t t t t t
1
1
C S
C C
N
N L
=
=
+
1
1
1
1
1
2
1
1
3
2
1
1
2 1
1 1
... C S
S
R
C S
S
R
C S
S
R
C S
S
R
SC R
N
N
N
N
d

+ + + + + = t
) (
...
1 1
1 1 1 1 1 1 1 1 1 1
C SR N
C SR C SR C SR C SR C SR
d
=
+ + + + + = t
r d
NSt t =
1
C S C
N
L
=
) ln( ln ) ln(
1
S N
C
C
S
L N
=
|
|
.
|

\
|
=
) ln(
ln
1
S
C
C
N
L
|
|
.
|

\
|
=
(

|
|
.
|

\
|
=
) ln(
ln
1
S
S
C
C
L
r d
t t
0
) ln(
=
(

c
c
=
c
c
S
S
S S
d
t
1 ) ln( = S or
e S =
|
|
.
|

\
|
=
|
|
.
|

\
|
=
1
1
ln
) ln(
ln
C
C
S
C
C
N
L
L
r
L
d
C
C
e t t
|
|
.
|

\
|
=
1
ln
Figure 8.13 Time constants in the cascade
(8.68)
(8.69)
(8.70)
(8.71)
(8.72)
(8.73)
(8.74)
(8.75)
(8.77)
(8.78)
(8.79)
(8.80)
(8.81)
(8.76)
(8.82)
(N stages)
1 1
, C R where
r
= t
0
)] [ln( ) ln(
1
2
=
S S
S
S
(e = 2.71)
13
Figure 8.14 shows the j-th stage circuit with the parasitic FET
capacitance C
Fj
included at the output S > e (in physical design)
Figure 8.14 Driver chain with
internal FET capacitance
) (
1 , +
+ =
j j F j j
C C R t
1 ,
) 1 (
, F
j
j F
C S C

=
) ( ... ) ( ) (
, 3 2 , 2 2 1 , 1 L N F N F F d
C C R C C R C C R + + + + + + = t
) (
1 1 1 , 1
C SR N C NR
F d
+ = t
|
|
.
|

\
|
(

|
|
.
|

\
|
+ =
1
ln
) ln( ) ln( C
C
S
S
S
L
r
x
d
t
t
t
1 , 1 F x
C R where = t
| |
r
x
S S
t
t
= 1 ) ln(
(8.68)
(8.69)
(8.70)
(8.71)
(8.72)
(8.73)
(8.74)
14