Inverter Mode of Operation

The circuit behaves as rectifier for < /2

where V
do
>0

And as a line-commutated inverter for > /2
where V
do
< 0

The circuits will work as inverter when we
connect a dc voltage source E
S
of proper
magnitude and polarity across their terminals
as shown on the next slide



Inverter Mode of Operation Contd




Inverter Mode of Operation contd
The dc source may be

a battery,
a photovoltaic source,
a dc voltage produced by a wind-electric
system or
a dc motor operating under overhauling
load conditions (a load that turns the
armature).



Load and SCR T
1
voltage waveforms for
continuous conduction current and with the
effect of the source inductance included are
shown on the next slide

v
T1
=v
s
when T
3
is conducting and T
1
is off.
v
T1
=0 so long as T
1
is conducting

The figure shows that the thyristor voltage v
T1

is negative during the extinction angle given
by
= 180 ( + )


.










The extinction angle must be great enough
to allow the thyristors to turn off and regain
their forward blocking capability before
forward voltage is reapplied, i.e.
> t
q

The two equations:
= 180 ( + ) and
> t
q

place a ceiling on the delay angle:
= 180 ( + ) > t
q



Its maximum value is, in practice,

max
= 180 -

If the > t
q
condition is not satisfied, the
commutation process will fail and then
destructive currents will occur.

Typical value of
max
is 165
o
.



Three-phase fully controlled bridge
converter (6-pulse)

The figure on the next slide shows the
converter with highly inductive load.

It is the most widely used line-commutated
thyristor rectifier.





.





The converter also uses two groups of SCRs:

T
1
, T
3
and T
5
in one group have common
cathode connection and
T
2
, T
4
and T
6
in the other group have a
common anode connection.

The two groups operate independently of
each other.




Here again if the gate currents to the SCRs
were applied continuously, then they would
behave like diodes

And for the common cathode connection, the
SCR with its anode at the highest potential
would conduct

And for the common anode connection, the
SCR with its cathode at the lowest potential
would conduct.


Let
v
an
= V
max
sint
v
bn
= V
max
sin(t 120
o
)
v
cn
= V
max
sin(t + 120
o
)

If they were diodes, which of them would be
conducting at t = 60
o
?

Note that at t = 60
o

v
an
>0, v
bn
<0 and v
cn
=0



The SCRs are fired in the following sequence
at time interval of 2/6 (i.e. the period
divided by 6): T
1
, T
2
, T
3
, T
4
, T
5
and T
6
.

In the case of discontinuous current flow, it is
possible for T
2
say to have stopped
conducting before T
3
is turned on.

Then it is necessary to apply a gate pulse
simultaneously to T
2
and T
3
when T
3
is being
turned on.




This problem is solved by double pulsing,
i.e., supplying two pulses per cycle spaced
60
o
or 2/6 apart to each SCR.

That is the SCRs are fired in the following
sequence:

(T
6
T
1
), (T
1
T
2
), (T
2
T
3
), (T
3
T
4
), (T
4
T
5
) ,
(T
5
T
6
), (T
6
T
1
),



Alternatively a long pulse, greater than 60
o
,
will overcome the problem, especially when
supplying an inductive load.

It is difficult to produce long pulses. So
usually a train of pulses with a frequency of
about 10 kHz is used to simulate a long pulse,
typically 120
o



Converter Feeding Highly Inductive load
The dc output voltage is given by
v
d
= v
Pn
v
Nn

The voltage v
Pn
= v
an
when T
1
is conducting,
= v
bn
when T
3
is conducting and = v
cn
when
T
5
is conducting.

Similarly v
Nn
= v
an
when T
4
is conducting, =
v
bn
when T
6
is conducting and = v
cn
when T
2

is conducting.





Line voltage v
ab

(T
6
and T
1
)





Line voltage v
ac

(T
1
and T
2
)





Line voltage v
bc

(T
2
and T
3
)





Line voltage v
ba

(T
3
and T
4
)





Line voltage v
ca

(T
4
and T
5
)





Line voltage v
cb

(T
5
and T
6
)


Converter waveforms are shown on the next
slide
The instants at which the SCRs would
naturally start conducting if they were diodes
are indicated in (a)
The effect of the phase angle on the
converter waveforms is shown in (b) to (d).

The current in phase a is shown in (c).
The line-to-line ac voltages and the dc output
voltage, are shown in (d).


















Output voltage
The output voltage has 6 pulses.
The mean output voltage is given by





where V
max
is the peak of the phase voltage
and V
LL
is the rms value of the line voltage.
u t u
t
e
t
o
t
o
t
o
t
o
t
d V t d v V
ab do
) 6 sin( 3
3
) (
3
max
2
6
2
6
+ = =
} }
+
+
+
+


o
t
o
t
cos
2 3
cos
3 3
max LL
V V
= =



Output voltage contd
In the time interval used for the integration
T
1
and T
6
are conducting resulting in
v
d
= v
an
v
bn
= v
ab

[we start at when T
1
starts conducting (30
o

+) and end at when T
2
starts conducting
(60
o
+30
o
+ = 90
o
+ ). Since T
2
takes over
from T
6
, it is T
6
that conducts in the
interval].
The expression for v
ab
is obtained using
phasor diagram


Output voltage contd
For delay angles up to /3, the output
voltage is at all instants non-zero; hence
load current is continuous for any
passive load.

Beyond /3 the load current may be
discontinuous.





Output voltage contd
The rms value of the output voltage is
given by



2
1
2
6
2 2
max
) ( ) 6 ( sin 3
3
(
(
(

+ =
}
+
+
t d t V V
rms
e t e
t
o
t
o
t


2
1
max
2 cos
4
3 3
2
1
3
|
|
.
|

\
|
+ = o
t
V



Input line currents
The input currents i
a
, i
b
and i
c
have
rectangular waveforms with amplitude I
d
.

The waveform of i
a
is phase shifted from v
an

by the delay angle .

It can be expressed in terms of its Fourier
components with t defined to be zero at the
positive zero crossing of v
an
as given on the
next slide
o





where the peak of the fundamental component
is given by

and the peak of the harmonics


Only nontriplen odd harmonics are present



o
)] ( 19 sin[ )] ( 17 sin[
)] ( 13 sin[ )] ( 11 sin[
)] ( 7 sin[ )] ( 5 sin[ ) sin( ) (
19 17
13 11
7 5 1
o e o e
o e o e
o e o e o e e

+ +
=
t I t I
t I t I
t I t I t I t i
m m
m m
m m m a

t
d
m
I
I
3 2
1
=
h
I
I
m
mh
1
=
where
1 6 = k h


From the waveform of i
a
, the rms value of the
input current can be shown from the basic
definition of rms to be


Alternatively, we may use the fact that
i
a
= i
T1
i
T4
from which


And hence



o
d S
I I
3
2
=

) ( ) ( ) (
2
4
2
1
2
RMS I RMS I RMS I
T T a
+ =
d d s
I I I ) 3 2 ( ) 3 ( 2
2
= =