RISC / CISC Architecture

by Kajari Sur

Overview
CISC Architecture RISC Architecture

Pipelining

RISC vs CISC

What is CISC
Complex Instruction Set Computer High level Instruction Set Executes several low level operations Ex: load, arithmetic operation, memory store

Memory in those days was expensive

bigger

program->more storage->more money

Hence needed to reduce the number of instructions per program Number of instructions are reduced by having multiple operations within a single instruction Multiple operations lead to many different kinds of instructions that access memory
In

turn making instruction length variable and fetchdecode-execute time unpredictable making it more complex Thus hardware handles the complexity

Example: x86 ISA

Features of CISC
Instructions can operate directly on memory Small number of general purpose registers Instructions take multiple clocks to execute Few lines of code per operation

What is RISC?
Reduced Instruction Set Computer RISC is a CPU design that recognizes only a limited number of instructions Simple instructions Instructions are executed quickly

Original idea to reduce the ISA

Provide

minimal set of instructions that could carry out all essential operations

Instruction complexity is reduced by

1. Having few simple instructions that are the same length 2. Allowed memory access only with explicit load and store instructions

Hence each instruction performs less work but instruction execution time among different instructions is consistent The complexity that is removed from ISA is moved into the domain of the assembly programmer or compiler Examples: LC3, MIPS, PowerPC (IBM), SPARC (Sun)

Features of RISC

Reduced instruction set Executes a series of simple instruction instead of a complex instruction Instructions are executed within one clock cycle Incorporates a large number of general registers for arithmetic operations to avoid storing variables on a stack in memory Only the load and store instructions operate directly onto memory Pipelining = speed

Quick Performance

Pipelining
Assembly Line Technique to process multiple instructions at the same time Allows instructions to be executed efficiently

Stages of Pipelining
Fetch instructions from memory Decode the instruction Execute the instruction or calculate an address Access an operand in data memory Write the result into a register

Pipelining Example

CISC vs RISC
CISC Complex instructions require multiple cycles RISC Reduced instructions take 1 cycle

Many instructions can reference memory

Instructions are executed one at a time Few general registers Many addressing modes Complexity in microcode Variable length instructions

Only Load and Store instructions can reference memory

Uses pipelining to execute instructions Many general registers Few addressing modes Complexity in compiler Fixed length instructions

CISC vs RISC

The difference between CISC and RISC becomes evident through the basic computer performance equation:

RISC systems shorten execution time by reducing the clock cycles per instruction (i.e. simple instructions take less time to interpret) CISC systems shorten execution time by reducing the number of instructions per program

Example for RISC vs. CISC

Consider the the program fragments:

The total clock cycles for the CISC version might be: (2 movs1 cycle) + (1 mul30 cycles) = 32 cycles While the clock cycles for the RISC version is: (3 movs1 cycle) + (5 adds 1 cycle) + (5 loops 1 cycle) = 13 cycles

References

http://cse.stanford.edu/class/sophomorecollege/projects-00/risc/ http://en.wikipedia.org/wiki/Complex_instruction_set_co mputer http://en.wikipedia.org/wiki/RISC http://arstechnica.com/articles/paedia/cpu/pipelining1.ars/4