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ARM Exception Handling and Software Interrupts (SWI) : Introduction To Embedded Systems
ARM Exception Handling and Software Interrupts (SWI) : Introduction To Embedded Systems
Software Interrupts
What is an SWI? What happens on an SWI? Vectoring SWIs What happens on SWI completion? What do SWIs do? A Complete SWI Handler A C_SWI_Handler (written in C)
Terminology
The terms exception and interrupt are often confused Exception They can happen because of some kind of exceptional condition during execution mode. usually refers to an internal CPU event such as
floating point overflow MMU fault (e.g., page fault)
Interrupt - occurs because of external devices outside the CPU core. usually refers to an external I/O event such as
I/O device request Reset
Vector table
It is a table of addresses that the ARM core branches to when an exception is raised
Vector Table
Service routine cannot be put at these addresses Theses addresses commonly contain branch instructions of one of the following forms: B<address> - This branch instruction provides a branch relative from the pc LDR pc, [pc, #offset] This instruction loads the handler address from memory to pc -This results in slight delay due to extra memory access. -Any address in the memory can be used for branch LDR pc, [pc, #-0xff0] This instruction is used when a vector interrupt controller is present( VIC PL190) MOV pc, #immediate This copies an immediate value into the pc. The address must be an 8-bit immediate rotated right by an even number of bits
Disabling an interrupt
Interrupt latency
It is the interval of time from an external interrupt request signal being raised to the first fetch of an instruction of a specific interrupt service routine.
Interrupt latency
How the interrupts are designed SWI are normally used to call privileged operating systems IRQ is normally assigned to general purpose interrupts FIQ is reserved for one single interrupt source that requires fast response time.
Interrupt handler