VLSI PHYSICAL DESIGN

VLSI Design Process

To reduce the complexity of VLSI Design process several levels of abstractions are introduced. The design is taken from specification to fabrication step by step with the help of various CAD Tools.

Levels of Abstraction
Idea Architectural Design Logic Design

Physical Design
Fabrication New Chip

Scope of Physical Design

Physical design of a circuit is the phase that precedes the fabrication of a circuit. Physical design refers to all synthesis succeeding logic design and preceding fabrication. These include the following steps: - Logic Partitioning - Floor planning - Placement and - Routing

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Physical design of any IC mainly affects the Performance of the circuit, its area , its yield and its reliability . Lay out is the most important task in the physical design of an IC chip. Consider the timing performance of the circuit Eg: Poly si metal

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Both poly and metal introduce wiring impedances . Thus longer the wire, the larger the wiring impedance and longer the delays introduced by the wiring impedance. When more than one metal layer is used for the layout , there is another source of impedance. Metal 1 via Metal 2

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Contacts and vias introduce a significant amount of impedance once again contributing to slow down the signals. Consider the area of the circuit: There are two components to the area of an IC 1. FUNCTIONAL AREA 2. WIRE AREA The area taken up by the active elements in the circuit is known as the functional area.

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Eg: serial adder :contains functional modules such as full adder , registers, muxs , d-ff , counter and other logic circuits . The wires used to interconnect these functional modules constitutes wire area.` A good layout should have strongly connected modules placed together , so that long wires are avoided as much as possible.

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Similarly , a good layout will have as few vias as possible. The area of the circuit majorly affects the yield of the manufacturing process. Yield is the number of chips that are defect free in a batch of manufactured chips. The larger the chip area , the lower the yield. A low yield means high production cost which increases the selling cost of the chip.

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The reliability of the chip is also influenced by the layout. Suppose vias are sources of unreliability , then a layout which has a large number of vias is more likely to have defects.

Structure of Resistor in CMOS

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In Fig. a layer within the CMOS process will have a certain resistivity (). By defining a suitable shape of material (and assuming that the thickness of the layer will remain constant), a resistor can be fabricated. Resistors are however physically large (when compared to transistors) and it is difficult to fabricate accurate values

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MOSFET as Resistor
Triode region (square law):

Small signal Resistance :

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Structure of capacitor

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the capacitor is fabricated with two conductors separated by an insulator (dielectric). This forms a capacitor structure. A range of capacitor structures can be formed in the CMOS process.

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Structure of MOSFET
The two types of MOSFETs are the depletion type and the enhancement type, and each has a n /p channel type. The depletion type is normally on, and operates as a JFET. The enhancement type is normally off, which means that the drain to source current increases as the voltage at the gate increases. No current flows when no voltage is supplied at the gate.

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Figure 2: The Structure of a Depletion Type MOSFET and its Operation (a) When VGS (Gate-source voltage) is not supplied (b) When VGS (Gate-source voltage) is supplied

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Figure 3: The Structure of an Enhancement Type MOSFET and its Operation (a) When VGS (Gate-source voltage) is not supplied (b) When VGS (Gate-source voltage) is supplied

POWER MOSFETS
Mosfets that are constructed to handle currents in amperes range and have breakdown voltage capabilities of the order of few hundreds of volts are known as power mosfets. For a small signal Mosfet, there is an upper limit on the drain current due to thin channel having large resistance. This limits the power handling capability of small signal Mosfet to about 1w. Construction of Power mosfet is modified so as to reduce this resistance to milliohm range.

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Also by using small signal mosfets(having short channel), there exist a possibility of depletion region penetrating entire channel and reach source region. When vds is large, the channel length required should also be large, to avoid avalanche breakdown. Ther are two possible constructions for power mosfets: - Lateral Double diffused Mosfet - v-groove Mosfet

STRUCTURE OF LDMOSFET

Operation of LDMOSFET
The construction of planar EMOSFET is modified to LDMOSFET ,to reduce the length of the channel. This will reduce the resistance of the channel. When a positive Vgs is applied , short channel is induced in p-layer between substrate and source. The current flows from n+ and n regions and through induced channel to source.

STRUCTURE OF VMOSFET

Operation of VMOSFET
The term vertical refers to the direction of the channel. VMOSFET has two source terminals, one on each side of gate terminal. The channel is induced vertically on both sides of v-groove between drain and source terminals. The channel length is set by thickness of different layers.

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Two conduction paths from drain to source are responsible for decreasing the resistance of the channel. Power handling capabilities around 10w are easily available.

UMOSFET
UMOSFET

Review of Technology
Moores Law In 1965, Gordon Moore noted that the number of transistors on a chip doubled every 18 to 24 months Transistors/Chip increasing by 50% per year (by 4 in 3.5 years) Gate Delay decreasing by 13% per year (by in 5 years) This rate of improvement will continue until about 2018 at least

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Cost of an Integrated Circuit

The total cost of any product can be separated into two components: ---- the recurring expenses or the variable cost, and ----- the non-recurring expenses or the fixed cost. Fixed Cost The fixed cost is independent of the sales volume, the number of products sold. An important component of the fixed cost of an integrated circuit is the effort in time and manpower it takes to produce the design. This design cost is strongly influenced by the complexity of the design, the aggressiveness of the specifications, and the productivity of the designer.

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Bringing down the design cost in the presence of an ever increasing IC complexity is one of the major challenges that is always facing the semiconductor industry. Additionally, one has to account for the indirect costs, the company overhead. It includes amongst others the companys research and development (R&D), manufacturing equipment, marketing, sales, and building infrastructure. Variable Cost This accounts for the cost that is directly attributable to a manufactured product, and is hence proportional to the product volume.

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Variable costs include the costs of the parts used in the product, assembly costs, and testing costs. The total cost of an integrated circuit is now cost per IC = variable cost per IC + (fixed cost/volume)

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Finished wafer. Each square represents a die - in this case the AMD Duron microprocessor. (Reprinted with permission from AMD).