High Speed Data Generation

for Optical Inter-Satellite Link

(OISL)

KAUSHIK NAGARAJ
ABHISHEK S.M.
 NECESSITY OF OPTICAL
COMMUNICATION
 Transferring large volume of
data in a minute time span.
 Immediate data transmission
for instant monitoring.

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 WHY OPTICAL THAN R.F?
 Higher data rates (in order of Gbps).
 No mutual interference.
 Compact system.
 Weighs less (saves launch cost).
 Consumes less power.
 Little or no regulatory requirement.
 Over all costs low
 Provides base for ever expanding space
activities.

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 Inter-Satellite Links
How They Work

Movie.wmv
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 TYPES OF INTER-SATELLITE
LINKS

1.   LEO – LEO link.

2.   LEO – GEO link.
3.   GEO – GEO link.
4.   GEO – Ground link.
5. Links for Deep Space Missions
(DSM).
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 Basic function of OISL
 Link establishment (Acquisition).
 Link maintenance (Pointing and
Tracking)
 Data transfer.

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 Block Diagram of The OISL System

TRENSMITTER RECEIVER
LASER Detector
ANTENNA ANTENNA
DIODE (APD)
(TELESCOPE) (TELESCOPE)

LASER
DRIVER
ELECTIRCAL
SIGNAL DEMULTIPLEXER
MULTIPLEXER
OPTICAL
SIGNAL PC
PC

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 Block Diagram of PC-Modulator
Interface

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 Basic Building Blocks
1. Data from PC is read out through 8
channels of PCI bus
2. DIO card to bring about data rate
conversion to 19.44 Mbps
3. TTL-to-ECL Translator to bring about TTL
to ECL logic conversion
4. Parallel In Serial Out Shift Register to
read 8 channel parallel input data serially
5. A 4-bit Counter to divide the input clock
by 8

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 Hardware
CLOCK
INPUT OUTPUT
INPUT

133 19.44 External

DIO CARD Mbps 8-channel Mbps 8-channel Clock
parallel parallel 19.44
MHz
19.44
TTL-TO-ECL Mbps 8-channel 19.44 8-channel 19.44
TRANSLATOR parallel Mbps parallel MHz

155.5
PISO SHIFT 19.44 8-channel 155.52
2 serial
REGISTER Mbps parallel MHz
Mbps

CLOCK INPUT C0,C1,C2,C3 155.52

COUNTER
155.52 Mbps 19.44 Mbps MHz
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 Hardware
 Digital Input/Output (DIO)
 Onboard memory
 8 bit TTL compatible input/output lines
 Maximum Transfer rate of 20 Mbps
 Provision for external clock input
 TTL-to-ECL Translator
 8-bit translator
 Clock driven; i.e., should have latch
 PISO Shift Register
 ECL compatible
 Select lines to select between
parallel load & serial right shift
 Counter
 Used as Clock divider

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 Circuit Diagram

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 Propagation Delay
 Propagation delay is inherent in all
ICs
 Total propagation delay of all the

devices put together must not

exceed the duration of 8 clock
pulses, i.e., 51.44ns
 1/155.52=6.43ns
 6.43ns * 8 = 51.44ns

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 Timing Diagram

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 Why ECL
 Emitter Coupled Logic (ECL) is a non-saturating logic
family capable of high speeds with low rise and fall
times
 ECL is an ideal choice for high-speed serial
communications
 ECL uses two supply voltages: 0 V and –5.2 V
 The two logic voltage levels used for signaling are a
function of the upper supply voltage (0V)

 Output High voltage (VOH) : –0.9 (VCC – 0.9 V)

 Output Low voltage (VOL) : –1.7 V (VCC – 1.7 V)

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 LVPECL
 PECL
 Upper supply voltage : +5V
 Lower supply voltage : 0V

 Provides CMOS compatible interface due to

positive supply voltage

 LVPECL
 Upper supply voltage : +3.3V
 Lower supply voltage : 0V

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 Termination
 ECL output is terminated through a
resistor Rt to a voltage VTT, such that
VTT = VCC – 2.0V
R t = Z0
where Z0 is the characteristic impedance
of the transmission line connecting the
ECL output to Rt

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 Software
 DIO Card is software programmable
 Programmable registers for DIO Card
 Input ports – 8 bits
 Output ports – 8 bits

 Generation of control & handshake to

prevent buffer overflow or underflow
 Files of different formats need to be

uniformly read out

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 Future Work
 Fabrication of PCB card
 Testing for proper working

 Implement on INSAT

 Design of receiver

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 Thank You!

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