Combinational circuits

a b c d
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 1
Introductory Example
d <= ( a and b) or c
Test bench
Signals as interconnect wires, can be used on both sides of
assignment operator ( in contrast to I/P or O/P ports);
declared in the declarative part of the architecture
Concurrent execution- order doesnt matter
Structural
Divide and conquer
Small models at a time
Explicitly specify the architecture
Reusability of the code
Behavioral
Just describe the behavior of the circuit(
what the circuit does)
Architecture is left up to the synthesis
tool
Concurrent statements
Order doesnt matter
Sequential statements
Only inside a process, function, procedure
Sequential only if blocking statements are
used (assignment to a variable)
Generally, a mixed design flow is used.
Two ways of modeling hardware
Structural architecture
AND gate
OR gate
2 methods of port map
Top level module
Using work library
The current folder you are working in( included by default unlike
ieee)
Sequential architecture
Working of the sensitivity list
Process is executed only once
whenever there is a change in
the value of the signals included
in the list
Incorrect sensitivity list
Is a process truly sequential?
Assignment to
a signal is a
non-blocking
statement, all
expressions on
the right side
are first
evaluated, and
then
assignment is
done
Lets use an intermediate signal e
1
st
solution
Include
interconnecting
signals in the
sensitivity list
Simulation time
increases
How to make statements inside process truly sequential?
2
nd
solution using variables
Declared in the declarative
part of process; signals
cant be declared inside a
process
Blocking statement;
Next statement will be
executed after the variable
has been updated
Variables cannot be used
outside a process; if a value
stored in a variable is
needed outside a process,
that value will have to be
passed to a signal
Library
The most frequently used packages
are:
Package standard, from the library
std (visible by default)(contains
some predefined data types and
operators)
Library work (the working library;
also visible by default)
Package std_logic_1164, from the
library ieee
Package numeric_std, from the
library ieee (special data types and
operators for arithmetic operations)

VHDL is a strongly typed language
Package standard
Available by default
Bit-related : bit, bit_vector, boolean
Integer-related : integer, natural, positive
Package std_logic_1164
std_logic type: 9 values
0, 1, Z : synthesizable (Z: high impedance/open
ckt; tri state buffer)
U, X : may be encountered in simulation
-, H, L, W
std_logic_vector : for multiple bit signals
(relation of MSB with to and downto)


Data types
Example
4-bit and gate
Package numeric_std
unsigned (array of std_logic)
signed (array of std_logic)
User defined data types
Integer type
type example is range 0 to 15;
Enumerated type
type state is (A, B, C, D, E);
User defined array types
type mem_type is array ( 0 to 3 ) of std_logic_vector( 7
downto 0);
signal memory : mem_type;
Data types
Type conversions between std_logic_vector and numeric data types

Type conversion
Constant
Evaluated during preprocessing and thus requires no physical circuits
Eg :
constant bit_size : integer := 7;
signal eg : std_logic_vector (bit_size downto 0);
Signal
Serves to pass values in and out of the circuit, as well as between its
internal units
In other words, it represents circuit interconnects(wires)
Signal declaration are not allowed in sequential code
signal temp : std_logic_vector (7 downto 0);
Note : All ports of an entity are signals by default
Variable
Can be used only inside a sequential unit
Represents local information

Data objects
Assignment operators
<=: used to assign a value to a signal
:= : used to assign a value to a variable or constant,
used to assign an initial value to a signal
Logical operators
not, and, or, nand, nor, xor, xnor
The only operator with precedence over the others is
not
Supported data types : bit, bit_vector, boolean,
std_logic, std_logic_vector


Operators
Arithmetic operators
+ , - , * , /, **
Supported data types : integer, natural, positive
If numeric_std is used, (un)signed can also be used
Note : std_logic_vector is not supported, so, type
conversion is required
Comparison operator
= , /= , < , > , <= , >=
bit, bit_vector, boolean, integer, natural, positive,
std_logic, std_logic_vector
If numeric_std is used, (un)signed can also be used





Operators
Shift operators
sll, srl, sla, sra, rol, ror
bit_vector
If numeric_std is used, (un)signed can also be used
Eg :
y <= x sll 2; -- if x <= "01001", then y <= "00100" (bit_vector)
Concatenation operator
&
bit_vector, std_logic_vector, unsigned
Eg :
y <=x(2 downto 0) & 00; -- if x <= "01001", then
-- y <= "00100"


Operators
4-bit adder
Example
4 bit Adder( using process and variables)
Concurrent routing/decision statements
when-else
Example: Multiplexer

ZZZ
With-select
Example: Multiplexer

Sequential routing/decision statements
If-else
case
Decoder

Another method
Using case
Priority encoder
Using if
ALU

Chu, P. P. FPGA prototyping by VHDL examples,
2008

Pedroni, V. A. Circuit Design and Simulation
with VHDL, 2008
References