Front-End Electronics For Hybrid Pixel Detectors (Planar and 3D)

Front-End Electronics for
Hybrid Pixel Detectors

(planar and 3D)
SRD 2006, Trento, 14.02.2006

Giovanni Anelli - CERN
SRD 2006, Trento, 14.02.2006

Outline
• SNR
• Timing resolution
• Power consumption, material budget
• Optimum partitioning Impossible
•
•
in 25
Data rate, pile up and the substrate noise problem
Radiation effects in microelectronics
• minutes…
Radiation effects in silicon detectors: cooling
• Layout considerations
• Summary
SRD 2006, Trento, 14.02.2006 Giovanni Anelli - CERN 2

Outline (2nd tentative)
• Signal, speed and noise in a Silicon Pixel

Detector System
• Optimization for maximum Signal to Noise
Ratio
• Optimization for maximum Timing Resolution
• Timing with 3D detectors
• Summary

Outline

Detector System
Ratio
• Optimization for maximum Timing
Resolution
• Conclusions

What are we after?
Signal to Noise Ratio (SNR) ?
Timing resolution ?
In any case, what we are interested in is:

Input Signal (Detector)
Speed (Detector, Electronics)
Noise (Detector, Electronics)

The timing resolution
The best achievable timing resolution depends on:
• Electronic noise (n_out) σ n_out
• Signal slope σt 
 Signal amplitude
dv out (t)
 Signal speed dt
vout(t)
Threshold σn
σt σt
Silicon detector signal amplitude
The amount of charge deposited follows the Landau
distribution. Thicker detectors give more signal!
M. Scarpa
Qin  t det
Energy Deposited (MeV)

Silicon detector speed
The carrier speed depends on the carrier type, on the
applied bias voltage and on the detector temperature
Hole speed:
34 m/ns
Reasonable (?) E field:

200 V on a 200 m thick
detector
Silicon detector speed (2)
Signal shape example: we assume an over depleted planar
detector (200 m thick, large pixels)
E = 104 V/cm
t det
coll_h 
v h (E, Tdet )
All the created electrons

and holes are collected
The beauty of 3D detectors
Thin planar detectors are fast… but we loose signal!
In 3D detectors we decouple the signal amplitude (which

comes from the thickness) from the speed (which comes
from the distance between vertical electrodes).
And we have small depletion voltages and radiation
hardness.
The possible disadvantages are that the signal shape

depends on where the ionizing particle goes through the
detector and that the capacitance might be higher than in a
planar detector (if the pitch between the vertical electrodes
is small). more later…
Electronic Noise
I will assume in the following that the signal from the detector
will be amplified by a charge amplifier.
The noise deteriorating the SNR or the time resolution is
mainly due to the noise of the amplifier input transistor and
to the detector leakage current shot noise (parallel noise).
In CMOS technologies, the transistors have mainly two noise
components:
1. Channel thermal noise (white noise)
2. 1/f noise
In the following, we will express the noise at the input of

the amplifier as an Equivalent Noise Charge (ENC)
Electronic Noise (2)
CF N.B. This
v out_MAX  G  Qin holds if
p > coll_holes
Qin   iin (t)dt
vout(t)
SHAPER Vout_MAX
iin(t) p
CD
Q in
SNR 
ENC
σ n_out ENC  G ENC  G  τ p ENC  τ p
σt    
dv out (t) v out_MAX Qin  G Qin
dt τp
Electronic Noise (3)
v n2  4kT
1

Kf 1 CF NOTE
gm Cox WL f DEPENDENCIES
ON W AND p
gm  f (IDS , W, L)
Cgs  f (IDS , W, L)
v n2 SHAPER
IDS p
iin(t) Cgs
CD in2  2qIleak
+ Ileak
Kf
ENC1/f  (CD  Cgs )
Cox WL
1 1
ENC w  (CD  Cgs ) kT
gm p
ENC  ENC 2w  ENCp2  ENC1/f
2
ENCp  2qIleak p
Planar detector capacitance
The detector capacitance is a function of the detector thickness tdet and
of the pixel size. The capacitance of each pixel (Cdet) has a component
dependent on the pixel area and one on the pixel perimeter. The latter
is normally quite important and has a very little dependence on tdet.
pixel size
Cdet 
t det
Not to be
forgotten:
parasitics!
Detector leakage current
If the dominating component of the leakage current comes from the
bulk, the leakage current of each pixel Ileak varies linearly with the
volume of the pixel.
Ileak_spec = 10 nA/cm2
Ileak  (pixel size)  t det

Noise vs shaping time (low Ileak)
Ileak = 10 pA, Cdet = 200 fF, IDS = 130 A

Noise vs shaping time (high Ileak)
Ileak = 10 nA, Cdet = 200 fF, IDS = 130 A

Noise vs transistor width
Ileak = 10 nA, Cdet = 200 fF, IDS = 130 A, p = 10ns

Outline

Detector System
Ratio (planar detectors)
Resolution
• Conclusions

Is there an optimum somewhere?
1 Kf 1 σ n_out ENC  G ENC  G  τ p ENC  τ p
v  4kT
2
 σt    
n dv out (t) v out_MAX Qin  G Qin
gm Cox WL f
dt τp
gm  f (IDS , W, L)
Cgs  f (IDS , W, L) Kf
ENC1/f  (CD  C gs )
Cox WL
Qin   iin (t)dt
1 1
v out_MAX  G  Qin ENC w  (CD  Cgs ) kT
gm p
in2  2qIleak
ENCp  2qIleak p
pixel size
Cdet 
t det
ENC  ENC 2w  ENCp2  ENC1/f
2
t det
Qin  t det coll_h 
v h (E, Tdet ) Ileak  (pixel size)  t det

Optimization program
Once we have fixed:
• Power available per unit area
• Detector leakage current per unit area
• Technology, transistor type and gate length
• Detector thickness
For each pixel dimensions we have that the ENC is a function of the
shaping time and of the transistor size. This function has always a
minimum. We plot this minimum as a function of the pixel
dimensions.
N.B. All the calculations done in the following take into account the variations of C gs and gm
depending on the transistor working region

Optimum pixel size (for SNR) – Ex. 1
• Power: 1.2 W / cm2

• tdet = 150 m
• Ileak = 10 nA / cm2
• 0.25 m TSMC
technology
• PMOS input
transistor, minimum
gate length
• All the power per
pixel BUT 500 W
goes into the input
transistor

Shaping time – Ex. 1

Transistor width – Ex. 1

Optimum pixel size (for SNR) - Ex. 2

• tdet = 150 m
• Ileak = 10 A / cm2
• 0.25 m TSMC
technology
• PMOS input
transistor, minimum
gate length
pixel BUT 500 W
goes into the input
transistor

Shaping time – Ex. 2

Optimum pixel size (for SNR) - Ex. 3
• tdet = 150 m
• Ileak = 10 nA / cm2
• Shaping time = 25 ns
• 0.25 m TSMC
technology
• PMOS input
transistor, minimum
gate length
pixel BUT 500 W
goes into the input
transistor
Outline

Detector System
Ratio
Resolution (planar detectors)
• Conclusions

Timing resolution
Obtaining a good SNR is normally NOT a problem with pixel
detectors (except in special cases such as extremely small
signals and very small power and very high granularity).
Having a good timing resolution is a bit trickier…
Let’s make some assumptions:
• Max power dissipation allowed: 1.2 W/cm2
• Signal: Minimum of the Landau divided by 2 to take into account
the charge sharing
• Technology considered: IBM 0.25 m CMOS (but similar results
are obtained with the IBM 0.13 m CMOS)
• We always chose the shaping time equal to the hole collection
time (this for the best timing resolution)
Optimum pixel size (for timing) – Ex. 1
With a low leakage current and at short shaping times the noise is
dominated by the white noise components.
ENC  τ p
σt 
Qin Ileak_spec = 10 nA/cm2
The shaping time
is here chosen
equal to the hole
collection time (to
go fast without
loosing signal)
1 1
ENC w  kT 
gm p
1 ENC w  (CD  Cgs )
IDS 
pixel size
Optimum pixel size (for timing) – Ex. 2
For higher leakage currents

(after irradiation) the parallel Ileak_spec = 12 A/cm2
noise component (ENCp)
become also very important,
as we can see in the plots at
room temperature.
Only cooling down we go
(almost) back to the case in
which the noise is
dominated by the white
noise.
We see here the importance of cooling (if the detector leakage current is
too high). But cooling might be difficult if we need a small material budget.

Optimum tdet (for timing) – Ex. 1
For low leakage currents we are dominated by white
noise, which decreases increasing the shaping time
ENC  τ p
Ileak_spec = 10 nA/cm2 σt 
Qin
p increases linearly
with the detector
thickness, Qin almost
linearly.

Optimum tdet (for timing) – Ex. 2
For high leakage Ileak_spec = 12 A/cm2

currents (like for an
irradiated detector at
room temperature)
increasing the shaping
time does not
decrease the noise
anymore!

Outline

Detector System
Ratio
Resolution (planar detectors)
• Conclusions

The beauty of 3D detectors
With 3D detectors we can maximize signal and speed at the
same time (they can be thick and fast at the same time, if the
pitch between the columns is small).
BUT
A small pitch can lead to high capacitances ( high noise)
In the following, we will try to estimate this capacitance and

compare 3D and planar detectors (for speed).
Note:
I will assume a thermal noise limited system (normally true at
short shaping times).
These results are preliminary, more work needs to be done.
3D pixel capacitance
Pixel side = 2*pitch
We can have an estimate
pitch
of the capacitance using
the coaxial cable formula.
This seems to be a
reasonable estimate,
according to some
simulations done by C.
Piemonte (gratefully
acknowledged)
2
C col   t det
 pitch  2 
ln 

 r 

4 “columns” per pixel
Pixel side = 4*pitch, C = 4*Ccol

9 “columns” per pixel
Pixel side = 4*pitch, C = 9*Ccol

Capacitance comparison
Columns per pixel
• Pitch = 50 m 1 4 9 16 25
• Columns radius =
6 m
• tdet = 200 m
N.B. The 3D pixel

capacitance is an
overestimate

Timing: better planar or 3D?
• Pitch = 50 m
• Columns radius =
6 m
• tdet = 200 m
• 0.25 m IBM
technology
• PMOS input
transistor, minimum
gate length

With one column per pixel

With one column per pixel (2)
For relatively large pixels, the “one column per pixel”

approach gives better results.
Summary
• First of all, remember that all the above calculations do not
include:
 The noise coming from the reset system
 The noise of the other transistors in the amplifier first stage
This is going to make things a bit worse
• Unless we have very demanding requirements, it is normally
possible to obtain good SNR (> 10) with Hybrid Silicon Pixel
Detectors
• It is going to be very difficult to have timing resolutions
< 100 ps with thin (~200 m) planar detectors. 3D detectors
are better in this respect!
• Power consumption is an issue (Sherwood would like
“problem” more, and it is very much linked to how much
material we can have.

Summary (cont.)
• We know how to make radiation hard ICs, especially for total
dose. For SEEs things might be more complicated, but still
there are methods to get rid of these problems.
• The post-irradiation leakage current is a potential killer of the
performance of a silicon pixel detector.
• The results I have shown are the BEST one can obtain. Many
problems can make them much worse, such as, for example,
substrate noise.
• I have concentrated my talk on a single transistor. Normally,
there is a lot of “system” around it. Normally, it is not easy to
make this system and to maintain the nice performance of the
above mentioned single transistor!

Thank you for your attention

SPARE SLIDES
SPARE
SLIDES
Silicon detector speed (3)
If we want to collect all the charge (not to loose signal) we
do have to make the electronics slower than the detector
E = 104 V/cm
t det
coll_h 
v h (E, Tdet )

Again on SNR (1)
The requirement on low noise given by the timing resolution normally
gives a very good SNR. Increasing the detector thickness we increase
the input signal and decrease the noise (if the white noise is dominant).
Ileak_spec = 10 nA/cm2
Qin
SNR 
ENC

Again on SNR (2)
When the parallel noise (from the leakage current) becomes also
important, the SNR still increases for thicker detectors (the input signal
increases), but at a slower pace (the noise decreases less or increases).
Ileak_spec = 12 A/cm2

The time walk
Signals with same

shape but different
amplitude will cross the
threshold at different
times. This spread can
easily be a few
nanoseconds. Threshold
Time walk
There are several techniques to compensate for this:

• Zero crossing discriminators (bipolar signals)
• Time over threshold techniques
• Constant fraction discriminators
And after the discriminator what?
To compensate for the time
walk one can use t1 and t3
(TOT). t1 and t2 is even better,
because the slope for t2 is
bigger and we keep the
“bus” busy for a shorter time
(important for the efficiency).
t1 t2 t3
PIXEL To measure the time one

possibility is to use a Time-
PIXEL
to-Digital Converter (TDC)
PIXEL per group of pixels.
TDC
PIXEL How many pixels can we
..
.. connect to the same TDC for
.
a given efficiency?
PIXEL

TDC Inefficiency
For 1 GHz total rate, 300 m by 300 m pixels and a beam area of 36 mm
by 48 mm the average rate per pixel is 52 kHz. The probability of having
two pixels (connected to the same TDC) hit in a time interval T
depends on the total number of pixels N going to the same TDC.
For a 1% inefficiency and an average rate of 52 kHz we have:
N
M. Scarpa
T
Data rate
Let’s assume a matrix of 32 columns and 60 rows (9.6 mm by 18 mm)

How many bits per hit?
t1 7 bits (10 ns / 128 = 78 ps)
t2 7 bits 32 bits per hit
Longer time 7 bits (10 ns * 128 = 1.28 s)
Pixel address 11 bits
What is the data rate per chip?
The average rate per chip is ~ 100 MHz
100 MHz * 32 bits gives 3.2 Gbit/s!!!
Transmitting this amount of data in principle should not be a big

problem. But how well can a Gbit/s transmitter coexist on the chip
together with all the rest? See next topic!
Digital noise in mixed-signal ICs
Integrating analog blocks on the same chip with digital circuits can
have some serious implications on the overall performance of the
circuit, due to the influence of the “noisy” digital part on the “sensitive”
analog part of the chip.
The switching noise originated from the digital circuits can be coupled
in the analog part through: V DD
• The power and ground lines

VIN VOUT
• The parasitic capacitances between interconnection lines
• The common substrate
GND
The substrate noise problem is the most difficult to solve.

Noise reduction techniques
• Quiet the Talker. Examples (if at all possible !!!):
 Avoid switching large transient supply current
 Reduce chip I/O driver generated noise
 Maximize number of chip power pads and use on-chip decoupling
• Isolate the Listener. Examples:
 Use on-chip shielding
 Separate chip power connections for noisy and sensitive circuits
 Other techniques depend on the type of substrate. See next slide
• Close the Listener’s ears. Examples:
 Design for high CMRR and PSRR
 Use minimum required bandwidth
 Use differential circuit architectures
 Pay a lot of attention to the layout

Different types of substrates
There are mainly two types of wafers:
1. Lightly doped wafers: “high” resistivity, in the order of

10 Ω-cm.
2. Heavily doped wafers: usually made up by a “low”

resitivity bulk (~ 10 mΩ/cm) with a “high” resistivity
epitaxial layer on top.
TSMC, UMC, IBM and STM (below 180 nm) offer type 1

Substrate noise: how to reduce it
To minimize the impact of disturbances coming from the substrate on
the sensitive analog blocks, we have mainly three ways:
• Separate the “noisy” blocks from the “quiet” blocks. This is effective
especially in uniform lightly doped substrates. For heavily doped substrates, it
is useless to use a separation greater that about 4 times the epitaxial layer
thickness.
• In n-well processes, p+ guard rings can be used around the different blocks.
Unfortunately, this is again effective mainly for lightly doped substrates. Guard
rings (both analog and digital) should be biased with separate pins.
• The most effective way to reduce substrate noise is to ground the substrate
itself in the most “solid” possible way (no inductance between the substrate
and ground). This can be done using many ground pins to reduce the
inductance, or, even better, having a good contact on the back of the chip
(metallization) and gluing the chip with a conductive glue on a solid ground
plane.
• Separate the ground contact from the substrate contact in the digital logic
cells, to avoid to inject the digital switching current directly into the substrate.
Interaction radiation - ICs
The two most important phenomena to be considered

are ionization and nuclear displacement.
Neutrons give origin mainly to nuclear displacement.
Photons give ionization.
Charged hadrons and heavy ions give both at the same
time.
For ionization we talk about Total Ionizing Dose (TID),
for nuclear displacement about Fluence

Interaction radiation – ICs (2)
MOS
TID
Bipolars
Cumulative
Effects Displacement
Bipolars
Optoelectronics
Non Catastrophic
Single Event (SEU)
MOS
Effects (SEE) Catastrophic
MOS
(SEGR, SEL)
SRD 2006, Trento, 14.02.2006 Giovanni Anelli - CERN

Radiation-hard circuits
Using a CMOS technology we have to worry “only”

about TID effects and SEEs
• In the Microelectronics Group at CERN we have
developed layout techniques which allow solving the most
disturbing TID effects and the Single Event Latch-up (SEL)
issue
• Single Event Gate Rapture (SEGR) never occurs in
advanced CMOS processes
• Single Event Upset (SEU) still remains an issue. We will
have to protect the most critical digital blocks against it
(special circuit architecture, redundancy, …)

Best option for min material budget
Readout Chip
48 mm
MATRIX
36 mm
32 x 60
21 mm
18 mm
cells
Area available for

all the remaining
circuitry!
Detector BUS (VDD, GND,
Signals) PROBLEM:
Support POWER DISTRIBUTION FOR
(Carbon Fiber?)
THE MATRIX, CHIP SIZE
Intermediate option
18 mm
MATRIX
48 mm 32 x 60
21 mm
cells
18 mm
In this case the problem of the power distribution is reduced but we still
have a very small area for all the rest of the circuits, a very long chip
and we have a non uniform material budget in the centre of the beam!
Possible best overall choice?
12 mm
48 mm
12 mm
18 mm
MATRIX
32 x 40
cells
This solution still has non uniformities in the material budget (but not
in the beam centre). On the other hand it gives:
• Power distribution on two sides of the chip
• More area for the circuits not in the matrix Last idea:
• A smaller chip (better yield, lower cost) Deep Via Technology?

Front-End Electronics For Hybrid Pixel Detectors (Planar and 3D)

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Front-End Electronics for

Hybrid Pixel Detectors

SRD 2006, Trento, 14.02.2006

SRD 2006, Trento, 14.02.2006

SRD 2006, Trento, 14.02.2006 Giovanni Anelli - CERN 2

• Signal, speed and noise in a Silicon Pixel

SRD 2006, Trento, 14.02.2006 Giovanni Anelli - CERN 3

• Signal, speed and noise in a Silicon Pixel

SRD 2006, Trento, 14.02.2006 Giovanni Anelli - CERN 4

Signal to Noise Ratio (SNR) ?

In any case, what we are interested in is:

SRD 2006, Trento, 14.02.2006 Giovanni Anelli - CERN 5

Energy Deposited (MeV)

SRD 2006, Trento, 14.02.2006 Giovanni Anelli - CERN 7

Reasonable (?) E field:

All the created electrons

In 3D detectors we decouple the signal amplitude (which

The possible disadvantages are that the signal shape

In the following, we will express the noise at the input of

Ileak  (pixel size)  t det

SRD 2006, Trento, 14.02.2006 Giovanni Anelli - CERN 15

SRD 2006, Trento, 14.02.2006 Giovanni Anelli - CERN 16

SRD 2006, Trento, 14.02.2006 Giovanni Anelli - CERN 17

SRD 2006, Trento, 14.02.2006 Giovanni Anelli - CERN 18

• Signal, speed and noise in a Silicon Pixel

SRD 2006, Trento, 14.02.2006 Giovanni Anelli - CERN 19

SRD 2006, Trento, 14.02.2006 Giovanni Anelli - CERN 20

SRD 2006, Trento, 14.02.2006 Giovanni Anelli - CERN 21

• Power: 1.2 W / cm2

SRD 2006, Trento, 14.02.2006 Giovanni Anelli - CERN 22

SRD 2006, Trento, 14.02.2006 Giovanni Anelli - CERN 23

SRD 2006, Trento, 14.02.2006 Giovanni Anelli - CERN 24

• Power: 1.2 W / cm2

SRD 2006, Trento, 14.02.2006 Giovanni Anelli - CERN 25

SRD 2006, Trento, 14.02.2006 Giovanni Anelli - CERN 26

• Signal, speed and noise in a Silicon Pixel

SRD 2006, Trento, 14.02.2006 Giovanni Anelli - CERN 28

For higher leakage currents

SRD 2006, Trento, 14.02.2006 Giovanni Anelli - CERN 31

SRD 2006, Trento, 14.02.2006 Giovanni Anelli - CERN 32

For high leakage Ileak_spec = 12 A/cm2

SRD 2006, Trento, 14.02.2006 Giovanni Anelli - CERN 33

• Signal, speed and noise in a Silicon Pixel

SRD 2006, Trento, 14.02.2006 Giovanni Anelli - CERN 34

In the following, we will try to estimate this capacitance and

SRD 2006, Trento, 14.02.2006 Giovanni Anelli - CERN 36

SRD 2006, Trento, 14.02.2006 Giovanni Anelli - CERN 37

SRD 2006, Trento, 14.02.2006 Giovanni Anelli - CERN 38

N.B. The 3D pixel

SRD 2006, Trento, 14.02.2006 Giovanni Anelli - CERN 39

SRD 2006, Trento, 14.02.2006 Giovanni Anelli - CERN 40

SRD 2006, Trento, 14.02.2006 Giovanni Anelli - CERN 41

For relatively large pixels, the “one column per pixel”

SRD 2006, Trento, 14.02.2006 Giovanni Anelli - CERN 43

SRD 2006, Trento, 14.02.2006 Giovanni Anelli - CERN 44

SRD 2006, Trento, 14.02.2006 Giovanni Anelli - CERN 45

SRD 2006, Trento, 14.02.2006 Giovanni Anelli - CERN 47

SRD 2006, Trento, 14.02.2006 Giovanni Anelli - CERN 48

SRD 2006, Trento, 14.02.2006 Giovanni Anelli - CERN 49

Signals with same

There are several techniques to compensate for this:

PIXEL To measure the time one