Design for Performance

Design for Performance

Modifed From "Digital Integrated Circuits", by J. Rabaey, A. Candra!asan and ". #i!olic
Contents
o
Device Sizing
o
Inverter Chain Sizing
o
CMOS gates transient considerations
o
Logical Effort
Modifed From "Digital Integrated Circuits", by J. Rabaey, A. Candra!asan and ". #i!olic
Design for Performance

Keep capacitances (internal, interconnect and fan-ot! s"all

#$ good la$ot

Increase transistor sizes

%
&atch ot for self-loading'

Once that the intrinsic capacitance do"inates the dela$, &(L does
not help an$"ore

Increase )
DD

%
*here are li"its to the "a+i"",
%
Increases po-er cons"ption
Device Sizing
Modifed From "Digital Integrated Circuits", by J. Rabaey, A. Candra!asan and ". #i!olic
De$ice %i&ing

.ss"ing a s$""etrical inverter, the capacitance is co"posed of/

Cint is the self-load, associated -ith diffsion and gate-drain (Miller!

Ce+t is e+trinsec, load, -iring, etc,

&here is the intrinsec dela$ (Ce+t01!

&hat are the conse2ences of scaling 3

ext L
C C C + =
int
! ( 4 ( ! ( 56 , 1
int 1 int
C C t C C R t
ext p ext eq p
+ = + =
int 1
56 , 1 C R t
eq p
=
Modifed From "Digital Integrated Circuits", by J. Rabaey, A. Candra!asan and ". #i!olic
De$ice %i&ing

Cint scales -ith size ratio S, and also 7e2/

*he dela$ is/

int
, ( ,
iref eq iref
C SC R R S = =
! ( 4 (
1 iref ext p p
SC C t t + =

*he intrinsic dela$ is independent of sizing and is deter"ined #$

technolog$ and la$ot,

Ma8ing S infinitel$ large gives the "a+i"" perfor"ance gain,

eli"inating the i"pact of an e+ternal load, 9et, a #ig enogh sizing
prodces si"ilar reslts -ith a gain in Silicon area

. #ig inverter has #ig inpt capacitance and affects the previos stages '
Modifed From "Digital Integrated Circuits", by J. Rabaey, A. Candra!asan and ". #i!olic
2 4 6 8 10 12 14
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
3.8
x 10
-11
S
t
p
(
s
e
c
)
De$ice %i&ing
'for f(ed load)
%elf*loading e+ect,
Intrinsic ca-acitances
dominate
In$erter Cain %i&ing
Inverter Chain Sizing
Modifed From "Digital Integrated Circuits", by J. Rabaey, A. Candra!asan and ". #i!olic
In$erter Cain
C
L
If C
.
is gi$en,
* /o0 many stages are needed to minimi&e te delay1
* /o0 to si&e te in$erters1
May need some additional constraints.
In
Out
Modifed From "Digital Integrated Circuits", by J. Rabaey, A. Candra!asan and ". #i!olic
In$erter Delay
2 Minimum lengt de$ices, .
2 Assume tat W
P
3 4W
N
=4W
2 same -ull*u- and -ull*do0n currents
2 a--ro(. e5ual resistances R
N
3 R
P
2 a--ro(. e5ual rise t
pLH
and fall t
pHL
delays
W N
unit
N
unit
unit
P
unit
P
R R
W
W
R
W
W
R
R = =

=
t
pHL
0 (ln :! R
N
C
L
t
pLH
0 (ln :! R
P
C
L
Delay 'D),
2W
W
unit
unit
gin
C
W
W
C ; = .oad for te ne(t stage,
Modifed From "Digital Integrated Circuits", by J. Rabaey, A. Candra!asan and ". #i!olic
Delay Formula
( )
( ) ( ) ( 4 ( 4
<
1
int
f t C C C kR t
C C R Delay
p int L W p
L int W
+ = + =
+
C
int
= C
gin
with

1
f = C
L
/ C
gin
- effective fanout
Delay is only a function of te ratio bet0een its e(ternal load
ca-acitance and its in-ut ca-acitance
Modifed From "Digital Integrated Circuits", by J. Rabaey, A. Candra!asan and ". #i!olic
A--ly to In$erter Cain
C
L
In Out
1 2 N
t
p
= t
p1
+ t
p2
+ + t
pN

+
+
j gin
j gin
unit unit pj
C
C
C R t
,
4 ,
4 <

L N gin
N
i
j gin
j gin
p
N
j
j p p
C C
C
C
t t t =

+ = =
+
=
+
=
4 ,
4
,
4 ,
1
4
,
, 4

Modifed From "Digital Integrated Circuits", by J. Rabaey, A. Candra!asan and ". #i!olic
6-timal 7a-ering for 8i$en N

Dela$ e2ation has N - 4 n8no-ns, Cgin

:
% Cgin
N

Mini"ize the dela$, find N - 4 partial derivatives

7eslt/ Cgin,j=4(Cgin,j 0 Cgin,j(Cgin,j-4

%
Each stage has the sa"e effective fanot (Cout(Cin!
%
Each stage has the sa"e dela$

Size of each stage is the geo"etric "ean of t-o neigh#ors

4 , 4 , , +
=
j gin j gin j gin
C C C
Modifed From "Digital Integrated Circuits", by J. Rabaey, A. Candra!asan and ". #i!olic
6-timum Delay and #umber of %tages

&hen each stage is sized #$ f and has sa"e eff, fanot f/

Effective fanot of each stage/

Mini"" path dela$

4 ,
(
gin L
N
C C F f = =
N
F f =
( ) ( 4
1
N
p p
F Nt t + =
Modifed From "Digital Integrated Circuits", by J. Rabaey, A. Candra!asan and ". #i!olic
9(am-le
C
L
= 8 C
1
In
Out
C
1
1 f f
2
: >
;
= = f
C
L
/C
1
has to be evenly distributed across N = 3 stages
Modifed From "Digital Integrated Circuits", by J. Rabaey, A. Candra!asan and ". #i!olic
6-timum #umber of %tages
?or a given load, C
L
and given inpt capacitance C
in
?ind opti"al sizing f
1
1
ln
4
ln ln
p
p p
t F
f f
t Nt
f f

= + = +


1
ln
4 ln
ln
:
1
=

=

f
f f
F t
f
t
p p

( ) f f + = 4 e+p
f that "ini"izes total dela$ reslts fro"/
f
F
N C f C F C
in
N
in L
ln
ln
and
= = =
Modifed From "Digital Integrated Circuits", by J. Rabaey, A. Candra!asan and ". #i!olic
6-timum 9+ecti$e Fanout f
6-timum f for gi$en -rocess defned by :
( ) f f + = 4 e+p
f
opt
3 ;.<
for :3=
For 0 1, f 3 e, N 3 lnF
Modifed From "Digital Integrated Circuits", by J. Rabaey, A. Candra!asan and ". #i!olic
7rade*o+s in te coice of #

@"#er of stages large, intrinsic dela$ do"inates

*oo s"all, the effective fan-ot do"inates

&ith "ore stages (s"aller f!, @ gro-s e+ponenciall$ and f

decreases linearl$/ tp increases

With fewer stages (bigger f), N reduces and f increases: tp

remains roughly constant
( )
1
log( !
4 ( ,
log( !
p p
F
t Nt f N
f
= + =
Modifed From "Digital Integrated Circuits", by J. Rabaey, A. Candra!asan and ". #i!olic
Coice of #, 9(am-le
2
9(am-le, Ci3=fF, Cout3=-F, F3=>>>
( ) ( 4
1
N
p p
F Nt t + =
t
p (nor"alized dela$! N (n"#er of stages!
f
f
!a"e f slightly larger than o#ti$u$ %to round off stages& 'y#&=()
Modifed From "Digital Integrated Circuits", by J. Rabaey, A. Candra!asan and ". #i!olic
#ormali&ed delay function of F
2
?alues of t-@6-timum't-) for se$eral designs
F Unbufered Two Stage Inverter
chain
=> == A.; A.;
=>> =>= 44 =<.B
=>>> =>>= <B 4C.A
=>,>>> =>,>>= 4>4 ;;.=
Modifed From "Digital Integrated Circuits", by J. Rabaey, A. Candra!asan and ". #i!olic
"u+er Design
1
1
1
1
*
+(
+(
+(
+(
(
2&*
*
1+
22&+
N f t
p
1 64 65
2 8 18
3 4 15
4 2.8 15.3
CMOS ates
Modifed From "Digital Integrated Circuits", by J. Rabaey, A. Candra!asan and ". #i!olic
CM6% 8ates

Static Aroperties of gates

Dela$ characteristics

?an-in and ?an-ot considerations

Modifed From "Digital Integrated Circuits", by J. Rabaey, A. Candra!asan and ". #i!olic
%tatic Pro-erties

Depend on inpt pattern

1)
;)
;)
1)
Vin
Vout
a! .0B01 C 4
#! .04, B01 C 4
c! B04, .01 C 4
a! *-o pll-p transistors in parallel are "ore difficlt to trn off than one
#! One pll-p transistor, one pll-do-n, D$na"icall$, the internal node has
to #e discharged (slo-er!
c! )ds4 prodces #l8 effect dring discharge, )t of transistor . is
increased, More )in is needed
Modifed From "Digital Integrated Circuits", by J. Rabaey, A. Candra!asan and ". #i!olic
%0itc Delay Model
,
-
e.
,
-
#
,
-
#
,
-
n /
0
,
/
0
1
-
n
,
-
#
1
-
#
,
-
n
/
int
1
-
#
,
-
#
,
-
n
1
-
n /
0
/
int
NAND2
INV
NOR2
Modifed From "Digital Integrated Circuits", by J. Rabaey, A. Candra!asan and ". #i!olic
In-ut Pattern 9+ects on Delay
2
Delay is de-endent on te
-attern of in-uts
2
.o0 to ig transition
%
bot in-uts go lo0

delay is >.<D R
-
@4 C
.
%
one in-ut goes lo0

delay is >.<D R
-
C
.
%
0en # transistor A goes o+,
internal node as to be carged
2
/ig to lo0 transition
%
bot in-uts go ig

delay is >.<D 4R
n
C
.
/
0
1
-
n
,
-
#
1
-
#
,
-
n
/
int
Modifed From "Digital Integrated Circuits", by J. Rabaey, A. Candra!asan and ". #i!olic
Delay De-endence on In-ut Patterns
-0.5
0
0.5
1
1.5
2
2.5
3
0 100 200 300 400
,=1=12
,=13 1=12
,=1 23 1=1
ti$e 4#s5
6
o
l
t
a
g
e

4
6
5
Input Data
Pattern
Delay
(psec)
.0B014
5D
.04, B014
5E
.0 14, B04
54
.0B041
EF
.04, B041
>1
.0 41, B04
>4
NMOS = 0.5m/0.25
m
PMOS = 0.75m/0.25
m
C
L
= 100 fF
when N transistor , goes off %,=1)3 internal node
has to be charged %slower)
Modifed From "Digital Integrated Circuits", by J. Rabaey, A. Candra!asan and ". #i!olic
7ransistor %i&ing
/
0
1
-
n
,
-
#
1
-
#
,
-
n
/
int
1
-
#
,
-
#
,
-
n
1
-
n /
0
/
int
2
2
2 2
1
1
(
(
N,N7 based i$#le$entations are #referred over NO-
Modifed From "Digital Integrated Circuits", by J. Rabaey, A. Candra!asan and ". #i!olic
7ransistor %i&ing a Com-le( CM6% 8ate
O8' = 7 + , 9 %1 + /)
7
,
1 /
7
,
1
/
1
2
2 2
(
(
*
*
+
3
+
+
Modifed From "Digital Integrated Circuits", by J. Rabaey, A. Candra!asan and ". #i!olic
Fan*In Considerations
7 / 1 ,
7
/
1
,
/
0
/
3
/
2
/
1
Distri#ted 7C "odel
(El"ore dela$!
t
pGL
0 1,56 7
e
(C
4
=:C
:
=;C
;
=EC
L
!
0 7
e
C
4
=: 7
e
C
:
=;7
e
C
;
=E7
e
C
L
H Aropagation dela$ deteriorates
rapidl$ as a fnction of fan-in %
2adraticall$ in the -orst case, (prop,
to 7IC!
H Internal nodes i"portant ''
Modifed From "Digital Integrated Circuits", by J. Rabaey, A. Candra!asan and ". #i!olic
t
-
as a Function of Fan*In
0
250
500
750
1000
1250
2 4 6 8 10 12 14 16
t
#:0
.uadratic
linear
t
#
t
#0:
t
#

%
#
s
e
c
)
fan-in
;ates with a fan-in greater than ( should be avoided&
Intrinsec / increases
linearly
<eries transistors cause a
double slowdown
=arallel transistors
increase /
Modifed From "Digital Integrated Circuits", by J. Rabaey, A. Candra!asan and ". #i!olic
t
-
as a Function of Fan*6ut
2 4 6 8 10 12 14 16
t
#
NO-2
t
#

%
#
s
e
c
)
eff& fan-out
,ll gates
have the
sa$e drive
current&
t
#
N,N72
t
#
IN6
<lo#e is a
function of
>driving
strength?
Modifed From "Digital Integrated Circuits", by J. Rabaey, A. Candra!asan and ". #i!olic
t
-
as a Function of Fan*In and Fan*6ut

?an-in/ 2adratic de to increasing resistance and capacitance

?an-ot/ each additional fan-ot gate adds t-o gate

capacitances to C
L
2
t
-
3 a
=
FI E a
4
FI
4
E a
;
F6