Unit 1 L4-L8

UNIT 1
L4-L8

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Lecture -4
The 8085 Microprocessor pin diagram

The 8085 pin diagram
The 8085 is an 8-bit general purpose microprocessor that can
address 64K Byte of memory.
It has 40 pins and uses +5V for power. It can run at a
maximum frequency of 3 MHz.
The pins on the chip can be grouped into 6 groups:
Address Bus.
Data Bus.
Control and Status Signals.
Power supply and frequency signals.
Externally Initiated Signals.
Serial I/O ports.
The Address and Data Busses
The address bus has 8 signal lines A
8
A
15
which are
unidirectional.
The other 8 address bits are multiplexed (time shared) with
the 8 data bits.
So, the bits AD
7
AD
0
are bi-directional and serve as A0
A7 as well as D0 D7.
During the execution of the instruction, these lines
carry the address bits during the early part of the cycle,
then during the later part of the cycle, they carry the 8
data bits.

The Address and Data Busses

In order to separate the address from the data, we can use
a latch to save the value before the function of the bits
changes.
The Control and Status Signals

ALE: Address Latch Enable. This signal is a positive going pulse
generated every time 8085 begins an operation(machine cycle) .It
becomes high when the AD
7
AD
0
lines have an address on them.
It becomes 0 after that. This signal can be used to enable a latch
to save the address bits from the multiplexed AD lines.
R D : Read. Active low. This is a read control signal.This signal
indicates that the selected I/O or memory device is to be read.

The Control and Status Signals

W R : Write. Active low. . This is a write control
signal.This signal indicates that the data on the data bus
are to be written into the selected memory or I/O
location.
IO/M (M active low): This signal specifies whether the
operation is a memory operation (IO/M =0) or an I/O
operation (IO/M =1).
S1 and S0 : Status signals to specify the kind of
operation being performed .Usually un-used in small
systems.

8085 machine cycle status and control signals
Machine Cycle IO/M S1 S0 Control Signals
Opcode Fetch 0 1 1 R D =0
Memory Read 0 1 0 R D =0
Memory write 0 0 1 W R =0
I/O Read 1 1 0 R D =0
I/O Write 1 0 1 W R =0
(Interrupt -
Acknowledge) 1 1 1 I N T A =0
Halt Z 0 0 R D =Z,
Hold Z X X W R =Z
Reset Z X X I N T A =1
t
Power supply and frequency.

There are 3 important pins in the frequency control group.
X0 and X1: are the inputs from the crystal or clock
generating circuit.
The frequency is internally divided by 2.
So, to run the microprocessor at 3 MHz, a clock
running at 6 MHz should be connected to the X0
and X1 pins.
CLK (OUT): An output clock pin to drive the clock of the
rest of the system.
VCC &VSS :Power supply VCC= +5Volt & VSS= GND
reference.

Externally Initiated Signals

8085 has five interrupt signals that can be used to interrupt a
program execution.Four interrupts(RSTs and TRAP) are
automatically vectored(transferred) to specific memory locations
without any external hardware.
The microprocessor acknowledges an interrupt request by the
I N T A (interruptacknowledge)signal.
TRAP:It is a vectored, highest priority , non mask able interrupt.
After TRAP, restart occurs and execution starts from address
0024H.It need not be enabled, and
can not be disabled.


RST7.5,RST6.5,RST5.5: Restart interrupts :These are
vectored interrupts that transfer the program control to
specific memory locations. These are maskable interrupts
and have low priority than TRAP. They have higher priorities
then INTR interrupt .Among these three, priority order is
7.5,6.5, and 5.5.

INTR :This is lowest priority,general purpose , maskable
interrupt.

I N T A :This is used to acknoledge an interrupt.


HOLD: This signal indicates that a peripheral such as A DMA
(direct memory access) Controller is requesting the use of
address and data buses.When P receives HOLD signal it
completes current machine cycle and stops executing next
instruction, the microprocessor Relinquishes the control of
buses and allows the external peripheral to use them.

HLDA: This signal acnowledges the hold request.

READY:If the signal at the READY pin is low Microprocessor
enters into the wait state,and will wait for an integral no of clock
cycles until it goes high.This signal is used primarily to
synchronize slower peripherals with the microprocessor.


R E SE T I N : When the signal on this pin goes low, the program
counter is set to zero,the buses are tristated, and
MPU is reset.

RESET OUT: The signal indicates that the MPU is being
reset.This signal can be used to reset other devices.

SERIAL I/O PORTS

The 8085 has two signals to implement the serial
transmission:

SID(Serial input data)
SOD(Serial output data)

In serial transmission, data bits are sent over a single
line,one bit at a time.

Lecture -5
The 8085 Microprocessor Architecture

18
8085 Functional Block Diagram
8085 Architecture

It includes the ALU (Arithmetic/Logic Unit),
Timing and Control Unit,
Instruction Register and Decoder,
Register Array,
Interrupt control,
and Serial I/O Control.

THE ALU

The arithmetic and Logic unit performs the computing functions.It
includes the accumulator , temporary registers,the arithmetic and logic
circuits, and five flags.
The temporary register is used to hold data during an arithmetic/logic
operation.
The result is stored in Accumulator.
The flags are set or reset according to result of operation.

THE ALU

Accumulator
The accumulator is an 8-bit register that is a part of arithmetic/logic
unit (ALU).This register is used to store 8-bit data and to perform
arithmetic and logical operations. The result of an operation is
stored in the accumulator. The accumulator is also identified as
register A.

THE ALU

Flags Register

Flags Register:It is a group of 5 flip flops used to know status of
various operations done. The Flag Register along with Accumulator is
called PSW or Program Status Word.
S-Sign Flag:After the execution of an arithmetic or logic operation,if
bit D
7
of the result(usually in the accumulator) is 1,the sign flag is set.
Z-ZeroFlag:The zero flag is set if the ALU operation results in zero,
and the flag is reset if the result is not zero.This flag is modified by
results in the accumulator as well as in other registers.

S Z X AC X P X CY
THE ALU

Flags Register

AC-Auxiliary Carry :In an arithmetic operation ,when a carry is
generated by digit D
3
and passed on to digit D
4
,the AC is set.This flag
is used only internally for BCD operations and is not available for the
programmer to change the sequence of a program with jump
instruction.
P-Parity Flag: After an arithmetic or logical operation,if the result has
an even number of 1s,the flag is set.If it has odd number of 1s the
flag is reset.
CY-Carry Flag:If an arithmetic operation results in a carry,the carry
flag is set;otherwise it is reset.The carry flag also serves as a borrow
flag for subtraction.

S Z X AC X P X CY
Timing and Control

This unit synchronizes all the microprocessor operations with
the clock and generates the control signals necessary for
communication between the microprocessor and
peripherals.

Instruction Register and Decoder

When an instruction is fetched from the memory, it is loaded
in the instruction register.
The decoder decodes the instruction and establishes the
sequence of events to follow.
The instruction register is not programmable and cannot be
accessed through any instruction.

Register Array

Temporary Regiters: Two registers, called temporary registers
W and Z, are included in the register array. These registers
are used to hold 8 bit data during execution of some
instructions.However because they are used internally,they
are not available to the programmer.
Programmable Registers:
1. General Purpose Registers:
2. Special purpose registers:

Programmable Registers
Register Array

1.General Purpose Registers: There are six 8 bit general purpose
registers in 8085 namely B, C, D,E, H, L. These are used for various
data manipulations. They can also be combined as register pairs to
perform 16-bit operations: BC, DE, HL.
2.Special purpose registers: There are two special purpose registers in
8085:
1. SP :Stack Pointer.
2. PC: Program Counter.
1. SP :Stack Pointer: The stack pointer is a 16 bit register used as a
memory pointer. It points to a memory location in R/W memory,
called the Stack.

Register Array

1. SP :Stack Pointer(contd):The beginning of the stack is defined by
loading a 16 bit address in the stack pointer.
2. PC: Program Counter: The microprocessor uses the PC register to
sequence the execution of the instructions.The function of the
program counter is to point to the memory address from which the
next byte is to be fetched.When a byte(data byte or opcode) is being
fetched,the program counter is incremented by one to point to the
next memory location

Interrupt Control

Refer to interrupt signals explained in pin
diag lec7
Serial I/O Control

Refer to serial I/O signals explained in pin
diag lec7
Lecture -6
Microprocessor Communication and Bus Timing

The 8085 Bus Structure

Address Bus: Consists of 16 address lines A
0
A
15
. Operates in
unidirectional mode. The address bits are always sent from the MPU to
peripheral devices, not reverse.16 address lines are capable of
addressing a total of 2
16
= 65,536 (64k) memory locations. Address
locations: 0000 (hex) FFFF (hex)
Data Bus: Consists of 8 data lines D
0
D
7.
Operates in bidirectional
mode: The data bits are sent from the MPU to peripheral devices, as
well as from the peripheral devices to the MPU. Data range: 00 (hex)
FF (hex)



Control Bus: Consists of various lines carrying the control signals
such as read / write signals.

8085Cycles and States
Instruction Cycle: The time required to complete the execution
of an instruction.In the 8085, an instruction cycle may consist
of 1 to 6 machine cycles.
Machine Cycle: The time required to complete one operation
of accessing memory or I/O, or acknowledging an external
request.This cycle may consist of 3 to 6 T-states.
T- State: One subdivision of an operation. A T-state lasts for
one clock period.An instructions execution length is usually
measured in a number of T-states. (clock cycles).


Demultiplexing the Bus AD
7
AD
0

AD
7
AD
0
can carry address only in T1 T State after that
address will be lost from the bus.
Fig shows the schematic that uses a latch and the ALE signal to
demultiplex the bus.The bus AD
7
AD
0
is connected as the
input to the latch 74LS373.The ALE signal is connected to
enable(G pin) of the latch
The ALE goes high during T1 T State of any machine
cycle.When the ALE is high ,latch is transparent;it means that
output changes according to input .Thus low order address is
latched during T1 T state
When the ALE goes low in T1 T state , AD
7
AD
0
bus can carry
data.

Demultiplexing the Bus AD
7
AD
0

A
15
- A
8

D
O
D
7

D
0
- D
7

A15-A8
Latch
74LS373 AD7-AD0
ALE

G

A
7
- A
0

8085

ALE

Opcode Fetch Machine Cycle

Example: Illustrate the steps and the timing of data flow when
the instruction code 0100 0001(41H-MOV B,C),stored in
location 1000H,is being fetched.
To fetch the byte MPU performs following steps
Step1:The microprocessor places the 16 bit memory address
from the program counter(PC)on the address bus.
Step2:The control unit sends the control signal R D to enable
the memory chip.
Step3: The byte from the memory location is placed on the
data bus.
Step4: The byte is placed in the instruction decoder of the
microprocessor, and the task is carried out according to the
instruction
Opcode fetch MOV B,C.
T1 : The 1st clock of 1st machine cycle (M1) makes ALE high
indicating address latch enabled. Microprocessor loads low-
order address 00H on AD
7
AD
0
and high-order address 10H
on A
8
A
15
. Microprocessor identifies that it is an opcode
fetch cycle by placing 011 on the signals(IO/M =0,S1=1 and
S0=1)
T2 : During T2 clock, the microprocessor issues RD control
signal to enable the memory and memory places 41H from
1000H location on the data bus. T3 : During T3, the 41H is
placed in the instruction register and RD = 1 (high) disables
signal.

Opcode fetch MOV B,C.
T3 : During T3, the 41H is placed in the instruction register
and R D = 1 (high) disables signal.It means the memory is
disabled in T3 clock cycle. The opcode fetch cycle is completed
by end of T3 clock cycle.
T4 :After the T3 state ,contents of the bus A
8
A
15
are
unknown, and the data bus AD
7
AD
0
goes into high
impedance. Contents of The opcode are decoded in T4 , the
content of C-register is copied in B-register.

Memory Read Machine Cycle
Example: Suppose MVI B, is stored in memory location 1000 and
1001H.Illustrate the timings as these codes are executed.
Mnemonics Machine Code Memory Location
MVI B,05H 06H 1000H
05H 1001H
The MVI B,05H instruction requires 2-machine cycles (M1 and M2).
M1 requires 4-states and M2 requires 3-states, total of 7-states as
shown in Fig.
1.Opcode fetch: The first machine cycle is opcode fetch is identical in
bus timing with the previously discussed except for the bus
contents.

2. Memory Read Cycle:
T1 : The 1st clock of 2nd machine cycle (M2) makes ALE high
indicating address latch enabled. Microprocessor loads low-order
address 01H on AD
7
AD
0
and high-order address 10H on A
8

A
15
. Microprocessor identifies that it is a Memory Read cycle by
signals(IO/M =0,S1=1 and S0=0)
T2 : During T2 clock, the microprocessor activates R D control signal
to enable the memory and memory places05 H from 1001H
location on the data bus.
T3 : During T3, 8085 reads and stores the byte in the Register B.

Memory Write Machine Cycle
Pl make the diagram and explain what is
happening in memory write cycle which is of
3T states.
Lecture -7
Instruction Set 8085

Instruction Types
An instruction is a command to the microprocessor to perform given
task on specified data.
Each instruction has two parts: One is the task to be performed,
called the operation code (opcode),and the second is the data to be
operated on, called the operand. For example
Opcode Operand
MOV C,A
One byte Instruction includes the opcode and operand in the same
byte. example: ADD B, MOV M,D
In Two byte Instruction ist byte specifies the opcode and the second
byte specifies the operand. example: ADI 45H,MVI 87H
In a three byte instruction Ist byte specifies the opcode ,and the
following two bytes specify the 16bit address or 16 bit data.

Instruction Classification
Instructions can be classified in the following groups
Data Transfer Instructions
Arithmetic Instructions
Logical Instructions
Branching Instructions
Machine Control Instructions
Data transfer operation is a copying operation so contents of source
are not destroyed
No flags are affected by these group of instructions.
If the operand is a memory location indicated by M, its location is
specified by the contents of the HL registers.(Applicable to all
instructions in all groups)
MOV Rd, Rs This instruction copies the contents of the source
M, Rs register into the destination register;
Rd,M Example: MOV B, C or MOV B, M

MVI Rd, data The 8-bit data is stored in the destination register or
M, data memory Example: MVI B, 57H or MVI M, 57H


LDA 16-bit address The contents of a memory location, specified by
a16-bit address in the operand, are copied to
the accumulator Example: LDA 2034H

LD AX B/D Reg. pair The contents of the designated register pair
point to a memory location. This instruction
copies the contents of that memory location
into the accumulator. Example: LDAX B

LXI Reg. pair,16-bit data The instruction loads 16-bit data in the register
pair(BC,DE,HL,SP) designated in the operand.
Example: LXI H, 2034H


LHLD 16-bit address The instruction copies the contents of the
memory location pointed out by the 16-bit
address into register L and copies the contents
of the next memory location into register H.
Example: LHLD 2040H
STA 16-bit address The contents of the accumulator are copied
into the memory location specified by the
operand. Example: STA 4350H
STAX B/D Reg. pair The contents of the accumulator are copied into
the memory location specified by the contents
of the operand (register pair). Example: STAX B

SHLD 16-bit address The contents of register L are stored into the
memory location specified by the 16-bit address in
the operand and the contents of H register are
stored into the next memory location.
Example: SHLD 2470H
XCHG The contents of register H are exchanged with the
contents of register D, and the contents of register
L are exchanged with the contents of register E.
Example: XCHG
SPHL The instruction loads the contents of the H and L
registers into the stack pointer register.
Example: SPHL


XTHL The contents of the L register are exchanged with the
stack location pointed out by the contents of the stack
pointer register. The contents of the H register are
exchanged with the next stack location (SP+1);
Example: XTHL
PUSH Reg. pair The contents of the register pair designated in the
operand are copied onto the stack in the following
sequence. The stack pointer register is decremented
and the contents of the high order register (B, D, H,
A) are copied into that location. The stack pointer
register is decremented again and the contents of the
low-order register (C, E, L, flags) are copied to that
location. Example: PUSH B or PUSH PSW


POP Reg. pair The contents of the memory location pointed out by
the stack pointer register are copied to the low-order
register (C, E, L, status flags) of the operand. The stack
pointer is incremented by 1 and the contents of that
memory location are copied to the high-order register
(B, D, H, A) of the operand. The stack pointer register is
again incremented by 1.Example: POP H or POP PSW

What is a Stack?
The stack is an area of memory (R/W) identified by the programmer
for temporary storage of information. The stack is a LIFO structure.
The programmer defines the bottom of the stack and the stack grows
up into reducing address range. Given that the stack grows backwards
into memory, it is customary to place the bottom of the stack at the end
of memory to keep it as far away from user programs as possible.

In the 8085, the stack is defined by setting the SP (Stack Pointer)
register. LXI SP,FFFFH This sets the Stack Pointer to location FF FFH (end
of memory for the 8085). Information is saved on the stack by PUSH
instruction. It is retrieved from stack by POP instruction.

Initialization location can not be used for storage of data .

LXI SP FFFFH will store FFFFH in SP register, stack will be initialized
Suppose B=32,C=77 and PUSH B is executed.
PUSH B will store 32H in FFFE and 77H in FFFD.SP will become FFFD
Suppose next POP D is executed, it will move data into DE,D=32,E=77
SP will be again FFFF.

FFFB
FFFC
FFFD
FFFE
FFFF SP
77
32
X
B=32 C=77

OUT 8-bit port address The contents of the accumulator are copied
into the I/O port specified by the operand.
Example: OUT F8H

IN 8-bit port address The contents of the input port designated
in the operand are read and loaded into the
accumulator. Example: IN 8CH

ADD R The contents of the operand (register or memory) are
M added to the contents of the accumulator and the result is
stored in the accumulator. All flags are modified to reflect
the result of the addition. Example: ADD B or ADD M
ADC R The contents of the operand (register or memory) and the
M Carry flag are added to the contents of the accumulator
and the result is stored in the accumulator. All flags are
modified to reflect the result of the addition.
Example: ADC B or ADC M
ADI 8-bit data The 8-bit data (operand) is added to the contents of
the accumulator and the result is stored in the
accumulator. All flags are modified to reflect the
result of the addition. Example: ADI 45H
ACI 8-bit data The 8-bit data (operand) and the Carry flag are added
to the contents of the accumulator and the result is
stored in the accumulator. All flags are modified to
reflect the result of the addition. Example: ACI 45H
DAD Reg. pair The 16-bit contents of the specified register pair (BC,
DE,HL,SP) are added to the contents of the HL register
and the sum is stored in the HL register. If the result is
larger than 16 bits, the CY flag is set. No other flags
are affected. Example: DAD H
SUB R The contents of the operand (register or memory ) are
M subtracted from the contents of the accumulator, and the
result is stored in the accumulator. All flags are modified to
reflect the result of the subtraction. Example: SUB B ,SUB M
SBB R The contents of the operand (register or memory ) and the
M the Borrow flag are subtracted from the contents of the
accumulator and the result is placed in the accumulator. All
flags are modified to reflect the result of the subtraction.
Example: SBB B or SBB M
SUI 8-bit data
The 8-bit data (operand) is subtracted from the contents of
the accumulator and the result is stored in the accumulator.
All flags are modified to reflect the result of the subtraction.
Example: SUI 45H
SBI 8-bit data The 8-bit data (operand) and the Borrow flag are
subtracted from the contents of the accumulator and
the result is stored in the accumulator. All flags are
modified to reflect the result of the subtraction.
Example: SBI 45H
INR R The contents of the designated register or memory are
M incremented by 1 and the result is stored in the same
place. S,Z,P,AC are modified to reflect the result of
operation.CY is not modified Example: INR B or INR M
INX Rp The contents of the designated register pair(BC,DE,HL,SP)
are incremented by 1 and the result is stored in the same
place. No flags are affected. Example: INX H
DCR R The contents of the designated register or memory are
M decremented by 1 and the result is stored in the same place.
S,Z,P,AC are modified to reflect the result of operation.CY is
not modified Example: DCR B or DCR M

DCX Rp The contents of the designated register pair(BC,DE,HL,SP) are
decremented by 1 and the result is stored in the same place.
No flags are affected. Example: DCX H

DAA none The contents of the accumulator are changed from a binary
value to two 4-bit binary coded decimal (BCD) digits. This is
the only instruction that uses the auxiliary flag to perform the
binary to BCD conversion. All flags are altered to reflect the
results of the operation.
If the value of the low-order 4-bits in the accumulator is
greater than 9 or if AC flag is set, the instruction adds 6 to the
low-order four bits.
If the value of the high-order 4-bits in the accumulator is
greater than 9 or if the Carry flag is set, the instruction adds 6
to the high-order four bits.
Example DAA
CMP R The contents of the operand (register or memory) are compared
M with the contents of the accumulator. Both contents are
preserved . The result of the comparison is shown by setting the
flags of the PSW as follows:
if (A) < (reg/mem): carry flag is set
if (A) = (reg/mem): zero flag is set
if (A) > (reg/mem): carry and zero flags are reset.
S,P,AC are also modified to reflect the result of operation.
Example: CMP B or CMP M
CPI 8-bit data
The second byte (8-bit data) is compared with the contents of
the accumulator. Result as well as flags affected are same as
produced by CMP instruction.Example: CPI 89H
ANA R The contents of the accumulator are logically ANDed with the
M contents of the operand register or memory,and the result is
placed in the accumulator. S,Z,P are modified to reflect the result
of the operation. CY is reset. AC is set. Example: ANA B or ANA M
ANI 8-bit data
The contents of the accumulator are logically ANDed with the
8-bit data (operand) and the result is placed in the accumulator.
S, Z, P are modified to reflect the result of the operation. CY is
reset. AC is set. Example: ANI 86H
XRA R The contents of the accumulator are Exclusive ORed with
M the contents of the operand (register or memory), and the result
is placed in the accumulator. S, Z, P are modified to reflect the result
of the operation. CY and AC are reset.
Example: XRA B or XRA M
XRI 8-bit data The contents of the accumulator are Exclusive ORed with
the 8-bit data (operand) and the result is placed in the
accumulator. S, Z, P are modified to reflect the result of the
operation. CY and AC are reset. Example: XRI 86H
ORA R The contents of the accumulator are logically ORed with
M the contents of the operand (register or memory), and the
result is placed in the accumulator. S, Z, P are modified to
reflect the result of the operation. CY and AC are reset.
Example: ORA B or ORA M
ORI 8-bit data The contents of the accumulator are logically ORed with
the 8-bit data (operand) and the result is placed in the
accumulator. S, Z, P are modified to reflect the result of the
operation. CY and AC are reset. Example: ORI 86H
RLC none Each binary bit of the accumulator is rotated left by one
position. Bit D7 is placed in the position of D0 as well as in
the Carry flag. CY is modified according to bit D7.No other flag
is affected. Example: RLC
RRC none Each binary bit of the accumulator is rotated right by one
position. Bit D0 is placed in the position of D7 as well as in
the Carry flag. CY is modified according to bit D0.No other
flag is affected. Example: RRC
RAL none Each binary bit of the accumulator is rotated left by one
position through the Carry flag. Bit D7 is placed in the Carry
flag, and the Carry flag is placed in the least significant
position D0. CY is modified according to bit D7.No other flag
is affected. Example: RAL
RAR none Each binary bit of the accumulator is rotated right by one
position through the Carry flag. Bit D0 is placed in the Carry
flag, and the Carry flag is placed in the most significant
position D7. CY is modified according to bit D0. D7.No other
flag is affected. Example: RAR
CMA none The contents of the accumulator are complemented. No flags
are affected. Example: CMA
CMC none The Carry flag is complemented. No other flags are affected.
Example: CMC
STC none The Carry flag is set to 1. No other flags are affected.
Example: STC
JMP 16-bit address The program sequence is transferred to the memory
location specified by the 16-bit address given in the
operand. No flag is affected. Example: JMP 2034H
Jump conditionally The program sequence is transferred to the memory
operand based on the specified flag of the PSW. No
flag is affected.Example: JZ 2034H
Instruction Description Flag Status
JC 2100 Jump on carry CY = 1
JNC 2300 Jump on no carry CY = 0
JP 3400 Jump on positive S = 0
JM 5666 Jump on minus S = 1
JZ 2845 Jump on zero Z = 1
JNZ 7822 Jump on no zero Z = 0

Jump coditionally (cntd)
JPE 2424 Jump on parity even P = 1
JPO FC11 Jump on parity odd P = 0
CALL 16-bit address The program sequence is transferred to the memory
operand. Before the transfer, the address of the next
instruction after CALL (the contents of the program
counter) is pushed onto the stack. No flags are
affected. Example: CALL 2034H

Call conditionally The program sequence is transferred to the memory
operand based on the specified flag of the PSW as
described below. Before the transfer, the address of
the next instruction after the call (the contents of the
program counter) is pushed onto the stack.No flags
are affected. Example: CZ 2034H
CC 2441 Call on Carry CY = 1
CNC 7661 Call on no Carry CY = 0
CP 8896 Call on positive S = 0
CM 9099 Call on minus S = 1
CZ 2209 Call on zero Z = 1
CNZ 7690 Call on no zero Z = 0

Call conditionally(cntd)
CPE 2232 Call on parity even P = 1
CPO 2300 Call on parity odd P = 0
RET none The program sequence is transferred from the subroutine to
the calling program. The two bytes from the top of the stack
are copied into the program counter, and program execution
begins at the new address. No flags are affected. Example: RET
Return from subroutine conditionally Operand: none
The program sequence is transferred from the subroutine to
the calling program based on the specified flag of the PSW.
The two bytes from the top of the stack are copied into the
program counter, and program execution begins at the new
address. No flag is affected. Example: RZ

RC 2441 Return on Carry CY = 1
RNC 7661 Return on no Carry CY = 0
RP 8896 Return on positive S = 0
RM 9099 Return on minus S = 1
RZ 2209 Return on zero Z = 1
RNZ 7690 Return on no zero Z = 0
RPE 2134 Return on parity even P = 1
RPO 3200 Return on parity odd P = 0

PCHL none The contents of registers H and L are copied into the program
counter. No flag is affected. Example: PCHL
RST 0-7 The RST instruction is equivalent to a 1-byte call instruction
to one of eight memory locations depending upon the
number. No flag is affected. The addresses are:
Instruction Restart Address
RST 0 0000H
RST 1 0008H
RST 2 0010H
RST 3 0018H
RST 4 0020H
RST 5 0028H
RST 6 0030H
RST 7 0038H
No flags are affected by M-Control group instructions.

NOP none No operation is performed. The instruction is fetched and
decoded. However no operation is executed. Example: NOP
HLT none The CPU finishes executing the current instruction and halts
any further execution. An interrupt or reset is necessary to
exit from the halt state. Example: HLT
DI none The interrupt enable flip-flop is reset and all the interrupts
except the TRAP are disabled. No flags are affected.
Example: DI
EI none The interrupt enable flip-flop is set and all interrupts are
enabled. No flags are affected.Example: EI
RIM none This is a multipurpose instruction used to read the status of
interrupts 7.5, 6.5, 5.5 and read serial data input bit. The
instruction loads eight bits in the accumulator with the
following interpretations. Example: RIM
SIM none This is a multipurpose instruction and used to implement the
8085 interrupts 7.5, 6.5, 5.5, and serial data output. The
instruction interprets the accumulator contents as follows.
Example: SIM
Lecture -8
Addressing Modes 8085

Addressing Modes Each instruction requires certain data on which it has
to operate. There are various techniques to specify data for
instructions. These techniques are called addressing modes. Intel 8085
uses the following addressing modes:

1.Direct addressing
2.Register addressing
3.Register indirect addressing
4.Immediate addressing
5.Implicit addressing
Direct Addressing In this mode of addressing the address of the operand
Is given in instruction itself. Examples STA 2400H, IN 02H
Register Addressing In Register addressing mode operand is in one of the
general purpose registers. The opcode specifies the address of the
Registers in addition to the operation to be performed.
Examples MOVA,B,ADD B
Register Indirect addressing In this mode of addressing the address of the
operand is specified by a Register Pair. Examples MOV M,A,STAXB
Immediate addressing In immediate addressing mode the operand is
specified within the instruction itself. Examples MVIA,05H,ADI06H
Implicit addressing There are certain instructions which operate on the
contents of the accumulator.Such instructions do not require the
Address of the operand. Examples are: CMA,RAL,RAR etc

Assembly language programming
ALP will be /is being discussed in lab /tutorial
classes.


Unit 1 L4-L8

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