Registers are used to store multiple bits of information, such as a number, using a set of flip-flops. There are two main types of registers: shift registers, which allow the contents to be shifted, and parallel access shift registers. Shift registers load data in serial fashion and transfer the contents between flip-flops on each clock cycle. Counters are circuits that can increment or decrement a count using flip-flops and are used to design up/down counters.
Registers are used to store multiple bits of information, such as a number, using a set of flip-flops. There are two main types of registers: shift registers, which allow the contents to be shifted, and parallel access shift registers. Shift registers load data in serial fashion and transfer the contents between flip-flops on each clock cycle. Counters are circuits that can increment or decrement a count using flip-flops and are used to design up/down counters.
Registers are used to store multiple bits of information, such as a number, using a set of flip-flops. There are two main types of registers: shift registers, which allow the contents to be shifted, and parallel access shift registers. Shift registers load data in serial fashion and transfer the contents between flip-flops on each clock cycle. Counters are circuits that can increment or decrement a count using flip-flops and are used to design up/down counters.
Registers are used to store multiple bits of information, such as a number, using a set of flip-flops. There are two main types of registers: shift registers, which allow the contents to be shifted, and parallel access shift registers. Shift registers load data in serial fashion and transfer the contents between flip-flops on each clock cycle. Counters are circuits that can increment or decrement a count using flip-flops and are used to design up/down counters.
When a set of n flip-flops is used to store n bits of information, such as an n-bit number, we refer to these flip-flops as a register Two types of register: Shift Register Parallel Access Shift Register Shift Register A register that provides the ability to shift its contents is called a shift register Example four-bit shift register Shift its contents one bit position to the right Data bits are loaded in serial fashion Contents are transferred to the next flip-flop at each positive edge of the clock Figure 5.17. A simple shift register. D Q Q Clock D Q Q D Q Q D Q Q In Out t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 1 0 1 1 1 0 0 0 0 1 0 1 1 1 0 0 0 0 1 0 1 1 1 0 0 0 0 1 0 1 1 1 0 0 0 0 1 0 1 1 Q 1 Q 2 Q 3 Q 4 Out = In (b) A sample sequence (a) Circuit Q 1 Q 2 Q 3 Q 4 Parallel-Access Shift Register Figure 5.18. Parallel-access shift register. Example 1 What is the difference of a latch and a flip- flop? Latch is a level sensitive device. Flip-flops are edge sensitive devices.
Example 2 Answer Example 3 Answer Example 4 Answer Example 5 Answer Counters Circuits that can increment or decrement a count by 1 Designed using T and D flip-flops Asynchronous Counters: Up-Counter with T Flip-Flops Down-Counter with T Flip-Flops Synchronous Counters: Synchronous Counter with T Flip-Flop Synchronous Counter with D Flip-Flop
Counters Counters with Parallel Load Normally, initial count being equal to 0 Sometimes it is desirable to start with different count Other types of counters: BCD Counter Ring Counter Johnson Counter
Up-Counter with T Flip-Flops 3-bit counter from 0 to 7 Clock inputs are connected in cascade T input of each flip-flop is connected to constant 1 Because it counts in the upward direction, we call it an up-counter
Figure 5.19. A three-bit up-counter. T Q Q Clock T Q Q T Q Q 1 Q 0 Q 1 Q 2 (a) Circuit Clock Q 0 Q 1 Q 2 Count 0 1 2 3 4 5 6 7 0 (b) Timing diagram Down-Counter with T Flip-Flops Clock inputs of the 2 nd and 3 rd flip-flops are driven by the Q outputs of the preceding stages The circuit counts in the sequence 0,7,6,5,4,3,2,1,0,7,6 Because it counts in downward direction, we call it down-counter Figure 5.20. A three-bit down-counter. T Q Q Clock T Q Q T Q Q 1 Q 0 Q 1 Q 2 (a) Circuit Clock Q 0 Q 1 Q 2 Count 0 7 6 5 4 3 2 1 0 (b) Timing diagram