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Chapter4: Combinational Logic: Originally by Reham S. Al-Majed
Chapter4: Combinational Logic: Originally by Reham S. Al-Majed
Chapter4: Combinational Logic: Originally by Reham S. Al-Majed
Part 4
Originally By Reham S. Al-Majed
Imam Muhammad Bin Saud University
Outline
2
Multiplexer
Definition
Examples
MUX and Decoder.
MUX Expansion.
Circuit Implementation with MUX
DeMultiplexer
Definition
3
It is a cc that select binary information from one of many input
lines to single output line.
The selection of input line depends on selection lines.
Its ab consists of:
Inputs lines = 2
n
Output line = 1
Selectors (depends on number of inputs) = n
An active high or active low enable input (not all multiplexers have it)
I
2
n
-1
I
0
MUX
.
.
.
.
S
0
S
n-1
2
n
Inputs lines
Definition
4
I
0
I
1
I
2
I
3
0 0
MUX
Y=I
0
I
0
I
1
I
2
I
3
1 0
MUX
Y=I
1
I
0
I
1
I
2
I
3
0 1
MUX
Y= I
2
I
0
I
1
I
2
I
3
1 1
MUX
Y=I
3
Example 1
5
Design a 2-to-1 multiplexer:
1. 2 data inputs (I
0
,I
1
), 1 select input S , and 1 output (Y)
2. Truth table:
S I
1
I
0
Y
0 0 0 I
0
=0
0 0 1 I
0
=1
0 1 0 I
0
=0
0 1 1 I
0
=1
1 0 0 I
1
=0
1 0 1 I
1
=0
1 1 0 I
1
=1
1 1 1 I
1
=1
S Y
0 I
0
1 I
1
Example 1 (cont.)
6
3. Simplification:
Y = S I
0
+ S I
1
3. Diagram:
1 1
1 1 S
I
0
I
1
Example 2
7
Design 4-to1 MUX:
There are four data inputs two selection inputs S
1
,S
0
.
The input selected to be passed to the output depends on the minterm of
the input.
Y = S
1
S
0
I
0
+ S
1
S
0
I
1
+ S
1
S
0
I
2
+ S
1
S
0
I
3
minterm S
1
S
0
Y
m
0
0 0 I
0
m
1
0 1 I
1
m
2
1 0 I
2
m
3
1 1 I
3
m
1
m
2
m
3
m
0
Multiplexer and Decoder
8
The AND gates and inverters in the MUX resemble a decoder
circuit.
They decode selection input lines.
2
n
-to-1 line multiplexer is constructed from n-to-2
n
decoder.
Example:
4-to-1 MUX constructed from 2-to-4 decoder
Multiplexer Expansion
9
Design a 4-to-1 MUX with 2-to-1 MUXes only.
4-to-1 has 4 data input, 2 selection input, and 1 output.
2-to-1 has 2 data input, 1 selection input, and 1 output.
S
1
S
0
Y
0 0 D
0
0 1 D
1
1 0 D
2
1 1 D
3
D
0
D
1
MUX
MUX
D
2
D
3
MUX
Y
S
0
S
1
I
0
I
1
I
0
I
1
I
0
I
1